JPS6246576A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase the sectional area of a source line, and to reduce a resistance value by constituting the source line of a semiconductor region integrally formed with a source region in a field-effect transistor as a memory cell and organizing at least one part of the source line in junction depth than the source region. CONSTITUTION:Semiconductor regions 8 as source regions S are shaped in tegrally with semiconductor regions 8 is other field-effect transistors Q arranged in the row direction, and construct source lines SL common in plurality of memory cells.Sections among field insulating films 2 (regions surrounded by two-dot dash lines) disposed in the line direction are constituted of n<++> type semiconductor regions 8A having impurity concentration higher than the semiconductor regions 8 as the source regions S and junction depth deeper than those. Accordingly, the source lines SL are organized by the semiconductor regions 8A having impurity concentration higher than the semiconductor regions 8 and junction depth deeper than those, thus partially increasing the sectional areas of the source lines SL, then reducing the resistance values of the source lines SL.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit device, and in particular, to a semiconductor integrated circuit device having a nonvolatile memory function using field effect transistors as memory cells. It's about technology.

[Background Art] In a semiconductor integrated circuit device (hereinafter referred to as an EPROM) having an ultraviolet erasable nonvolatile memory function, a field effect transistor having a floating gate electrode is used as a memory cell. Information 110 IN is written into this memory cell by injecting hot electrons generated by a high electric field near the drain region into the floating gate electrode.

In this type of EPROM, the data line is composed of a low resistance wiring made of aluminum or the like, and the source line is composed of a semiconductor region formed integrally with the source region of a field effect transistor. The source line configured in this manner can be formed in the same manufacturing process as the source region and the train region of the field effect transistor, so it has the feature that the number of conductive layer forming steps can be reduced. Further, since this source line does not require a mask alignment margin for connecting five different conductive layers with the source region, it has the feature that it occupies a small area and can improve the degree of integration.

However, the present invention has discovered a problem in that, in a plurality of memory cells connected to a common source line, the efficiency of writing information differs from memory cell to memory cell, which lowers electrical reliability. The problem is that the source line is 30[Ω/
Since the source line has a sheet resistance value as high as 1000 yen, it causes non-uniform distribution of the potential of the source line, which occurs because the voltage mode during the write operation differs from memory cell to memory cell.

Note that the EPROM is described, for example, in Science Forum Co., Ltd.'s "Ultra LSI Device Handbook," published November 28, 1980, p.54 to p.56.

[Object of the Invention] An object of the present invention is to provide a technique that can improve the electrical reliability of a semiconductor integrated circuit device having a nonvolatile memory function.

Another object of the present invention is to provide a technique that can equalize the writing efficiency of information in memory cells and improve the mechanical reliability in a semiconductor integrated circuit device having a nonvolatile memory function. be.

Another object of the present invention is to provide a technique capable of reducing the resistance value of a source line connected to a memory cell in a semiconductor integrated circuit device having a nonvolatile memory function.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, in a semiconductor integrated circuit device having a non-volatile memory function, a source line is formed of a semiconductor region formed integrally with a source region of a field effect transistor serving as a memory cell, and at least a portion of this source line is connected from the source region. Also configured with deep bonding depth.

This increases the cross-sectional area of the source line.

Since the resistance value can be reduced, the potential distribution of the source line can be made uniform, and the information writing efficiency can be made uniform.

As a result, electrical reliability in the information writing operation can be improved.

Below, five configurations of the present invention will be described together with an embodiment in which the present invention is applied to an EPROM.

In addition, in all the figures of the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Example] A memory cell of an EPROM, which is an example of the present invention, is
It is shown in a plan view in the figure, and a cross-section taken along the line ■--■ in FIG. 1 is shown in FIG. In addition, Figure 1.

In order to make the configuration of this embodiment easier to understand, insulating films other than the field insulating film provided between each conductive layer are not shown.

In FIG. 1, 1 is a p-type semiconductor substrate made of single crystal silicon, 2 is a field insulating film, and 3 is a p-type channel stopper region. The field insulating film 2 and the channel stopper region 3 are provided on the main surface of the semiconductor substrate 1 between the semiconductor element forming regions or on the main surface thereof.

Field effect transistor Q which becomes the memory cell of EPROM
is the area of the semiconductor substrate 1 surrounded by the field insulating film 2
It is set in. That is, the field effect transistor Q
4. mainly depends on the first gate insulation. It is composed of a floating gate electrode 5, a second gate insulating film 6, a control gate electrode 7, and a pair of rl' type semiconductor regions 8 used as a source region S or a drain region.

The gate electrode 7 is connected to the electric field of the cells arranged in the column direction.
: A word line (
WL)? It constitutes A.

The semiconductor region 8 serving as the source region S is formed integrally with the conductor regions 8 of other field effect transistors Q arranged in one column direction, and constitutes a source line SL common to a plurality of memory cells. . Moreover, this source line SL has a higher impurity concentration and is deeper than the semiconductor region 8 which becomes the source region S between the field insulation @2 arranged in the row direction (the region surrounded by the two-point fi line in the first @). It is composed of an n'' type semiconductor region 8A having a junction depth.

In this way, by forming the source line SL with the semiconductor region 8A having a higher impurity concentration and a deeper junction depth than the semiconductor region 8, the cross-sectional area of the source line SL can be partially enlarged. The resistance value of SL can be reduced.

The semiconductor region 8A is formed through the direct contact forming process and step 5.
A semiconductor region 8 used as a normal source region S and a drain region is formed in a step. That is, it can be formed through the following steps. First, source fisL
An opening 4A is formed in the gate insulating film 4 in the formation region, and then a first layer polycrystalline silicon film for forming the gate electrode 5 is formed over the entire surface. Then, an impurity (phosphorus or arsenic) that reduces the resistance value is diffused into this polycrystalline silicon film.

This impurity is diffused into the main surface of the semiconductor substrate 1 through the opening 4A. Thereafter, the first layer polycrystalline silicon film is subjected to predetermined patterning to form a second Mj-th polycrystalline silicon film, and an impurity (phosphorus or arsenic) is doped to this second layer polycrystalline silicon film. Spread. And the second
Patterning is applied to the polycrystalline silicon film of the second layer and the first layer.

Gate electrodes 5 and 7 are formed. At this time, source line S
In order to introduce impurities into the L formation region in a later step,
It is preferable that no polycrystalline silicon film be present. After forming the insulating film 9 covering the gate electrodes 5 and 7 and the upper main surface of the semiconductor substrate 1, impurities (phosphorous or arsenic) are added to form the source region S, drain region and source line SL.
By introducing the semiconductor region 8 and the semiconductor region 8A, the semiconductor region 8 and the semiconductor region 8A can be formed. Further, the direct contact step may be performed between the step of forming the gate insulating film 6 and the step of forming the gate electrode 7 (the second layer of polycrystalline silicon).

In this way, by forming the semiconductor region 8A in the direct contact step and the conductor region 8 forming step, one
Since the semiconductor region 8A can be formed in the same manufacturing process that is incorporated in the normal manufacturing process, the number of manufacturing steps for the semiconductor region 8A can be reduced.

Further, the semiconductor region 8A may be formed in the semiconductor region 8 forming step and a new impurity introduction step without using the direct contact step.

Furthermore, it is desirable that the semiconductor region 8A be provided apart from the channel formation region of the field effect transistor Q. This is to prevent the impurity concentration of the semiconductor region 8 (source region S or drain region D) near the channel formation region from increasing more than necessary. With such a configuration, it is possible to suppress the extension of the depletion region formed from the semiconductor region 8 to the semiconductor substrate 1 side, so that the short channel effect can be suppressed.

Furthermore, by providing the semiconductor region 8A partially on the source line SL, that is, in the region surrounded by the two-dot chain line in FIG.
Since the junction capacitance formed between the semiconductor substrate 1 and the semiconductor substrate 1 can be reduced, the speed of the information read operation can be increased.

The semiconductor region 8A is 1, for example, the semiconductor region 8 is
When constructed with an implant of about 10" [at, oms/cm"] and a bonding depth of about 0.3 to 0.4 cm.

It is constructed with an impurity concentration of about 9 [ato+ms/cm'] and a junction depth of about 2.0 [μm].

10 is an insulating film covering a semiconductor element such as a field effect transistor Q, and 11 is a connection hole provided by removing the insulating film 10 above a predetermined semiconductor region 8.

Reference numeral 12 denotes a data line DL, which is electrically connected to the semiconductor region 8 through the connection hole 11 and is provided extending above the insulating film 10 in the row direction. and.

This data line (DL) is provided extending outside the region surrounded by the two-dot chain line in FIG. 1, that is, in a portion that does not intersect with the semiconductor region 8A. This is to reduce the floating area formed by the data linework 2 and the semiconductor region 8A.

In the above embodiment, the present invention was applied to a field effect transistor Q having a single drain structure, but the present invention applies to a field effect transistor Q having a double drain structure, LDD (Light
The present invention may also be applied to a field effect transistor having a drain structure.

Further, in the above embodiment, the semiconductor region 8A is provided in a part of the source line SL, but if the stray capacitance formed with the data line (DL) 12 is tolerable, the present invention
The semiconductor region 8A may be provided in the entire L.

Further, in the above embodiment, in order to suppress the short channel effect, the semiconductor region 8A with high impurity concentration and deep junction depth is not provided near the drain region, but the impurity concentration of the semiconductor region 8 near the channel forming region is According to the present invention, the semiconductor region 8A may be provided near the drain region as long as it is within the allowable range for the short channel effect. In this case, aluminum spikes can be prevented at the connection portion with the data line 12.

[Effects] As explained above, according to the novel technology disclosed in this application, the following effects can be obtained.

(1) In a semiconductor integrated circuit device having a nonvolatile memory function, a source line is formed of a semiconductor region that is formed integrally with a source region of a field effect transistor serving as a memory cell, and at least a portion of this source line is connected to the source region of a field effect transistor that is a memory cell. By configuring the junction with a deeper junction depth, the cross-sectional area of the source line can be increased, and the resistance value of the source line can be reduced.

(2) According to (1) above, the potential distribution of the source line can be made uniform, so that the information writing efficiency can be made uniform. In particular, E
In a PROM, the high voltage mode during a write operation can be made uniform in a plurality of memory cells connected to a source line, so that write efficiency can be made uniform.

(3) According to (2) above, electrical reliability in the information writing operation can be improved.

Although the invention made by the present inventor has been specifically explained based on the above embodiments, the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course, it can be modified.

For example, although the present invention was applied to an EPROM in the above embodiment, the present invention can also be applied to a semiconductor integrated circuit device having a non-volatile memory function other than EPR○M, such as a mask ROM.

[Brief explanation of drawings]

FIG. 1 is a plan view of a memory cell of an EPROM which is an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line ■--■ in FIG. In the figure, 4, 6... gate insulating film, 5, 7... gate electrode, 8, 8A... semiconductor region, 7A, WL... word line, 12. DL...data line, Q...field effect transistor, S...source region, D...drain region. SL: Source line.

Claims (1)

[Claims] 1. A semiconductor integrated circuit device having a nonvolatile memory function using a field effect transistor as a memory cell, wherein a semiconductor region of the same conductivity type as the field effect transistor is formed in the source region of the field effect transistor. 1. A semiconductor integrated circuit device, characterized in that a source line is integrally formed, and at least a portion of the source line is formed with a deeper junction depth than the source region. 2. The semiconductor integrated device according to claim 1, wherein the field effect transistor has a floating gate electrode and constitutes a memory cell with an ultraviolet erasable nonvolatile memory function. circuit device. 3. The source line as set forth in claim 1 is characterized in that a portion of the source line other than where it intersects with a data line connected to a memory cell is formed of a semiconductor region with a deep junction depth. Semiconductor integrated circuit device.