JPS6145627Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a digital AGC circuit that gives different time constants to rising and falling responses.

Various AGC circuits have been proposed to reproduce pulsed echoes and the like while distinguishing them from other noise.

In conventional analog AGC circuits, the input signal level has been increased,
Consideration is given to switching the time constants such as increasing the rising time constant and shortening the falling time constant in response to the rising or falling of a decreasing or pulsed signal.

However, in conventional digital AGC circuits, such considerations are not taken into account due to the circuit configuration. A conventional digital AGC circuit will be explained with reference to FIG.

In the figure, 1 is a digital delay circuit for delaying an input signal 11, and has a capacity of N words. The input signal 11 is delayed by the digital delay circuit 1, and is taken out as a signal 12 from a point corresponding to one-half the delay time of the digital delay circuit 1.

A digital adder circuit 2 having a capacity of N words adds the delayed signals X ₁ to X _N from the digital delay circuit 1 and outputs a signal 14 to the divider circuit 3 .

The division circuit 3 performs division using N as a divisor. Digital delay circuit 1, digital addition circuit 2, and division circuit 3 constitute an N-word moving average value circuit, and this output signal has a time constant corresponding to N words. The division circuit 4 divides the output signal 15 from the moving average value circuit and divides the delayed input signal 1.
Perform division using 2 as the dividend and use the AGC as the result.
It is output as an output signal 13. Since the aforementioned N is fixed and there is only one system of moving average value circuit, the number of time constants is limited to one type.

Next, the operation of the digital delay circuit will be explained with reference to FIG.

In FIG. 2, 1 is an input signal, which shows the waveform of the signal 11 in FIG. 1, and 2 shows the number of stages of the delay circuit 1 (indicating the moving average section) in correspondence with the time axis. 3 indicates the waveform 15 in FIG. 1, that is, the moving average value output. 4 is a signal waveform extracted from 1/2 the number of stages of the digital delay circuit 1, and shows the waveform 12 in FIG. 5 converts the input signal (12 in FIG. 1) delayed by the digital delay circuit 1 into the output signal (12 in FIG. 1) from the moving average value circuit.
The waveform of the output signal (13 in Figure 1) of the AGC circuit after division by 15) in the figure is shown. Since the conventional digital AGC circuit has only one type of time constant, the rising and falling responses to the input signal are equal, and depressions occur before and after the reproduced signal, as shown in FIG. 2. When reproducing such a signal as an image, an appropriate threshold value is set in order to avoid reproducing noise (not shown). Figure 2 5
The “ts” period shown in is the part that becomes a shadow on the video screen, and if there is another signal during this “ts” period,
If it is below the threshold value, a problem arises in that nothing is displayed as an image.

In other words, conventional digital
In the AGC circuit, the interval in which the moving average value is taken is fixed for the continuously sampled input signal, and since the circuit has only one system, the time constant of the AGC circuit is limited to one type, and the input signal It remains constant regardless of level changes, and if the time constant is set to improve the rising response, the falling response becomes poor, causing a problem in that a shadow appears on the image.

The purpose of this invention is to solve the problem of conventional digital AGC circuits where shadows appear on the image. The object of the present invention is to provide an AGC circuit in which constants can be selected.

In order to achieve the above object, the digital AGC circuit according to the present invention includes a digital delay circuit that delays an input signal wave for a certain period of time, a digital addition circuit that adds the input signal waves delayed for a certain period for a certain period, and The input signal wave from the digital delay circuit is the moving average value output that is the output of the dividing circuit of a moving average value circuit that is composed of a dividing circuit that performs division using the addition output as the dividend and the addition period as the divisor. In a digital AGC circuit that obtains an output by dividing the delayed output of Two division circuits are provided to divide these two types of addition outputs by values corresponding to the respective addition periods, and a moving average value output with a long moving average period and a moving average value output with a short moving average period are provided. On the other hand, a discrimination circuit receives a delayed signal of the input signal wave from the digital delay circuit and discriminates the rise and fall of the signal, and a discrimination signal output from the discrimination circuit and the In response to the moving average value output with a long moving average period and the moving average value output with a short moving average period, the moving average value output with a long moving average period is selected when the signal rises, and the moving average value output with a long moving average period is selected when the signal falls. a digital switching circuit that selects a short moving average value output, and two types of moving average value outputs corresponding to the rising and falling edges of the signal from the digital switching circuit, which outputs the same delayed signal that is applied to the discrimination circuit from the digital delay circuit. A division circuit that performs division by is provided, and the time constant is made long for the rising edge of the input signal wave, and shortened for the falling edge of the input signal wave.

According to the above configuration, the object of the present invention can be completely achieved.

The digital AGC circuit according to the present invention will be explained in more detail below with reference to the drawings and the like.

FIG. 3 is a block diagram showing an embodiment of the AGC circuit according to the present invention.

Digital delay circuit 1 is a circuit for delaying input signal 11 and has a capacity of N words. The input signal 11 is delayed by the digital delay circuit 1 and is taken out as a signal 12 from a point corresponding to one-half the delay time of the digital delay circuit 1. The digital adder circuit 2 has a capacity of N words and receives the delayed signal X ₁ from the digital delay circuit 1.
The signal 14 which is the result of adding ~X _L ~X _P ~X _N and the result of adding M words of the delay signal X _L ~X _P centered at a point corresponding to 1/2 the delay time of the digital delay circuit 1 Two types of addition output signals of the signal 16 are output. 3 and 5 are division circuits, the division circuit 3 uses N as a divisor, and the division circuit 5
has M as a divisor, and the digital delay circuit 1,
Digital addition circuit 2 and division circuits 3 and 5 constitute a moving average value circuit for N words and M words. 15 and 17 are output signals of moving average values, which have time constants corresponding to N words and M words, respectively.

The determination circuit 6 determines whether the signal 12 is on an increasing trend or not.
Or, it determines whether the signal has a decreasing tendency, that is, the rising edge or the falling edge of the pulse-like signal, and outputs a determination signal 18. The digital switching circuit 7 is a switching circuit operated by the determination signal.

The digital switching circuit 7 changes the moving average value output signal 15 (N
(having a time constant corresponding to a word) is selected and output as a signal 19. In the opposite case, that is, when the pulse signal corresponds to a falling edge, the digital switching circuit 7 outputs the moving average value output signal 17 (M
with a time constant corresponding to the word) and select signal 1
Output as 9.

The division circuit 4 performs division using the signal 19 selected by the digital switching circuit 7 as a divisor and the delayed input signal 12 as a dividend, and calculates the result.
Output as AGC output signal 13.

As a result, the time constant is selected so as to obtain optimal rise and fall response characteristics to changes in the input signal level, thereby reducing the shadow portion on the video screen.

Digital using conventional moving average circuit
The AGC circuit (see Figure 1) is composed of a digital delay circuit 1, a digital addition circuit 2, and a division circuit 3 and 4. Since the number of words for which the moving average is taken is fixed at a constant value, the AGC Since the time constant of is also constant, it was not possible to select the time constant so as to obtain the optimum rise and fall response characteristics with respect to changes in the input signal level, but the present invention can solve this problem.

Next, the operation of the circuit shown in FIG. 3 will be further explained with reference to FIG.

In FIG. 4, 1 is an input signal and shows the waveform of the input signal 11 in FIG. 2 and 3 represent the moving average range, 2 has a time constant corresponding to N words (1 to N), and the moving averaged output waveform is 4. This is the moving average value output 15 in Figure 3.
corresponds to the waveform of 3 has a time constant corresponding to M words (L to P), and its moving averaged output waveform is 5, which is the moving average value output 1 in FIG.
This corresponds to the waveform of No. 7. 6 is digital delay circuit 1
The input signal is delayed by 1/2 of the total delay amount, and corresponds to 12 in FIG.

7 shows the AGC output signal. In the period from t ₁ to t ₂ in this waveform 7, the moving average value output 4 (having a time constant corresponding to N words) is selected by the digital switching circuit 7 shown in FIG. 3, and the dividing circuit shown in FIG. This is the period used as the divisor of 4. The period from t ₂ to t ₃ is a period in which the moving average value output of 5 (having a time constant corresponding to M words) is selected and used as the divisor of the division circuit 4 in FIG. 3 to perform calculations.

From now on, the AGC output waveform of the conventional circuit (Figure 2, 5)
It can be seen that the portion corresponding to ts is shortened and improved in the AGC output waveform of the present invention in FIG. 4.

As explained above, the present invention improves the digital AGC circuit using the conventional moving average value circuit.
multiple moving average value circuits that have multiple time constants so that the interval for taking moving averages can be changed;
A circuit that determines the increase or decrease tendency of the input signal and the rise or fall of the pulsed signal and a digital switching circuit are added to select the optimal time constant according to changes in the input signal level. This has the effect of making the amplitude of the background noise uniform, reducing the deformation of the waveform of the pulsed signal, and reducing the portions that become shadows on the video screen.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a digital AGC circuit using a conventional moving average value circuit, Fig. 2 is a signal waveform diagram for explaining its operation, and Fig. 3 shows an embodiment of the digital AGC circuit according to the present invention. The block diagram and FIG. 4 are signal waveform diagrams for explaining its operation. 1... Digital delay circuit, 2... Digital addition circuit, 3, 4, 5... Division circuit, 6... Judgment circuit, 7... Digital switching circuit.

Claims (1)

[Scope of utility model registration request] a digital delay circuit that delays an input signal wave for a certain period; a digital addition circuit that adds the input signal waves delayed for a certain period for a certain period;
The input signal from the digital delay circuit is the moving average value output which is the output of the dividing circuit of the moving average value circuit, which is composed of a dividing circuit that performs division using this addition output as the dividend and the addition period as the divisor. In a digital AGC circuit that obtains an output by dividing the delayed output of a wave, two types of digital adder circuits are used, one with a long moving average period and one with a short moving average period, so that two types of moving average value outputs with different moving average periods can be obtained. Two division circuits are provided to divide these two types of addition outputs by values corresponding to the respective addition periods, and a moving average value output with a long moving average period and a moving average value output with a long moving average period are obtained. On the other hand, a discrimination circuit receives the delayed signal of the input signal wave from the digital delay circuit and discriminates the rise and fall of the signal, and a discrimination signal output from the discrimination circuit. In response to the moving average value output with a long moving average period and the moving average value output with a short moving average period, the moving average value output with a long moving average period is selected when the signal rises, and the moving average value output with a long moving average period is selected when the signal falls. A digital switching circuit selects a moving average value output with a short period, and when the same delay signal is applied from the digital delay circuit to the discrimination circuit, two types of moving average values corresponding to the rising and falling edges of the signal from the digital switching circuit are provided. A digital AGC circuit that is equipped with a divider circuit that performs division at the output, and has a long time constant for the rising edge of the input signal wave, and a short time constant for the falling edge of the input signal wave.