JPS59197935A - Digital processing type comparator circuit having hysteresis characteristic - Google Patents

Abstract

PURPOSE:To give a hysteresis characteristic to a digital comparator and to stabilize its comparing operation, by supplying an input signal to one input terminal of the comparator then delaying the output of the comparator by n bits and selecting two kinds of thresholds from the delayed output and supplying the result to the other input terminal of the comparator. CONSTITUTION:A digital input signal 1 is inputted into one side of a level comparator 101 and the output 2 of the comparator 101 is delayed by n bits by means of an n-bit shift register 102. The signal delayed by the register 102 is inputted into a 2-1 selector 103 and two kinds of thresholds, high level H and low level L, are selected, and then, the output 3 of the selector 103 is inputted into the other side of the comparator 101. A hysteresis characteristic is provided to the comparator 101. The comparator 101 discriminates the height of the level of a multiplexed data sequence and, when the level of the input signal 1 is gradually increased or decreased and the signal 1 contains a sound component, stabilizes its comparing operation.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a comparison circuit, and more particularly to a digital processing type comparison circuit for determining whether the level of a certain multiplexed data series is high or low.

Generally, analog comparison circuits can easily respond to large level changes, but when the input signal level gradually increases or decreases near the threshold, the comparison output becomes unstable. In order to solve this drawback, a comparison circuit having hysteresis characteristics is used, but a comparison circuit having hysteresis characteristics may also be required in a digital circuit.

The present invention seeks to provide a digital processing type comparison circuit having hysteresis characteristics that satisfies such requirements.

The comparison circuit according to the present invention has means for delaying the comparison output (n bits<n is a positive integer), and means for selecting and outputting two threshold values, large and small, according to the output of the delay means. If the data before the sample is thicker than the larger threshold, the 9th data is compared with the smaller threshold, and conversely, if the data of 1 sample is smaller than the smaller threshold, the 9th data is compared with the larger threshold. It is characterized by having a hysteresis characteristic by comparing it with . Of course, with a digital signal multiplexed to a multiplicity of n, it is possible to determine whether the level of a certain data series is high or low for each frame by comparing it with a threshold value selected based on the level of data n bits before. can.

Detailed explanation 1 of the present invention is given below.

The figure shows a block configuration of an embodiment of the present invention.

A level comparator 101 with digital input signal 1 as one input, an n-bit shift register 102 that delays output 2 of this comparator 101 by n pints, and high level H and low level depending on the output of this shift register 102. L
and a 2-1 selector 106 that selects and outputs two types of threshold values.

The output 6 of the selector 106 is used as the other input of the comparator 101.

When the input level of the comparator 101 is input 1≧output B, output 2 becomes °“1”, and when input 1 < output 5, output 2 becomes °“O”’
shall be. Here, when the level of the input 1 is lower than the high level H and the low level L, the output 2 is always '0', and at this time the selector 106 selects and outputs the threshold value of the high level H.

When the level of input 1 gradually rises and exceeds the high level H, output 2 of comparator 1o1 becomes "'1", and selector 1
In step 06, the low level L threshold is selected and output. As a result, the output 2 will maintain +111+ until the level of the input 1 drops to low level B. In addition, when the level of human power 1 gradually decreases, when it becomes lower than the low level L, output 2 becomes °'0'', and comparator 10
A threshold value of 1 switches to a high level H.

Therefore, if input signal 1 is a multiplexed signal with multiplicity n,
In the comparator 101, a certain channel Ch of a certain frame Fk
The level of the input data of i and the n-bit shift register 1
02, it was delayed by n bits. That is, a comparison is made with a threshold value selected by a comparison output based on the input data of the same channel Chi of frame Fk-1 one frame before.

Of course, in the case of n-1, a comparison is made with a threshold value selected by a comparison output based on input data one bit before.

As is clear from the above explanation, level comparison circuits with hysteresis characteristics, which are common in analog circuits,
It can also be realized in a digital circuit as a level comparison circuit that determines whether the level of a certain multiplexed data series is high or low. Therefore, according to the present invention, stable comparison can be performed even when the input signal level gradually increases or decreases or includes noise components.

[Brief explanation of drawings]

The figure is a block diagram of an embodiment of the present invention. Level H Level L

Claims (1)

[Claims] 1) a comparator with a digital input signal as one input;
What is the output of the comparator? It has means for delaying L bits (where n is a positive integer), and means for selecting and outputting two types of threshold values according to the output of the delay means, and the output of the selection means is applied to the comparator. A digital processing type comparison circuit, characterized in that it is connected to the other input.