JPS6145340A - Runaway monitor system - Google Patents

Abstract

PURPOSE:To detect early and assuredly the runaway of a microprocessor by comparing the information delivered for a reading or writing action with the information on the using condition of a memory area. CONSTITUTION:A microprocessor 1 gives an access to the address of a memory 2 and performs a reading or writing action. Here a circuit consisting of a selection circuit 4, an EX-OR circuit 5 and an AND circuit 6 compares the information on a reading or writing action given from a memory 3 storing the using condition of the memory 2 with information read out of the memory 3. Then an alarm output is delivered through a terminal 7 when no coincidence is obtained from said comparison.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a runaway monitoring system for a microprocessor used for data processing and the like.

Generally, a microprocessor (hereinafter abbreviated as MPU)
reads the program written in the memory, and sequentially executes, for example, data processing or device control according to the program.

At this time, for example, if MPLI executes a first instruction and then executes a certain task depending on the second instruction, it must next read the third instruction and execute a certain task depending on it. The first instruction may be read out again to perform work even though the first instruction is not executed, forming a closed loop.

Further, the address accessed for reading/writing may be outside the allocated memory area due to malfunction.

A runaway is defined as a state in which normal processing is not performed, such as a closed loop state due to MPU malfunction, and methods to monitor this runaway have already been implemented. In some cases, detection may not be possible, so there has been a demand for the development of a more reliable runaway monitoring system.

[Conventional technology]

FIG. 2(a) shows a block diagram of a conventional example of a runaway monitoring system.

In the figure, it is assumed that a program is written between addresses 0000 and 7FFF in a memory area of addresses 0000 to FFFF of a memory 2, for example, a read-only memory (hereinafter abbreviated as ROM).

On the other hand, the memory map circuit 3 is R(7M2 is 0000~
It is written that only addresses 0000 to 7FFF of the FFFF addresses will be used and the rest will not be used.

Now, when MPU 1 accesses ROM 2, the address signal is also sent to memory map circuit 3.

There, it is checked whether the sent address specifies an address within addresses 0000 to 7FFF, and if an address outside the specified address range is specified, this is detected and an alarm is sent to the outside.

Figure 2(C) is a block diagram of another conventional example.
shows an example of the program configuration.

In the same figure, the program written in the memory (not shown) includes clear signal sending commands a and b at predetermined time intervals (for example, 0.9 seconds) as shown in FIG. 2 (10). is provided.

Therefore, when the MPU 1 reads and executes the program written in the memory, a clear signal is applied to the counter 4 at intervals of 0.9 seconds.

On the other hand, when the counter 4 measures the clock for, for example, one second, it sends out a carry signal (which is used for an alarm).
Since a clear signal is applied from MPU 1 to counter 4 at intervals of 0.9 seconds, no alarm is sent to the outside.

[Problem that the invention seeks to solve]

As mentioned above, the runaway monitoring method shown in Figure 2 (al) accesses the specified address range, but if the instruction code and data that make up the program are read by mistake, the runaway of the NPU is detected because it is within the specified address range. Can not.

Furthermore, if a closed loop occurs in the program execution process as shown in (■) in Figure 2 (C), the clear signal sending command a does not reach the end even after one second has elapsed, so the clear signal is not sent and the MPU An alarm is sent to the outside as a runaway.

However, when the generated loop includes the above-mentioned point a and enters a loop state, the measured value of the counter 4 is periodically cleared, so an alarm is not sent to the outside, and runaway of the MPU cannot be detected.

That is, the conventional runaway monitoring system has a problem in that it may not be possible to detect the runaway depending on the state of the runaway.

[Means for solving problems]

The above problem is that when the address of the first memory is accessed from MPtl and read or written, the MP[
information sent regarding reading or writing from I;
According to the runaway monitoring method of the present invention, the runaway of the MPIJ is monitored by detecting coincidence or mismatch with information corresponding to the address read from the second memory that stores the usage state of the area of the first memory. resolved.

[Effect]

The present invention provides information from the MPU that executed reading or writing (for example, address signals, information such as whether the contents of the program read from memory are instruction codes or processing data),
Information on the usage status of this memory area (for example, information on the write area, read area, configuration of the written program, etc.)
A runaway of the MPU is detected by comparing information at the same address read from the MPU and detecting a match or mismatch.

This makes it possible to monitor runaway conditions that could not be detected conventionally, making it possible to perform runaway monitoring more reliably.

〔Example〕

FIG. 1(a) shows a block diagram of one embodiment of the present invention.
Figures (b) and (C) show usage diagrams of the memory areas of #1 ROM and #2 ROM, where the same reference numerals indicate the same objects throughout the plan.

First, as shown in FIG. 1(b), an instruction code is written at address 1000, data is written at address 1001, etc. in #lROM2 (first memory described in claims). .

On the other hand, as shown in FIG. 1 (C1), the memory #2RσM3 (second memory described in the claims) has #IROW
The configuration of the program written in the memory card 2 is, for example, "1" for the instruction code and "0" for the data, and is written in the order of addresses using 8 pins. Note that 8-bit information is written in one row of this memory.

For example, MPU 1 is #lROM2, for example, 1
When address 000 is accessed and the program written there is read, Mpt5i sends information that address -1000 has been accessed to #2 ROM3.

Therefore, #2 ROM3 contains 100 out of the written information.
Sends 8-bit data (for one line) including address 0 to the selected IP and route 4.

On the other hand, among the above information sent from liver υ-1, the lower 3
Depending on the combination of bits, any one of the eight bits can be extracted from the selection circuit 4, so the selection circuit 4 extracts and excludes only the first bit corresponding to the information at address 1000. EX-OR circuit (hereinafter abbreviated as EX-OR circuit) 5.

A status signal indicating whether the MPU 1 is reading the program read from the #1 ROM 2 as an instruction code or as data is added to this EX-OR circuit 5. If these two signals match, an EX-OR circuit is applied. The output of the circuit 5 is "O', and if there is no match, 1" is sent and added to the AND circuit 6.

A read signal indicating that the program has been read from #1ROM2 is applied from MPU i to another input terminal of this AND circuit 6, and if they match, "0" is sent to the terminal 7, and if they do not match, "1" is sent to the terminal 7.

Therefore, the output "1" when there is a mismatch is used as an alarm.

FIG. 1(d) shows a block diagram of another embodiment of the invention.

The difference between Figure 1(a) and Figure 1(d) is that the former uses only ROFI as the first memory, while the latter uses random access memory (hereinafter abbreviated as RAM) and ROM. Six examples are shown.

The basic idea is the same in the case of Figure 1(d), and the RA
MP for writing/reading in M8 or ROM9
The address accessed from u1 is sent to ROM 3, and RAM 8 and ROM written in this ROM are
From the information regarding the usage state of 9, the information of the corresponding address is read out in the same way as above and added to the AND circuit 6.

On the other hand, write/write from MPU 1 through OR circuit 10
The read signal is ANDed by an AND circuit 6, and if it does not match, 1'' is output from the terminal and an alarm is sent to the outside.

By using such a circuit to detect whether writing/reading is being performed in a predetermined memory area, runaway of the MPU can be detected more reliably at an earlier point in time.

〔Effect of the invention〕

As explained above, according to the present invention, MPU runaway can be detected more reliably at an early stage, so MPU runaway can be detected at an early stage.
It is possible to restore the PU to normal operation.

[Brief explanation of drawings]

FIG. 1(a) is a block diagram of one embodiment of the present invention, FIG. 1(b) and (0) are memory usage state diagrams, and FIG. 1(d) is a block diagram of another embodiment of the present invention. , Fig. 2(a) is a block diagram of a conventional example, Fig. 2(a) is a block diagram of another conventional example, Fig. 2(C1
shows the program configuration diagram. In the figure, 1 is an npu, 2.1tRO1'l, 4 is a selection circuit, 5 is an EX-OR circuit, 6 is an AND circuit, and 7 is a terminal. 〒1 Figure

Claims (1)

[Claims] When the microprocessor accesses the address of the first memory and performs reading or writing, the first memory stores the information sent out regarding the reading or writing from the microprocessor and the usage state of the area of the first memory. 1. A runaway monitoring system, characterized in that runaway of said microprocessor is monitored by detecting coincidence or mismatch with information corresponding to said address read from memory No. 2.