JPS6144463A - Emitter short-circuit structure of thyristor - Google Patents

Abstract

PURPOSE:To allow sufficient emitter short-circuit by a method wherein a short- circuit layer is buried in lattice form in the N<-> region in the neighborhood of a P-emitter layer, and the end is provided with a short-circuit hole layer which is connected to the anode. CONSTITUTION:An N<+> layer 1 of lattice form is buried in the NB<-> layer 2'' in the neighborhood of a PE 1'' by the epitaxial method, and the end of the N<+> layer 11 is provided with an N<+> layer 8''; then, one end 12 of the layer 11 is connected to the anode 5. When negative bias is impressed on a gate electrode 7, holes h' of the layer 2'' are rapidly led out of P<+> layer 3, and a depletion layer (a) is formed around the channel region. This construction enables electrons e' leaking out of an NS<-> 2 during channel-off to be easily led out by the elimination of the influence of the diffusion potential Vd between NS and PE because the emitter short-circuit part has been provided in the NB<-> layer, and the extinction time of element is reduced. Besides, the ON-voltage between the NB layer 2'' and the buried N<+> layer decreases, and the lead-out of carriers to the anode 5 is facilitated at the time of extinction, resulting in further reduction in extinction time.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a technology for increasing the speed of a thyristor that is used for high frequency control and has high switching performance, that is, a self-extinguishing thyristor.

<Prior Art> The following technologies are available for increasing the speed of so-called self-extinguishing thyristors such as electrostatic induction thyristors (hereinafter referred to as SI thyristors) and gate turn-off thyristors. In other words, (1) A method of forming p-type and n-type layers with appropriate concentration and depth on a semiconductor substrate such as silicon (2) A method of forming a heavy metal such as "tryP(+F@) on a semiconductor substrate" A method to diffuse and reduce the minority carrier lifetime within the same substrate.

(3) Emitter layer (
Different types of diffusion layers are arranged in parallel in the substrate, ζ beside the p-type or n-type of the emitter layer, n-type for the p-type of the emitter layer, and p-type for the n-type of the emitter layer. How to make it form.

Here, the above-mentioned (1
) In the method (2) above, in a semiconductor device in which emitter layers are provided on both surfaces of the semiconductor substrate, holes or electrons injected from the emitter layer can be injected into the device from the entire surfaces of both surfaces of the semiconductor substrate. The on-voltage generated when a layer-direction current is applied is low.

Therefore, since the heat generated by the element is low, it has the advantage of being less likely to break. However, carriers flowing from an adjacent n-type layer different from the p-type emitter layer, that is, electrons for the p-type emitter layer (hereinafter referred to as the 28th layer), and electrons for the n-type emitter layer (hereinafter referred to as the n8 layer) The hole is
When a thyristor is turned off by switching, for example, an n-type high resistance region (hereinafter n
In some cases, it is difficult for electrons flowing from a hole (referred to as mm) to disappear.

This means that even if electrons flow through the nmFJ and head towards layer I) 1, it is difficult for them to enter layer 28 due to the diffusion potential.

Therefore, the turn-off time becomes longer.

Therefore, in order to improve the switching performance of a thyristor, the emitter short-circuit structure described in item (3) above has been proposed.

To explain this item (3) with respect to pmffi, for example, if an n layer, that is, the same type of layer as the n1 layer, is formed next to the second layer, electrons that are difficult to flow into the PI layer at turn-off can easily pass through the n layer. and flows into the anode electrode. This reduces the turn-off time.

However, the 28 layers formed in the semiconductor substrate and n t
Since the m or n layer is divided into two adjacent layers, carrier injection from hf6 toward the 111 layer decreases, and the on-state voltage may increase.

That is, in order to improve switching performance, it is effective to increase the emitter short circuit density, but on the other hand, the on-voltage increases and power loss increases. The state of these self-arc-extinguishing thyristors is shown in Figures 4 and 5, taking the 8I thyristor as an example.
This will be explained based on the diagram.

Figures 4(a) and 4(b) are schematic cross-sectional views showing an example of a conventional 81 thyristor without an emitter short-circuit structure;
The figure shows the on state, the figure (b) shows the off state, and the figure 5 (a) shows the off state.
), (b) indicates the state.

tlc4 figure, figure 5 IC oil, 1, 1'1ipx
N, 2.

2' is the n1 layer, 2' is the n layer, and 3 is the p-type gate/? ! (
4 is the n3 layer, 5 is the anode electrode, 6 is the cathode electrode, 7 is the gate electrode, 8 is the n-layer layer of the shorting hole, h and h' are holes, and e and e' are electrons. ,a
is a depletion layer.

The S Esthyristor is a normally-on type element that is turned on when no bias is applied to the gate electrode 7 and turned off when a negative bias is applied to the gate electrode 7, and is turned off when no bias is applied to the gate electrode 7. There is a normally-off type element that is turned on when a positive bias is applied to 7.

The following will be explained using a normally-on type element as an example.

That is, in the normally-on type element shown in FIG.
A gate 3 is buried as a gate portion at the boundary between the n1 layer 2' and n1i2. The portion of nmfi2 surrounded by the p+ layer gate 3 is called a channel, and the load current mainly flows through this channel portion. An n1 layer 4 is superposed on top of the 11 layer 2', and a cathode electrode 6 is provided on the top surface of the n1 layer 4.

A pg layer 1 is provided below the n1 layer, and an anode electrode 5 is provided on the lower surface thereof. Furthermore, a gate electrode 7 is provided on the exposed surface of the layered gate 3.

Thus, as shown in FIG. 4(a), when a voltage is applied with the anode electrode 5 side as the positive electrode and the cathode electrode 6 side as the negative electrode, the S ethyristor is turned on, and the holes as carriers are transferred from pxffil to the channel. The electron e flows from nx layer 4 to nB! Flows to fa2.

Next, as shown in FIG. 4(b), when a negative bias is applied to the gate electrode 7, the S ethyristor is turned off. That is, the holes h' in the nl1 layer 2 are rapidly drawn out from the p+ layer 3, which triggers the formation of a carrier boule depletion layer a around the channel region. Therefore, a potential that prevents the movement of carriers is generated, the movement of carriers is stopped, and the element waits for the disappearance of minority carriers in rsfaQ, that is, holes h', and enters an OFF state.

On the other hand, nM2' flowing between channels while off
The electrons e' are not easily drawn out due to the influence of the diffusion potential vd generated between the nBn layer and the h layer 1. For this reason, the turn-off interval of the element becomes longer. This improvement measure will be explained in FIGS. 5(a) and 5(b). In FIG. 5, the n+ layer 8 is provided beside the p+J1' in parallel with the 21 layers 1', and also extends into the region of the 11 layers 2'. And on the bottom surface of 11+ layer 8, px
An anode electrode 5 is provided which is in contact with the layer 1'.

Thus, the potential generated between the 111 layer 2'' and the n+ layer 8 is reduced by providing the n+ layer 8, and carriers can move freely. Therefore, as shown in FIG. 5(b), During turn-off, carriers can be drawn out easily to the anode electrode 5, and the turn-off time can be much shorter than that shown in Fig. 4. Furthermore, if the short-circuit density of I'mJi! Since the injection is also reduced, the turn-off time can be further reduced.

Next, we will take up a conventional example of these schematic diagrams.
The explanation will be based on the drawings.

6(a), (b), and (C) show an example of the conventional one according to FIG. 4, where (a) is an external view of the cathode side, (b) is a state diagram of the emitter side, and (C) is a diagram of the state of the emitter side. (A sectional view taken along the line A-A in Figure 81, Figures 7 (a) and (b) are g5
An example of the conventional one is shown in the figure, (a) figure is a state diagram seen from the emitter side excluding the anode electrode, (b) figure is (a)
) is a view taken along line B-B in the figure.

In the figure, items with the same symbols as in Figure 3 have the same functions, so
The explanation will be omitted.

In Figure 6 (a), (b), and (C), nm
At the boundary between NI2 and nWI2', p+Ff&gates 3 are embedded in a grid pattern as shown in figure (C), and the part of the n1 layer 2 surrounded by the p+ layer agate 3 is called a channel, and the load Current mainly flows through this channel portion. An n1 layer 4 is superposed on top of the n layer 2', and a cathode electrode 6 is provided on the upper surface thereof.

28 layers 1 are provided below the n1 layer 2, and an anode electrode 5 is provided below the 28 layers 1. Furthermore, the peripheral portions of the n-layer 2' and the n-straw waste 4 are removed, and a lattice-shaped p+ layer agate 3 is formed.
The peripheral portion is exposed, and a gate electrode 7 is provided on this exposed surface. A large number of sections configured in this manner are arranged within a single semiconductor substrate to form an S ethyristor.

Here, the part surrounded by the dotted line in FIG. 3(b) shows the shape of the cathode electrode 6 side.

The difference between FIGS. 7(a) and 7(b) from FIG. 6 is that two layers 8 and 8' are provided as short-circuit holes.

In this example, as shown in FIG. Two layers 8° 8' are provided to short-circuit the anode electrode 5 and the anode electrode 5. Here, the first layer 8' is connected to the end of the second layer 8. shows a channel interval 1 of 6 μm, an n+ layer width m of 10 μm, a substrate diameter of 10 plates φ, and an on-current of 30 A.

In this way, if the width and pitch of the n-shaped paper resistance region are determined as necessary, the n1 layer 2 near the anode electrode 5 can be
The short-circuit resistance per unit area between ' and the anode electrode 5 can be set to an appropriate value and uniformly.

<Problems with Prior Art> However, as described above, although the turn-off time is shortened, the on-voltage increases, resulting in an increase in power loss.

<Objects and configuration of the invention> The present invention solves the above-mentioned problems, suppresses the on-voltage to a low level, and
An object of the present invention is to provide a thyristor emitter short-circuit structure that shortens turn-off time and improves switching performance.

In other words, in this device, the emitter configuration area is not reduced as much as possible, and the emitter short-circuit part is connected to the main current flow so that the carrier expulsion is performed smoothly, the emitter short-circuit is sufficiently filled, and the current flow is improved. It is embedded in the n1 layer near the 91st layer, which has a small number of layers, and has a layer of short circuit holes at the end thereof, and connects the short circuit holes to the anode electrode. The present invention will be described below with reference to FIGS. 1 and 2, taking an SI thyristor as an example.

<Embodiments of the Invention> FIGS. 1(a) and 1(b) are schematic cross-sectional views showing an example of an emitter short-circuit structure of an 81 thyristor according to the present invention.
Fig. 2(a) shows the on state, Fig. 2(b) shows the off state.

(b) shows one example of this, (a) is a state diagram seen from the emitter side excluding the anode electrode, (b) is a cross-sectional view taken along line C-C in (a), and Components with the same reference numerals as those in FIG. 4 have the same functions, so their explanation will be omitted here.

Figure 1 (a), (b) and Figure 2 (a), (
b) IC Oite, p.

In the nmff 12'' near the layer 1', a buried shorting layer formed by epitaxial growth, for example, a buried n+ layer 11, is provided in a lattice shape. A layer of shunt holes, for example layer 8', is provided at the end of buried layer 11;
One end portion 12 of this buried first layer 11 is connected to the anode electrode 5.

That is, next to the h layer 1#, a layer 8' is provided which is in contact with the 21 layer 1" and the n1 layer 1" and is arranged in parallel with the buried layer 11, and this n+ layer 8' is connected to each layer 11. An anode electrode 5 is provided on the lower surface of the h layer 1# and n''NJa'.

Thus, as shown in FIG. 1(a), the anode electrode 5@
When a voltage is applied with the positive electrode and the cathode ball 6 side as the negative electrode, the S ethyristor turns on, and holes as carriers flow from PMMS' to nM2' through the channel, and electrons e pass through the n1 layer 4. Flows from the n1 layer 2'' to the n1 layer 2''.

Next, as shown in FIG. 1(b), when a negative bias is applied to the gate electrode 7, the SI thyristor is turned off. In other words, the hole h' in the n1 layer 2'' is p''fE3
This causes a carrier boule depletion Jia+ to be formed around the channel region. Due to this, the 8I thyristor is turned off as explained in FIG. 4(b).

Here, Iζ, in the present invention, since the emitter short circuit is provided in the n1 layer 2# in the vicinity of the p1 layer l#, as explained in FIG. The electrons e' in the layer 2' are not affected by the diffusion potential 4 generated between the n1 layer and pmIWj and are easily drawn out, thereby shortening the turn-off time of the device.

Also, as shown in Figure 5, nj/?
5s, the carrier injection from i) m/i41' was reduced and the on-voltage increased, but px
Since the layer is no longer provided with an n+ calendar, the on-voltage becomes lower.

In other words, the on-voltage generated between the 111 layer 2'' and the buried n+ layer 11 is lower than that of the conventional one, and carriers can move freely.As a result, carriers are drawn out to the anode electrode 5 at turn-off. The turn-off time is reduced by 11 times.

Next, FIG. 3 shows the characteristics of the on-voltage VTM and turn-off time tgx with respect to the emitter short circuit rate X, comparing the conventional one and the one of the present invention.

That is, the emitter short circuit rate X is reduced. Based on this emitter short circuit rate X,
On-voltage VTM + of the conventional one and the one according to the present invention
The characteristics of the turn-off time stone were determined from experimental data as shown below. Note that the on-current ITM at this time is based on the case of 100 people. In addition, point Q is the on-voltage VTM according to the present invention.
, shows the turn-off time tB characteristic.

FIG. 3 shows this value in a graph. In other words, from these values, it can be seen that the device according to the present invention has a longer turn-off time and a lower turn-off time t if the on [lEVτM is lower than the conventional one
If M was high, the turn-off time tB would be short, which was not very desirable, but we were able to obtain a low and short appearance in both cases.

<Effects of the Invention> As explained above, according to the present invention, by providing the emitter short circuit in the vicinity of the 2g layer and in the nyrm, and connecting this emitter short circuit to the anode electrode, not only the on-voltage is reduced, but also the on-voltage is reduced. Turn-off and turn-on times are also shorter.

Therefore, since the emitter short-circuit structure of the self-extinguishing thyristor according to the present invention has high-speed switching performance, S
It can be applied to esthyristors, gate turn-off thyristors, etc., and is extremely useful in practice.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are schematic cross-sectional views showing an example of a short-circuit structure of a thyristor according to the present invention, in which FIG. 1(a) shows an on state, FIG. 1(b) shows an off state, and FIG. ), (
Figure b) shows an example of this, and figure (a) shows the state seen from the emitter side. (b) Figure is a sectional view taken along the line C-C in Figure (a), and Figure 3 is 8
Characteristic diagrams of I thyristors, Figures 4 (a) and 4 (b) are cross-sectional schematic diagrams showing an example of a conventional type without an emitter short-circuit structure, where (a) shows the on state and (b) the off state. , FIGS. 5(a) and 5(b) are schematic cross-sectional views having an emitter short circuit structure, where FIG. 5(a) shows the on state, FIG. 5(b) shows the off state, and FIGS. 6(a) and (b). , (C) shows an example of the conventional one shown in FIG. Cross-sectional view, Fig. 7(a), (
b) shows an example of the conventional one shown in Fig. 5, (a) is a state diagram seen from the emitter side, and (b) is a state diagram of B in Fig. (a).
- It is a sectional view taken along the line B. 1 , 1' , 11z, , , pm layer, 2 , 2
'...-flB layer, 5 =--anode electrode, 8.8'
...n+ layer, 11...buried 1 layer.

Claims (1)

[Claims] In the emitter short-circuit structure of a p- or n-gate three-terminal self-extinguishing thyristor, a buried short layer formed by epitaxial growth is provided in a lattice shape in an n-type high resistance region near the p-type emitter layer, and 1. An emitter short-circuit structure for a thyristor, characterized in that a layer of short-circuit holes is provided at an end of a buried short-circuit layer in order to short-circuit the short-circuit layers, respectively, and the layer of short-circuit holes is connected to an anode electrode.