JPS6013309B2 - Electrostatic induction type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrostatic induction thyristor in which a current path is made perpendicular to a substrate surface.

Conventional thyristors have only one base, which is a control electrode, and because the main current passes through this base, it is not possible to increase the impurity density in the base, which increases the base series resistance, and furthermore, the base acts as a main current path. Since it exists over the entire cross section of the area, the distributed capacitance is also large. As a result, the R·C time constant becomes large, so that the usable frequency limit is at most about 1 Hz.
That is, when the element transitions from the blocking state to the conducting state (hereinafter this state will be referred to as "evening on"), as is the case with the conventional SiriS.
), it is not possible to quickly control the expansion of the on-state region due to the large R・C time constant of the base, and the turn
I can't shorten the on time. Also, when transitioning from the conductive state to the inhibited state (hereinafter this state is referred to as turn-off).
This takes a long time because a large number of majority carriers and minority carriers injected into the junction in the on state move by diffusion, are absorbed by the control electrode, and disappear. Furthermore, since the series resistance of the base is large, the voltage applied to the base via the base electrode in order to turn it off does not reach a far region away from the base, and only slightly turns off the vicinity of the base electrode. Turn-off time is increased or turn-off is not possible. Therefore, it is almost impossible to cut off direct current, and even if it were possible, it would be limited to a device with a very small capacity. That is, conventional thyristors have many major drawbacks, such as being unable to operate at ultra-high speeds and with high power, being inefficient in high-speed operations, and being almost impossible to cut off direct current.

The present invention is intended to eliminate the above-mentioned conventional drawbacks, and its purpose is to provide a new electrostatic induction thyristor that is capable of ultra-high speed and high power operation, has high efficiency, and can also be applied to DC cutoff. It is in.

In addition to the electrostatic conduction type syringe of the present invention, the potential barrier generated in the intrinsic semiconductor region or low impurity density region that becomes the main current path is lowered by the control electrode, and a large number of positive currents are generated by rapidly injecting carriers. Due to the reduction in the electric field due to the mixed state of holes and electrons, the blocking state transitions to the conducting state, and by re-establishing this potential barrier, carrier injection is stopped, and in addition, the internally accumulated carrier By attracting A with an electric field and absorbing it into the control electrode, an operation is performed to return from the conducting state to the blocking state.Therefore,
The main current does not pass through the high impurity density region or metal electrode (hereinafter the high impurity density region or metal electrode is collectively referred to as gate) for controlling carriers.
The impurity density in the gate portion can be made as high as desired, and the portion occupied by the gate in the intrinsic semiconductor region or low impurity density region adjacent to the gate may be small.
Furthermore, by lowering the impurity density, the distributed capacitance of the gate capacitor becomes even smaller.In other words, the R/C timing of the gate can be reduced. Proceedings of the 13th Semiconductor Specialized Seminar, 1978
The purpose of this research was to further improve the excellent features of the ``Static Induction Field Effect Transistor (SIT)'' by Nishizawa, held from August 25th to 28th.

A conventional electrostatic induction field effect transistor has a structure shown in FIG.

In FIG. 1, 15 is an n-type semiconductor substrate which becomes a drain region, 2 is an n- type epitaxial growth layer, 3 is a p-type semiconductor region which becomes a gate region, and 4 is an n+-type semiconductor region which becomes a source region. , 5 is a surface protective film, 16 is a drain electrode connected to the drain region 15 with low resistance, 7 is a gate electrode t connected to the gate region 3 with low resistance, and 17 is a source electrode connected to the source region 1 with low resistance. , ○, S and G are the drain terminal, source terminal and gate terminal, respectively. The characteristics of the element having such a structure are as follows.

[1] In order to obtain triode vacuum tube characteristics, when the gate gap is kept the same, a channel region with high resistivity must be formed so that the channel is almost pinched off in the depletion layer.

■ In order to increase the frequency, it is necessary to reduce the carrier transit time from the source to the drain.

For this, sauce. The smaller the distance between drains, the better. But the gate. In order to reduce the capacitance between the drains, the distance cannot be made too small. [3} High voltage operation is advantageous for high output.

Gate to obtain high voltage resistance. Between drains and gates
The distance between sources must be increased. ■ For highly efficient operation, mutual conductor willow = (tengata)
vd=-road must be large.

However, △ld is the gate when the drain voltage Vd is constant. This is the variation in the drain current due to the voltage variation ΔVGs between the sources. Empirically, gm depends on the resistivity of the channel region and the gate structure. In the structure of FIG. 1, a result has been obtained that the lower the specific resistance of the n-type region 2, the larger the gm. '51 Current/voltage special curves exhibit triode-type non-saturation characteristics as shown in Figure 2. The current rises exponentially at first, and then the carrier density in the channel region increases due to the impurity concentration. When the magnitude becomes comparable to the concentration, the flow of current is limited by the space charge effect.

This state is reached around the voltage at which the depletion layer reaches the drain region. (2) The region from the gate to the drain acts as a drain resistance to reduce the gradient of current-voltage characteristics, so the distance and specific resistance of this region must be chosen small.

Parameters for current devices are selected in order to optimally design them based on the above-mentioned characteristics, but there are many compromises and optimal performance has not been achieved.

An object of the present invention is to provide an electrostatic induction thyristor that achieves high withstand voltage and large current without deteriorating frequency characteristics.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is an explanatory diagram for explaining the construction principle of this invention,
FIG. 4 is a sectional view showing an embodiment of the present invention.

In FIG. 3, 9 to 12 indicate the green color of the depletion layer spreading around the gate region 3 when the gate-anode voltages VGA are OV, 20V, 60V and 100V, respectively.
In this way, even if the gate bias is OV, the depletion layer
It is formed by the diffusion potential created between the p-n junction.
Even when the gate-anode voltage VGA increases, the depletion layer extends toward the anode in a manner similar to the gate structure. As the anode voltage increases further, the equipotential surface becomes parallel to the anode surface. The gist of the present invention is “Azord area 1
The junction surface with the n-type region 2 is made to have a shape similar to the equipotential surface between the maximum operating voltages. That is, the anode region 1 as shown in FIG. 4 is formed. In addition, the fourth
In the figure, the dotted line indicates the edge of the depletion layer. The advantages brought about by forming the anode region 1 in this way are as follows. [1] Is the cathode channel length extremely short?

Therefore, high frequency operation is possible. ■ High voltage operation remains the same) and large currents can flow.

In other words, ``Since the anode resistance is small, the current flows with a large gradient even in the high voltage region.t3} gm becomes large for channels with the same specific resistance. This is because the area where the space charge effect occurs can be made extremely small since it is a resistive layer.Next, we will discuss an example of a specific manufacturing process for realizing an electrostatic induction thyristor with such a configuration. As shown in a, a predetermined surface area of the p+ type substrate is selectively etched to form a recess la.

Next, as shown in FIG. 5b, a high resistivity n-type layer 2 is grown by vapor phase growth. At this time, a recess 2a is similarly formed on the recess la. Next, Qin suppuration 13 is formed on the n-type layer 2 by a CVD method, a sputtering method, or the like. At this time, since it is difficult for the pus 13 to be generated on the sloped portion of the recess 2a, that portion is formed thin and removed by light etching of the nitride film 13. Nitride film 13 on the slope part
The cross section after removal is shown in Figure 5c. Next, as shown in FIG. 5d, an oxide film 5 is selectively formed using the remaining nitrided pus 13 as a mask. Thereafter, using the selective oxide film 5 as a mask, the nitrided pus 13 on the recess 2a is removed and P-type impurities such as boron are diffused to form the gate region 3.

Next, the remaining nitride film 13 is removed using the selective oxide film 5 and the oxide film produced when forming the gate region 3 as a mask, and the n-type impurity is diffused to form the cathode region 4. After that, metals such as aluminum, titanium, platinum, and gold are vapor-deposited using a conventional method to form an anode electrode 6, a gate electrode, and a cathode electrode 8.The electrostatic induction thyristor completed through these steps is It is shown in Figure 5e.
The electrostatic conductive thyristor formed in this way is
It is possible to form the same not only for N-cha skin EL but also for P-channel element. Furthermore, as shown in FIG. 6, the p+ type region 1 shown in FIGS.
However, it may consist of two layers with different impurity concentrations, p and p. To obtain an element with such a structure, ``prepare a semiconductor substrate consisting of a two-layer structure of a p-type layer formed on a p+-type layer, and selectively etch only the p-type layer in the step shown in Figure 5a. Bye.

In this case, the etching rate in the p-type layer decreases due to the difference in impurity concentration, so the structure shown in FIG. 7 can be easily created. As described above, according to the present invention, a high-voltage, large-scale electrostatic induction type semiconductor device can be easily realized without deteriorating frequency characteristics.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a conventional static induction transistor.
Fig. 2 is a current/voltage characteristic diagram, Fig. 3 is an explanatory diagram for explaining the principle of the invention, Fig. 4 is a sectional view showing an embodiment of the invention, and Figs. FIG. 6 is a cross-sectional view of the process order showing one embodiment of the manufacturing method, and FIG. 6 is a cross-sectional view showing another embodiment of the present invention. In the figure, 1 is a p+ type semiconductor substrate, 2 is an n-type epitaxial growth layer, 3 is a p-type semiconductor region, 4 is an n-type semiconductor region, 5 is an oxide film, 13 is a nitrided pus, la and 2
a is a concave portion. Note that the same reference numerals in the figures indicate the same or corresponding parts. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1. A first semiconductor region of a first conductivity type with low specific resistance, a second semiconductor region of a high specific resistance of a second conductivity type formed on this first semiconductor region, and this second semiconductor region a third semiconductor region of a second conductivity type with low resistivity formed on the main surface of the semiconductor region, and is disposed in a part of the current path between the first and third semiconductor regions, and opens and closes the current path. a first conductivity type low resistivity gate region forming a space charge region, the gate region being formed at the bottom of a recess formed in the main surface of the second semiconductor region; 1
An electrostatic induction semiconductor device characterized in that a junction surface between the semiconductor region and the second semiconductor region is formed along the shape of the edge of the space charge region.