JPH025016B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a self-extinguishing thyristor, particularly a buried gate type electrostatic induction thyristor.

[Conventional technology]

As is well known, a thyristor with a conventional PNPN four-layer structure has a flat P-type base region that separates the N region of the high-resistance layer, which serves as the main current path and shares the breakdown voltage. becomes the control area. In this case, the main current will flow within the control region itself, and carriers will accumulate in this P-type control base region, which takes time to draw out.

Also, since the carrier is injected into the control area,
In order not to reduce the efficiency of the implantation, the impurity density in the control region cannot be made too high, and the layer cannot be made too thick. Therefore, the lateral resistance of the base region is increased, which slows down the switching time.

Static induction thyristors (hereinafter referred to as SI thyristors) are recently invented thyristors capable of high-power, high-speed switching, and have a gate shape that differs from conventional thyristors with a four-layer structure. .

FIGS. 4 and 5 are schematic diagrams of the cross-sectional structure of existing SI thyristors, showing unit elements, and in reality, a large number of these unit elements are connected in parallel to form an SI thyristor.

Due to the difference in gate structure, the one in Figure 4 is called a buried gate type, and the one in Figure 5 is called a surface gate type.Although each has performance characteristics, the operating principle is the same, and the parts with the same function are are given the same reference numerals.

To explain the structure of the buried gate type SI thyristor shown in Fig. 4, the anode 2 consisting of P ⁺ layer
A PIN diode is formed between a cathode 1 made of an N ⁺ layer and a base region 3 made of an N ^- layer with low N type impurities, and a PIN diode is formed in a portion of the base region 3 near the cathode 1 called a channel 5 ^. A gate 4 consisting of a P type low resistance region P ⁺ layer surrounding the layer.
It has a structure with Here, 6, 7, 8
represent a cathode electrode, an anode electrode, and a gate electrode provided on the surfaces of the cathode 1, anode 2, and gate 4, respectively.

The surface gate type SI thyristor shown in Figure 5 is
It has a planar structure in which the gate 4 is formed on the same surface as the cathode 1, and in this case the channel 5 is the area shown in the figure.

Figure 6 is a circuit diagram for explaining the operation when opening and closing a DC circuit using the embedded gate type SI thyristor shown in Figure 4.It is constructed by connecting many unit elements of Figure 4 in parallel. Thyristor 11 and
A main circuit is formed by the main power supply 13 and the load 12, and the cathode electrode 6 and gate electrode 8 of the SI thyristor 11 are connected via the switch 16 to the electrode 14 whose positive electrode is connected to the gate electrode 8, and the switch 17. A control circuit is formed so that the negative electrode is connected to the power source 15 connected to the gate electrode 8.

In FIG. 6, if switch 17 is opened and switch 16 is closed, the gap between gate 4 and cathode 1 is
The P ⁺ N ^- N ⁺ junction is forward biased and the cathode 1
Electrons from the N ⁺ region and holes from the P ⁺ layer of the gate 4 are injected as carriers into the N ^- layer of the channel 5, so that the carrier density of the channel 5 increases significantly and becomes highly conductive.

At this time, from the N ⁺ area of cathode 1 to channel 5
Some of the electrons injected into the main power supply 13
is accelerated by the electric field caused by the impurity concentration, moves through the N ^- layer of the base region 3 with a low impurity concentration, and is accumulated in the N ^- layer portion of the base region 3 directly under the P ⁺ layer of the anode 2 . The electrons accumulated in this part promote the injection of holes from the anode 2 to the base region 3, and the holes injected into the base region 3 pass through the channel 5 and reach the cathode 1, and further injection of electrons. urge.

In this way, the base region 3 consisting of the lightly impurity N ^- layer is filled with a high concentration of carrier and exhibits a low resistance. This process is the turn-on of the SI thyristor, and in the on steady state, the channel 5 of the base region 3 of the SI thyristor is filled with electrons and holes, and the holes are accumulated in the gate 4 of the P ⁺ layer.

Next, the SI thyristor 11 in this state
The operation when turning off is described below.

In FIG. 6, when switch 16 is opened and switch 17 is closed, the gap between gate 4 and cathode 1 is
The P ⁺ N ^- N ⁺ junction is reverse biased. At this time, P ⁺
The holes accumulated in the N ^- layer of the gate 4 and the base region 3 near the gate 4 are transferred from the gate electrode 8, and the electrons in the cathode 1 and the N ^- layer of the base region 3 near the cathode 1 are transferred from the gate electrode ⁸ . It is swept out from the cathode electrode 6 as a reverse current of the gate 4.

As a result, N ^- of the base region 3 near the gate 4
A depletion layer is formed in the layer, and as the depletion layer grows, the channel 5 becomes completely depleted, and the depletion layer further extends through the base region 3 toward the anode 2. On the other hand, as the depletion layer in the base region 3 grows, the voltage between the anode 2 and the cathode 1 begins to increase and finally becomes equal to the voltage E _S of the main power supply 13.

At this time, the base region 3 near the anode junction 9
In the N ^- layer, there are many carriers (mainly holes) that remain without being swept out of the gate 4, and these carriers flow through the base region 3 and are swept out of the gate 4 of the P ⁺ layer. The carrier flow at this time is a Hall current, which is observed as a current flowing from the anode electrode 7 to the gate electrode 8 immediately after turn-off, and is called a tail current.

During the period when the tail current flows during turn-off, the anode voltage is generally restored to the circuit voltage, so a large power loss occurs in the device at this time. Therefore, in high-voltage, large-current devices, reduction of tail current has been a conventional issue.

[Problem that the invention seeks to solve]

As a countermeasure against such problems, structures shown in FIGS. 7 and 8 have been known. 7 and 8 are schematic diagrams showing the cross-sectional structure of different SI thyristors, each showing a unit element, and the same reference numerals as in FIG. 4 indicate parts having the same function.

The structure shown in FIG. 7 has a structure in which an N-type layer called a buffer layer 10 of medium resistivity is sandwiched between the P ⁺ layer of the anode 2 and the N ^- layer of the base region 3. This is the same as the buried gate type SI thyristor shown in Figure 4. When the depletion layer spread in the base region 3 made of the N ^- layer reaches the buffer layer 10, the buffer layer 10 becomes a PIN structure in which the spread width of the depletion layer is restricted due to the relatively high impurity concentration. .

Therefore, the required
Since the thickness of the base region 3 of the N ^- layer is small, the forward voltage drop is reduced, and the lifetime of the remaining carrier can be shortened by that amount by performing gold diffusion into the N ^- layer of the base region 3. Tail current decreases.

The structure shown in FIG. 8 is known as an anode short-circuit structure, in which the P ⁺ layer of the anode 2 and part of the N ^- layer of the base region 3 are directly connected to the anode electrode 7. Other than that, it is the same as the buried gate type SI thyristor shown in FIG.

With this structure, hole injection from the P ⁺ layer of the anode 2 to the N ^- layer of the base region 3 is suppressed, and even during the tail period at turn-off, the base region directly under the P ⁺ layer of the anode 2 is suppressed. of
The electrons accumulated in the N ^- layer pass directly to the anode electrode 7 from the short circuit where the N ^- layer itself contacts the anode electrode 7, and the holes in the N ^- layer also return to the P ⁺ layer of the anode 2, so that the remaining carrier This has the effect of making it disappear faster.

Furthermore, an SI thyristor called a dual-gate SI thyristor has already been made public. FIG. 9 is a schematic diagram showing the cross ^- sectional structure of a unit element of a dual ^- gate type SI thyristor. A second channel 19 having the same function as the channel 5 by the gate 4 on the side is provided, and the same reference numerals as in FIG. 4 indicate parts having the same function.

At turn-on, the second gate 18 and the anode 2
A forward bias is applied between the two layers to facilitate injection of holes from the P ⁺ layer of the anode 2 to the N ^- layer of the base region 3.

At turn-off, the second gate 18 and the anode 2
By applying a reverse bias between the two channels, electrons in the vicinity of the second channel 19 are swept out to the N ⁺ layer of the second gate 18, and holes are swept out to the P ⁺ layer of the anode 2, so that the vicinity of the second channel 19 is rapidly depleted.

As a result, a significant improvement in switching performance is expected.

The examples shown in FIGS. 7 to 9 described above are all effective in reducing the tail current at the time of turn-off, but they all have problems.

For example, in the SI thyristor with the buffer layer 10 shown in ^FIG . Current flows.

In addition, in the SI thyristor with the anode short-circuit structure shown in Fig. 8, there is a problem in the method of determining the short-circuit ratio of the anode 2, and the dimensions of the unit element become fine as in the SI thyristor, and the base region made of N ^- layer As the thickness of 3 increases, effective design becomes more difficult.

Furthermore, although using the dual gate type SI thyristor shown in Figure 9 is extremely effective,
Forming the microstructured channel 5 and the second channel 19 on both the cathode 1 side and the anode 2 side of the base region 3 is a rather difficult manufacturing problem.

[Purpose of the invention]

The present invention has been made to solve these problems, and provides an SI thyristor with low forward voltage drop and low tail current, and which is easy to manufacture.

[Summary of the invention]

Fig. 1 is a schematic diagram showing the cross-sectional structure of a unit element of the SI thyristor according to the present invention, and an actual SI thyristor chip has a structure in which a large number of these unit elements are connected in parallel, and Fig. 3 shows an example of the cross-sectional structure. The same reference numerals as in FIGS. 4 to 9 indicate parts having the same functions.

This unit element is similar to the conventional anode 2 shown in FIG.
The shape is almost the same as that in which a buffer layer 10 having an intermediate resistivity is sandwiched between the P ⁺ layer of the base region 3 and the N ^- layer of the base region 3. They are exposed on the same surface, and a second gate electrode 20 is provided on this exposed surface.

It is similar to the conventional dual gate type SI thyristor shown in FIG. 9 in that it has a second electrode.
However, in the case of the dual-gate SI thyristor shown in Fig. 9, ^the second
A second channel 19 exists between the gates 18, but in the SI thyristor of FIG. 1 according to the present invention, the N-type buffer layer 10 is characterized by having the same planar structure as the gate layer of the conventional thyristor.

Next, the operation will be explained. FIG. 2 is a circuit diagram for explaining the operation when opening and closing a DC circuit using the SI thyristor according to the present invention, and parts having the same functions as those in FIG. 6 are denoted by the same reference numerals. Reference numeral 11' indicates an SI thyristor according to the present invention in which a large number of unit elements shown in FIG. 1 are connected in parallel. In addition to the control circuit shown in FIG. 6, the anode electrode 7 and second gate electrode 20 of the SI thyristor 11' are connected to a power source 14' whose positive electrode is connected to the anode electrode 7 via a switch 16', and a switch 17'. A control circuit is added by connecting the negative electrode to a power source 15' connected to the anode electrode 7 via the anode electrode 7.

To turn on the SI thyristor 11', open the switches 17, 17' and close the switches 16, 16' at the same time. At this time, between gate 4 and cathode 1
P ⁺ N ^- N ⁺ junction, anode 2 and second gate electrode 2
The P ⁺ N junctions between 0 are forward biased together and the central
A hole is formed from the anode 2 to the base region 3 of the N ^- layer.
Electrons are injected from cathode 1.

The carrier injected into the base region 3 of the N ^- layer is
Accelerated by the electric field from the main power source 13, electrons flow to the anode 2 and holes flow to the cathode 1, so the SI thyristor 11' is rapidly turned on.

Next, SI thyristor 1 in this state
1', when switches 16, 16' are opened and switches 17, 17' are simultaneously closed, an NP ⁺ junction between the second gate electrode 20 and the anode 2 and an N ⁺ N ^- P between the cathode 1 and the gate 4 are formed. ⁺ junctions are reverse biased together.

At this time, a depletion layer is formed in the channel 5 and its vicinity, and spreads to the base region 3 made of the N ^- layer as shown in the SI thyristor 11 shown in FIG.
However, since the P ⁺ N junction on the anode 2 side is reverse biased, the buffer layer 10
The electrons in the N layer of are swept out by the second gate electrode 20, and the holes are swept out to the P ⁺ layer of the anode 2, and the P ⁺ N junction reversely recovers.
Injection of holes into ^N- stops immediately.

Most of the carriers present in the base region 3 made of the N ^- layer in the conductive state are swept out through the gate 4 as the depletion layer in the channel 5 portion expands, so that after the depletion layer has sufficiently expanded to block the circuit voltage. The current flowing is only a current for sweeping out a few holes remaining on the anode 2 side of the N ⁻ layer of the base region 3 to the gate 4 . That is,
Great effect in reducing tail current.

Furthermore, if the design is such that the expansion of the depletion layer in the N ^- layer of the base region 3 due to the circuit voltage reaches the N layer of the buffer layer 10, it is possible to reduce the tail current to zero.

The above explanation is based on the gate electrode 8 and the second gate electrode 2.
I explained that the timing of the operation of 0 is the same, but
For example, before closing switch 16, switch 1
6' may be closed, and after holes are injected into the N ^- layer of the base region 3, the switch 16 may be closed. Also, after the switch 17 is closed at turn-off and the storage carrier on the cathode 1 side has been swept out,
It is also possible to close the switch 17' and flush out the storage carrier on the anode 2 side. In these cases, since there is no need to align the operations of the gate control circuits, the configuration becomes easier.

Further, as a method of using only a part of the function of the second gate electrode 20, for example, in order to reduce the tail current, the second gate electrode control circuit may be provided with only the power supply 15' and the switch 17' shown in FIG. Alternatively, the second gate electrode 20 may be left open and used in the same manner as shown in FIG. How to use these can be arbitrarily selected depending on the purpose.

The above explanation has all been about the improvement of the conventional buried gate type SI thyristor shown in Fig. 4, but the conventional surface gate type SI thyristor shown in Fig. 5 has been improved.
It can also be applied to a thyristor, and almost the same effect can be obtained.

〔Example〕

Next, an example of fabricating an SI thyristor according to the present invention will be described, taking as an example one having a buried gate structure shown in FIG.

First, the bond forming process will be explained. As a silicon material, the impurity density is approximately 5×10 ¹³ atoms/cc.
N-type silicon 3 with high resistivity and a thickness of approximately 300 μm.
Impurity density on one side of a is approximately 5×10 ¹⁶ atoms/cc
N-type medium resistivity buffer layer 1 with a thickness of about 30 μm
A material on which 0 has been formed in advance is prepared. here,
The buffer layer 10 having a medium specific resistance can be easily formed by a known epitaxial growth method.

Next, on the other surface of the high-resistivity N-type silicon 3a, the gates 4 (center part) and 4' (attachment part of the gate electrode 8) of the low-resistance P ⁺ layer are formed into a channel 5 which is designed and planned in advance. A plurality of pieces are selectively formed so as to secure an interval of . The gates 4 and 4' have a surface impurity density of about 2×10 ¹⁹ atoms/cc, a junction depth of about 15 μm, and a channel spacing of about 4 to 10 μm.

Simultaneously with the formation of the P ⁺ layer of the gate, the anode 2 made of the P ⁺ layer can also be formed. The surface impurity density and junction depth of the anode 2 are approximately at the same level as those of the gates 4 and 4', and the anode 2 is located at a location facing the channel 5. Such selective formation of the gates 4, 4' and the anode 2 is achieved by oxidation, diffusion, and photolithography techniques using, for example, boron, which has a masking effect on the oxide film as a known P-type impurity. It can be done easily.

Thereafter, in order to bury the gate 4, an N-type epitaxial growth layer 3b having a thickness from line AA to line BB in FIG. 2×10 ¹⁴ atoms/cc
It is formed to a thickness of about 20 μm. Therefore, the N-type silicon 3a as the material and the epitaxial growth layer 3
b forms the base region 3 of the N ⁻ layer.

An N-type low resistance layer is selectively formed on the surface of this epitaxial growth layer 3b and the surface of the N-type medium specific resistance buffer layer 10. This N-type low resistance layer has a surface impurity density of about 5×10 ¹⁹ atoms/cc and a junction depth of about 7 μm. The N type low resistance layer provided in the epitaxial growth layer 3b is the cathode 1, and the N type low resistance layer 21 provided in the buffer layer 10 is connected to the aluminum electrode forming the second gate electrode 20. Provided to improve ohmic contact.

The selective formation of such an N-type low resistance layer is
N-type impurity has a masking effect on the oxide film,
This can be easily accomplished, for example, by using phosphorus and using known oxidation, diffusion, and photolithography techniques.

Next, the electrode formation process will be explained. Each electrode is formed in the following manner on the wafer on which the bond has been formed as described above. First, in order to form an electrode on the gate 4' for external conduction, the epitaxial growth layer 3b is dug up to the position where the gate 4' of the P ⁺ layer is exposed (from line B-B to line A-A). Such selective engraving can be easily accomplished by combining known photolithography techniques with wet or dry etching techniques.

Next, approximately 5-7 μm of aluminum is deposited over both sides of the wafer to form each electrode. By separating this aluminum vapor deposition film, a cathode electrode 6, an anode electrode 7, a gate electrode 8, and a second gate electrode 20 are formed. The aluminum vapor deposited film can be easily separated using known photolithography techniques and aluminum wet etching techniques.

Finally, the end face of the wafer is subjected to surface processing and surface passivation to complete the SI thyristor chip according to the present invention having the structure shown in the drawing.

〔Effect of the invention〕

In the present invention, only the N-channel buried gate structure SI thyristor has been described; however,
The present invention is not limited to this, and can be applied to a P channel, and the same effect can be obtained even when applied to surface gate type, beam gate type SI thyristor, field terminated diode, and gate turn-off type thyristor. Those skilled in the art will readily understand that there are some.

As explained in detail above, in the present invention, a high resistivity base region that shares the forward blocking voltage and a low resistivity anode having a conductivity type opposite to this base region are provided with the same structure as the base region. By providing a buffer layer of conductive type with intermediate specific resistance and providing a second gate electrode on the buffer layer, the current interrupting characteristics of the self-extinguishing semiconductor element are significantly improved, and its industrial value is extremely high. It's large.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing the cross-sectional structure of a unit element of the SI thyristor according to the present invention, and FIG. 2 is a circuit diagram for explaining the operation when opening and closing a DC circuit using the SI thyristor according to the present invention. , FIG. 3 is a cross-sectional structure diagram of an actual SI thyristor chip according to the present invention, FIGS. 4 and 5 are schematic diagrams of the cross-sectional structure of an existing SI thyristor unit element, and FIG.
This is a circuit diagram for explaining the operation when opening and closing a DC circuit using the SI thyristor shown in the figure, and FIGS. 7 to 9 each show a cross-sectional structure of a unit element of an existing improved SI thyristor. FIG. 1... cathode, 2... anode, 3... base region, 4... gate, 5... channel, 6...
Cathode electrode, 7... Anode electrode, 8... Gate electrode, 9... Anode junction, 10... Buffer layer, 11, 11'... SI thyristor, 12... Load, 13... Main power supply, 14, 14 '15,15'...
...Power supply, 16, 16', 17, 17'...Switch, 18...Second gate, 19...Second channel, 20...Second gate electrode, 21...N-type low resistance layer.

Claims (1)

[Claims] 1. A first gate electrode is provided in a low resistivity gate region having a conductivity type opposite to a high resistivity base region that shares the forward blocking voltage, and a low resistivity gate region having the same conductivity type as the base region and in contact with it is provided with a first gate electrode. In a self-arc-extinguishing semiconductor element capable of turning on and off an anode current by transmitting an electric signal between the cathode electrode provided in the cathode region of the base region, the anode region has a low resistivity and has a conductivity type opposite to that of the base region. A buffer layer having the same conductivity type as the base region and having a medium specific resistance is provided between the base regions, and a second gate electrode is provided on the buffer layer to control the anode current by transmitting an electric signal between the buffer layer and the anode electrode. A self-extinguishing semiconductor device characterized by having functions.