JPS6142932A - Manufacture of mesa-type semiconductor device - Google Patents

Manufacture of mesa-type semiconductor device

Info

Publication number
JPS6142932A
JPS6142932A JP59166692A JP16669284A JPS6142932A JP S6142932 A JPS6142932 A JP S6142932A JP 59166692 A JP59166692 A JP 59166692A JP 16669284 A JP16669284 A JP 16669284A JP S6142932 A JPS6142932 A JP S6142932A
Authority
JP
Japan
Prior art keywords
wafer
substrate
mesa
semiconductor substrate
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59166692A
Other languages
Japanese (ja)
Inventor
Masaaki Sadamori
貞森 将昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59166692A priority Critical patent/JPS6142932A/en
Publication of JPS6142932A publication Critical patent/JPS6142932A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Abstract

PURPOSE:To prevent damages of a wafer by dividing a semiconductor substrate into each individual semiconductor device after fixing an enforcing plate via alloy to one part of the at least one main face of the semiconductor substrate having P-type and N-type layers formed thereon in advance and next drilling mesa grooves on the substrate to clad and calcine glass therein and cladding electrode material on the substrate. CONSTITUTION:An enforcing plate 8 composed of polycrystalline silicon or single crystal silicon, molybdenum or tungsten is fixed to one part of the at least one main force of a semocinductor substrate 1 having P-type and N-type layers formed thereon via aluminum or alloy 19 containing aluminum. After mesa-type grooves 2 are drilled on the semiconductor substrate 1, glass 5 is cladded and calcined on the substrate 1 and furthermore, electrode material is cladded. After this, ths substrate 1 is divided into each individual semiconductor device. Said enforcing plate 8 is formed, for example, by fixing a polycrystalline silicon ring 8 to the wafer 1 via aluminum foil 9 at 700 deg.C in a vacuum. This allows damages of the wafer to be prevented and the caliber of the wafer to be made large.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明はメサ型半導体装置の改良された製造方法に関す
るものである。。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improved method of manufacturing a mesa-type semiconductor device. .

〔従来技術〕[Prior art]

第1図はこの81ノ従来のメサ型サイリスタ装置の製造
工程を示し、第1図Aは半導体基板(以下ウェハと言う
) 1にあらかじめ設計したP−N−P−Nの4層を公
知の不純物拡散法により形成した状態を示す図、第1図
Bはウェハ1にメサ溝2掘設し、PN接合部3および4
をこのメサ溝2内に露出させたのち、パフシベーシνン
ガラス5を被着させた状態を示す図、次に第1図Cは、
ウェハ1に電極をメタライズした状態を示す図で、6は
金からなる陽極、7はアルミニウムからなる陰極、12
はアルミニウムからなるゲート極である。
Fig. 1 shows the manufacturing process of this 81 conventional mesa type thyristor device, and Fig. 1A shows a semiconductor substrate (hereinafter referred to as wafer) 1 with four layers of P-N-P-N designed in advance. Figure 1B shows a state formed by the impurity diffusion method, in which mesa grooves 2 are dug in wafer 1, and PN junctions 3 and 4 are formed.
FIG.
This is a diagram showing a state in which electrodes are metallized on a wafer 1, where 6 is an anode made of gold, 7 is a cathode made of aluminum, and 12 is a cathode made of aluminum.
is a gate electrode made of aluminum.

なお、陽極6、陰極7、ゲート12はそれぞれ真空蒸着
にて被着させている。このように、各電極8、?1.1
2が被着された後には、第1図Cの破線で示す様にダイ
ヤモンドカッターにて個々のサイリスク素子に分割して
、所謂ウェハプロセスが完了することになる。
Note that the anode 6, cathode 7, and gate 12 are each deposited by vacuum evaporation. In this way, each electrode 8,? 1.1
After 2 is deposited, the wafer process is completed by dividing the wafer into individual silice elements using a diamond cutter as shown by the broken lines in FIG. 1C.

さて、この様にサイリスタ素子の場合、ウェハ1は第2
図に示す様にBの工程以降、即ち、メサ溝2を掘設する
工程以降、急激にウェハ破損が発生して製造歩留が低下
する傾向にある。この原因の第1に挙げられる事項は、
ウェハ1の主面にメサ溝2が掘設されることに起因し、
このメサ溝2によってウェハ1の材料強度が低下するこ
とである。即ら、一般に阻止電圧値が400乃至150
0V級のサイリスクの場合、ウエノ11の厚味は200
乃至300μm程度が適しており、このウェハ1では例
えば、N型基板を用いた場合P型エミッタ領域の基板表
面よりの深さくχ」)は50乃至は70μm5!度必要
であり、このため、メサ溝2の深さはとのχjを超すべ
く60乃至は80μrn程度は必要になる。従って、ウ
ェハ1の両主面よりメサ溝2を掘設するとウェハ1の最
も薄い箇所の厚味は80乃至は140μmとなり極めて
破損しやすいことになる。更にサイリスタ、ダイオード
、トライアック等のディスクリート素子は電流をウェハ
1の縦方向で制御する方が横方向に比べて大容量を得や
すいのであるが、このことはウニへ1の厚味を無差別に
厚く出来ないことを意味する。
Now, in the case of a thyristor element as described above, wafer 1 is
As shown in the figure, after the step B, that is, after the step of digging the mesa groove 2, wafer breakage occurs rapidly and the manufacturing yield tends to decrease. The first reason for this is:
Due to the mesa groove 2 being dug on the main surface of the wafer 1,
This mesa groove 2 reduces the material strength of the wafer 1. That is, the blocking voltage value is generally 400 to 150.
In the case of 0V class Cyrisk, the thickness of Ueno 11 is 200
Approximately 300 μm is suitable, and in this wafer 1, for example, when an N-type substrate is used, the depth of the P-type emitter region from the substrate surface χ”) is 50 to 70 μm5! Therefore, the depth of the mesa groove 2 needs to be about 60 to 80 μrn in order to exceed χj. Therefore, if the mesa grooves 2 are dug from both main surfaces of the wafer 1, the thickness of the thinnest part of the wafer 1 will be 80 to 140 μm, and it will be extremely susceptible to damage. Furthermore, for discrete elements such as thyristors, diodes, and triacs, it is easier to obtain a large capacity by controlling the current in the vertical direction of the wafer 1 than in the lateral direction; This means that it cannot be made thicker.

次に第2に挙げられる事項はウェハ1の材料(シリコン
)とパッシベーシスンガラス5との熱膨張率差に起因し
、ウェハ1に歪が加わることである。
The second problem is that distortion is applied to the wafer 1 due to the difference in thermal expansion coefficient between the material of the wafer 1 (silicon) and the passivation glass 5.

この為にウニへ1は第2図のAの範囲の如く、メサ溝2
を設ける以前迄はウェハ破損の程度は概ね許容できるが
、第2図のB、Cの範囲の如く、メサ溝2を掘設してか
らはウェハ破損の度合はウェハ1のハンドリング回数に
比例して増大する問題点があった。
For this reason, the sea urchin 1 has a mesa groove 2, as shown in the area A in Figure 2.
The degree of wafer damage was generally tolerable until the mesa groove 2 was formed, but as shown in ranges B and C in Figure 2, after the mesa groove 2 was dug, the degree of wafer damage was proportional to the number of times the wafer 1 was handled. There were increasing problems.

そこでこの樺な問題点に対し、従来では、次に述べるよ
うなウェハを補強する手段が提案されていた。その一方
法は、ウニへの寸法を厚くシ、この元々厚いウニへの主
要部分のみエツチングにより座取りして、元々のウェハ
の表面の一部を残し、この残った部分を補強枠とし、座
取り部分に素子を形成するものである。しかし、この方
法では素子を形成する座取り部分が平担に仕上らぬとい
う重大な問題点があり、又、逆に元々薄いウェハに部分
的に多結晶シリコンを堆積させ、この堆積した部分を補
強枠とする方法が考えられるが、この、いずれ゛の方法
も不充分なものであった。
To solve this problem, the following methods for reinforcing the wafer have been proposed. One method is to thicken the dimensions of the wafer, remove only the main part of the originally thick wafer by etching, leave a part of the original surface of the wafer, and use this remaining part as a reinforcing frame. The element is formed in the recessed portion. However, this method has the serious problem that the seated portions that form the elements cannot be finished flat, and conversely, polycrystalline silicon is partially deposited on an originally thin wafer, and this deposited portion is Although a method of using a reinforcing frame has been considered, both of these methods were insufficient.

〔発明の概要〕[Summary of the invention]

この発明は上記の欠点を解消するためになされもので、
半導体基板にあらかじめp2及びN型11を形成した後
、上記半導体基板の少なくとも一主面の一部分に、アル
ミニウム又はアルミニウムを成分に加えた合金を介して
多結晶シリコン又は単結晶シリコン又はモリブデン又は
タングステンから成る補強板を合金固着する工程と、上
記補強板を合金固着した上記半導体基板にメサ溝を掘設
しtコ後ガラスを被゛着焼成する工程と、この工程の後
、上記半導体基板に電極材料を被着、その後個々の半導
体装置に分割する工程とを具備することにより、ウェハ
の破損を防止でき、ウニへの口径をより大口径化できる
メサ型半導体装置の製造方法を提供す゛るものである。
This invention was made to eliminate the above-mentioned drawbacks.
After forming p2 and n-type 11 in advance on a semiconductor substrate, a portion of at least one main surface of the semiconductor substrate is made of polycrystalline silicon, single crystal silicon, molybdenum or tungsten via aluminum or an alloy containing aluminum as a component. A step of digging a mesa groove in the semiconductor substrate to which the reinforcing plate is fixed with an alloy, and then coating and firing glass on the semiconductor substrate.After this step, an electrode is attached to the semiconductor substrate. The present invention provides a method for manufacturing a mesa-type semiconductor device that can prevent damage to the wafer and increase the diameter of the wafer by including the steps of depositing a material and then dividing the wafer into individual semiconductor devices. be.

〔発明の実施例〕[Embodiments of the invention]

以下、図面により一実施例を説明する。第3図はウェハ
1に多結晶シリコンリング8をアルミニウムはく9を介
して真空中で700℃、15分間合金固着した状態で7
を示す図である。
An embodiment will be described below with reference to the drawings. Figure 3 shows a state in which a polycrystalline silicon ring 8 is bonded to a wafer 1 through an aluminum foil 9 in a vacuum at 700°C for 15 minutes.
FIG.

とこで、多結晶シリコンリング8は良く知られる様にC
VD法により量産されるものであり、炭素棒の周囲にシ
リコンを堆積させ、しかる後に、炭素棒を焼き切るか、
又は引き抜くことにより円Iキを得て、その後、この円
管を輪切りにすることにより、多結晶シリコンリング8
を得ることが出来る。なお、単結晶シリコンでも同様の
方法で得ることかできろ。ところで、この多結晶シリコ
ンリング8の厚味は任意であるが、ウェハ1の厚味が2
00μmのときは経験的に200乃至500μm程度が
適当である。また、アルミニウムはく9はリング状に打
ち抜くことにより得ろことができ、例えば厚味は30乃
至50μm程度が適当である。
By the way, as is well known, the polycrystalline silicon ring 8 is C
It is mass-produced using the VD method, in which silicon is deposited around the carbon rod, and then the carbon rod is burned out, or
Alternatively, a circle I is obtained by pulling it out, and then the polycrystalline silicon ring 8 is obtained by cutting this circular tube into rings.
can be obtained. I wonder if it can be obtained using a similar method for single crystal silicon. By the way, the thickness of this polycrystalline silicon ring 8 is arbitrary, but the thickness of the wafer 1 is 2.
When the thickness is 00 .mu.m, empirically, it is appropriate to have a thickness of about 200 to 500 .mu.m. Further, the aluminum foil 9 can be obtained by punching it into a ring shape, and the appropriate thickness is, for example, about 30 to 50 μm.

又、合金材料(ろう材)としてはアルミニウムに限らず
アルミ−シリコン共晶はくなど、アルミニウムを成分と
しtこものであれば、良好な合金固着を得ることが出来
る。これはA I −S i共晶合金が安定ご強固なこ
とによる。
Further, the alloy material (brazing material) is not limited to aluminum, but any material containing aluminum as a component, such as aluminum-silicon eutectic foil, can provide good alloy adhesion. This is because the AI-Si eutectic alloy is stable and strong.

しかしてこの様に多結晶シリコンリング8を合金固着し
ておくとウェハ1の強度は極めて太きくなリ、経験的に
は2乃至4倍に至った。
However, when the polycrystalline silicon ring 8 is fixed to the alloy in this manner, the strength of the wafer 1 becomes extremely large, and empirically it has been increased by 2 to 4 times.

第3図Bは従来と同様に公知の方法、例えばホトレジス
ト、シリコン酸化膜、シリコン窒化膜でメサ溝2以外を
写真製版でマスキングし、CP−4系のエッチャントで
メサエッチングし、次いでイノチック社のIP760ガ
ラスを750℃で被着焼成した状態を示す。従ってウェ
ハ1にメサ溝2を形成する工程までは1200乃至13
00℃の高湿度の不純物拡散のように比較的I&湿温度
作業されるが、メサ溝を掘設してからは750’CPI
!度のガラス被着焼成や電極材料でメタライズされるだ
けで比較的低温度であることから補強板を合金固着した
場合、固着部分は充分に温度に耐え得る事になる。
FIG. 3B shows a conventional method in which the area other than the mesa groove 2 is masked by photolithography using a photoresist, a silicon oxide film, or a silicon nitride film, mesa etching is performed using a CP-4 etchant, and then Inochik's This figure shows the state in which IP760 glass was deposited and fired at 750°C. Therefore, up to the step of forming mesa groove 2 on wafer 1, it takes 1,200 to 13
It is relatively I & humidity temperature work like impurity diffusion in high humidity of 00℃, but after digging mesa trench, 750'CPI
! If the reinforcing plate is fixed with an alloy, the fixed portion will be able to withstand the temperature sufficiently since the temperature is relatively low just by glass deposition firing or metallization with electrode material.

ところで、この実施例の通用で従来と比べて考慮すべき
点は、メサ溝2パターンを得る場合の写真製版ではフン
タクト方式よりはプaジェクシ璽ン方式が適しているこ
とである。又、ガラスを焼成する場合一時点に合金ろう
材9が軟化することがあるため、ウェハ1は水平に重ね
て焼成処理する方法が好ましいが、立てて焼成する場合
でも、多結晶シリコンリング8がズレによって、ろう材
9が流出するという恐れがなければその方向性は特に限
定するのではない。
By the way, a point that should be taken into consideration when comparing this embodiment with the conventional method is that the print method is more suitable than the direct method in photolithography when obtaining two patterns of mesa grooves. Furthermore, when firing glass, the alloy brazing filler metal 9 may soften at one point, so it is preferable to stack the wafers 1 horizontally and perform the firing process, but even when firing the wafers upright, the polycrystalline silicon ring 8 The direction is not particularly limited as long as there is no fear that the brazing filler metal 9 will flow out due to misalignment.

更に又、補強材としては、ウェハ1と熱W張車の近似し
たモリブデン、タングステンのリングを用いてもその効
果は同じである。
Furthermore, the effect is the same even if a ring made of molybdenum or tungsten, which is similar to the wafer 1 and the thermal W tensioning wheel, is used as the reinforcing material.

また、補強板は、第4図Aに示す様に十文字の補強板1
0や第4図Bのように十文字パターンにリングパターン
を組み合わせた補強材11でも同様の効果を奏する。
In addition, the reinforcing plate is a cross-shaped reinforcing plate 1 as shown in Fig. 4A.
A similar effect can be obtained using a reinforcing material 11 in which a ring pattern is combined with a cross pattern as shown in FIG. 0 and FIG. 4B.

尚、補強板のパターンが複雑になればろう材は真空蒸着
、スパッタリングにより形成すれば良い。
Incidentally, if the pattern of the reinforcing plate becomes complicated, the brazing material may be formed by vacuum evaporation or sputtering.

上記説明では補強板はウェハ1の両主面に取り付られて
いるものについて述べたが、いずれか一方の主面のみに
取り付けたものでもその効果が発揮される事は明らかで
ある。ところで、第3図Bの工程の後には、従来の工程
第1図Cと同様に陽極6に金、陰極7にアルミニウム、
ゲート極12にアルミニウムをそれぞれ真空蒸着するこ
とでウェハプロセスが完了する。
In the above description, the reinforcing plate is attached to both main surfaces of the wafer 1, but it is clear that the effect can be exerted even if the reinforcing plate is attached to only one of the main surfaces. By the way, after the step shown in FIG. 3B, the anode 6 is made of gold, the cathode 7 is made of gold,
The wafer process is completed by vacuum-depositing aluminum onto each gate electrode 12.

さて、この様にして完成したウェハは従来と同様にダイ
ヤモンドカックー等で個々のサイリスク素子に切断され
ることになるが、乙の場合、適常ダイヤモンドカッター
はウニへの周縁部よす切断を開始するので、補強板とし
て多結晶及び単結晶シリコンを使用しtこ場合はウェハ
と共に容易に切断出来るが、タングステン及びモリブデ
ンを使用した場合はダイシング前に硫酸−硝酸−水系及
び硝酸−弗酸−水系のエッチャントによって補強板のみ
エツチング除去してのちダイシングする必要がある。
Now, the wafer completed in this way will be cut into individual cyrisk elements using a diamond cutter, etc., as in the past, but in the case of O, a suitable diamond cutter can cut along the periphery of the sea urchin. Polycrystalline or single-crystalline silicon is used as a reinforcing plate because of the dicing process.In this case, it can be easily cut together with the wafer, but when tungsten or molybdenum is used, sulfuric acid-nitric acid-water system and nitric acid-hydrofluoric acid-system are used before dicing. It is necessary to remove only the reinforcing plate by etching with a water-based etchant and then dicing.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明は半導体基板にあらかじめP型及
びN型層を形成した後、上記半導体基板の少なくとも一
主面の一部分に、アルミニウム又はアルミニウムを成分
に加えた合金を介して多結晶シリコン又は単結晶シリコ
ン又はモリブデン又はタングステンから成る補強板を合
金固着′する工程と、上記補強板を合金固着した上記半
導体基板にメサ溝を掘設しに後ガラスを被着焼成する工
程と、との工程の後、上記半導体基板に電極材料を被着
、その後個々の半導体装置に分割する工程とを具備した
ので、ウニへの破損を防止でき、ウニへの大口径化を計
ることができる効果がある。
As described above, in the present invention, after forming P-type and N-type layers on a semiconductor substrate in advance, polycrystalline silicon or A step of fixing a reinforcing plate made of single crystal silicon, molybdenum, or tungsten with an alloy, and a step of digging a mesa groove in the semiconductor substrate to which the reinforcing plate is fixed with an alloy, and then applying glass and firing it. After that, the semiconductor substrate is coated with electrode material and then divided into individual semiconductor devices, which has the effect of preventing damage to the sea urchin and making it possible to increase the diameter of the sea urchin. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図A、B、Cは従来のメサ型サイリスタ装置の製造
過程を示す要部の断面図、第2図は従来のウェハ破損の
プロセス別変化を示すグラフ、第3図A、Bは本発明の
一実施例の工程を示す主要部の断面図、第4図は本発明
の他の実施例を示す斜視図、第5図はこの発明の更に他
の実施例を示す斜視図である。 図中、1は半導体基板、2はメサ溝、8、io。 11は補強板、9はろう材である。 なお、図中、同一符号は同−又は相当部分を示す。
Figures 1A, B, and C are cross-sectional views of main parts showing the manufacturing process of a conventional mesa-type thyristor device, Figure 2 is a graph showing changes in conventional wafer breakage by process, and Figures 3A and B are the main parts of the conventional mesa-type thyristor device. FIG. 4 is a sectional view of a main part showing the steps of one embodiment of the invention, FIG. 4 is a perspective view of another embodiment of the invention, and FIG. 5 is a perspective view of still another embodiment of the invention. In the figure, 1 is a semiconductor substrate, 2 is a mesa groove, and 8 is io. 11 is a reinforcing plate, and 9 is a brazing material. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims]  半導体基板にあらかじめP型及びN型層を形成した後
、上記半導体基板の少なくとも一主面の一部分に、アル
ミニウム又はアルミニウムを成分に加えた合金を介して
多結晶シリコン又は単結晶シリコン又はモリブデン又は
タングステンから成る補強板を合金固着する工程と、上
記補強板を合金固着した上記半導体基板にメサ溝を掘設
した後ガラスを被着焼成する工程と、この工程の後、上
記半導体基板に電極材料を被着、その後個々の半導体装
置に分割する工程とを具備してなるメサ型半導体基板装
置の製造方法。
After forming P-type and N-type layers in advance on a semiconductor substrate, polycrystalline silicon, single crystal silicon, molybdenum, or tungsten is applied to a portion of at least one main surface of the semiconductor substrate via aluminum or an alloy containing aluminum as a component. A step of drilling a mesa groove in the semiconductor substrate to which the reinforcing plate is fixed with an alloy and then depositing and firing glass thereon; After this step, applying an electrode material to the semiconductor substrate. A method for manufacturing a mesa-type semiconductor substrate device, comprising the steps of deposition and then dividing into individual semiconductor devices.
JP59166692A 1984-08-07 1984-08-07 Manufacture of mesa-type semiconductor device Pending JPS6142932A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59166692A JPS6142932A (en) 1984-08-07 1984-08-07 Manufacture of mesa-type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59166692A JPS6142932A (en) 1984-08-07 1984-08-07 Manufacture of mesa-type semiconductor device

Publications (1)

Publication Number Publication Date
JPS6142932A true JPS6142932A (en) 1986-03-01

Family

ID=15835967

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59166692A Pending JPS6142932A (en) 1984-08-07 1984-08-07 Manufacture of mesa-type semiconductor device

Country Status (1)

Country Link
JP (1) JPS6142932A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0423451A (en) * 1990-05-18 1992-01-27 Fuji Electric Co Ltd Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0423451A (en) * 1990-05-18 1992-01-27 Fuji Electric Co Ltd Manufacture of semiconductor device

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