JPH0423451A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0423451A
JPH0423451A JP2128220A JP12822090A JPH0423451A JP H0423451 A JPH0423451 A JP H0423451A JP 2128220 A JP2128220 A JP 2128220A JP 12822090 A JP12822090 A JP 12822090A JP H0423451 A JPH0423451 A JP H0423451A
Authority
JP
Japan
Prior art keywords
wafer
grooves
semiconductor
junction
grooved
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2128220A
Other languages
Japanese (ja)
Inventor
Kazuyasu Yoneyama
米山 和穏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP2128220A priority Critical patent/JPH0423451A/en
Publication of JPH0423451A publication Critical patent/JPH0423451A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable prevention of deterioration of characteristics of a base by a method wherein the terminal of each of grooves made in the shape of a lattice from the surface of a semiconductor wafer to a depth beyond a P-N junction is so provided as to project from the part of intersection with another groove. CONSTITUTION:Every time when one P-N junction is formed, grooves are made in the shape of a lattice from the surface of a wafer to a depth beyond the P-N junction, and the terminal of each of the grooves 2 and 3 is so provided as to project from the point of intersection with another groove. Even with respect to the outermost ones 1A out of the semiconductor bases formed in the shape of the lattice, accordingly, two of the grooves 2 always intersect each other, and when the wafer is cut along these grooves 2 by a dicer, it is prevented that cutting is made from a grooved part through a part not grooved or from the part not grooved through the grooved part in the periphery of each of the outermost semiconductor bases 1A. By this method, a stress applied to the wafer 10 is reduced and it is avoided that deterioration of characteristics of the semiconductor bases 1A is caused by a mechanical damage.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、表面に平行な少なくとも1個のPN接合を有
する半導体ウェーハの一面から格子状にPN接合を超え
る深さまで溝を堀り、この溝に沿って半導体ウェーハを
切断し、半導体基体に分割する半導体装置の製造方法に
関する。
Detailed Description of the Invention [Industrial Field of Application] The present invention involves digging grooves in a grid pattern from one surface of a semiconductor wafer having at least one PN junction parallel to the surface to a depth exceeding the PN junction. The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor wafer is cut along grooves and divided into semiconductor substrates.

〔従来の技術〕[Conventional technology]

第2図は従来のダイオード、トランジスタ、IC等の半
導体装置の一製造工程における半導体ウェーハ(以下ウ
ェーハと称する)の構造を示し、(a)は平面図(b)
は(a)のB−Bにおける断面図、(C)は(a)の半
導体基体1の要部断面図である。
Figure 2 shows the structure of a semiconductor wafer (hereinafter referred to as a wafer) in one manufacturing process of conventional semiconductor devices such as diodes, transistors, and ICs, and (a) is a plan view (b).
2A is a sectional view taken along line BB in FIG. 1A, and FIG.

半導体装置を製造するには第2図に示すように、拡散等
の技術を用いてウェーハ10の上にPN接合を形成し、
このウェーハIOの表面に格子状に溝2を掘る。この溝
2はうニーム10に設けられているPN接合5を超える
深さまで掘られ、この溝2に沿って露出したPN接合5
をパッシベーション膜4で被覆する。次にダイザ−を用
いてその溝に沿ってウェーハを切断し、半導体基体1に
分割するようにする。
To manufacture a semiconductor device, as shown in FIG. 2, a PN junction is formed on a wafer 10 using a technique such as diffusion,
Grooves 2 are dug in a grid pattern on the surface of this wafer IO. This groove 2 is dug to a depth exceeding the PN junction 5 provided in the neem 10, and the PN junction 5 is exposed along this groove 2.
is covered with a passivation film 4. Next, the wafer is cut along the grooves using a dizer to divide the wafer into semiconductor substrates 1.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

前述の半導体装置の製造方法では、ウェーハの」二に格
子状に形成された複数個の半導体基体を分割する際、半
導体基体の周囲の溝に沿ってウェーハをグイサーにより
切断しているが、ウェーハの上に格子状に形成された複
数個の半導体基体のうち最外周の半導体基体(第2図に
おいてIAで示す)の周囲では、溝のある部分(例えば
、第2図において11の部分)から溝のない部分(例え
ば、第2図において12の部分)を切断する、あるいは
溝のない部分から溝のある部分を切断するようになり、
このためウェーハには大きな応力が加わり、最外周に形
成されている半導体基体にはダメージが与えられ、特性
劣化を生じる危険がある。
In the method for manufacturing semiconductor devices described above, when dividing a plurality of semiconductor substrates formed in a lattice shape on the second side of a wafer, the wafer is cut with a cutter along grooves around the semiconductor substrates. Around the outermost semiconductor substrate (indicated by IA in FIG. 2) among the plurality of semiconductor substrates formed in a lattice pattern on top of the semiconductor substrate, from the grooved portion (for example, the portion 11 in FIG. 2) Cutting a part without a groove (for example, part 12 in FIG. 2), or cutting a part with a groove from a part without a groove,
Therefore, a large stress is applied to the wafer, and the semiconductor substrate formed on the outermost periphery is damaged, and there is a risk of deterioration of characteristics.

本発明の課題は前述の問題点を解決して、半導体基体を
分割するためウェーハを切断する際、ウェーハにか\る
応力を低下させ、半導体基体の特性劣化を防ぐようにし
た半導体装置の製造方法を提供することにある。
An object of the present invention is to solve the above-mentioned problems and to manufacture a semiconductor device that reduces the stress applied to the wafer when cutting the wafer to divide the semiconductor substrate, thereby preventing deterioration of the characteristics of the semiconductor substrate. The purpose is to provide a method.

〔課題を解決するだめの手段〕[Failure to solve the problem]

前述の課題を解決するために、本発明の半導体装置の製
造方法においては、表面に平行な少な(とも1個のPN
接合を形成した半導体ウェーハの表面から格子状にPN
接合を超える深さまで溝を堀り、この溝に沿って露出し
たPN接合をパッシベーション膜で被覆し、前記溝に沿
って半導体ウェーハを切断し、複数個の半導体基体を得
る半導体装置の製造方法において、前記各溝の終端を他
の溝との交差部より突出させて設けるようにする。
In order to solve the above-mentioned problems, in the method for manufacturing a semiconductor device of the present invention, a small number of PNs parallel to the surface (all 1 PN
PN is formed in a lattice pattern from the surface of the semiconductor wafer on which the bond is formed.
In a method of manufacturing a semiconductor device, a trench is dug to a depth exceeding the junction, a PN junction exposed along the trench is covered with a passivation film, and a semiconductor wafer is cut along the trench to obtain a plurality of semiconductor substrates. , the terminal ends of each of the grooves are provided to protrude from the intersections with other grooves.

〔作 用〕[For production]

本発明の半導体装置の製造方法においては、ウェーハ上
に格子状に掘られた溝を、その終端が他の溝との交差部
より突出するよう設けるようにしたので、格子状に形成
された最外周の半導体基体も、その周囲の溝はがならず
2個の溝が直交しており、この溝に沿いウェーハをダイ
サーで切断する際半導体基体の周囲で溝のある部分から
溝のない部分を、あるいは、溝のない部分から溝のある
部分を切断することはなくなり、これにより、ウェーハ
にか\る応力は低下し半導体基体は機械的ダメージによ
り特性劣化を生じることが避けられる。
In the method for manufacturing a semiconductor device of the present invention, grooves are dug in a lattice pattern on a wafer so that their terminal ends protrude from the intersections with other grooves. The semiconductor substrate on the outer periphery also has two grooves that are perpendicular to each other without peeling, and when cutting the wafer along these grooves with a dicer, the semiconductor substrate is separated from the grooved part to the non-grooved part. Alternatively, the grooved portion is no longer cut from the non-grooved portion, thereby reducing stress on the wafer and preventing characteristic deterioration of the semiconductor substrate due to mechanical damage.

〔実施例〕〔Example〕

第1図は本発明の一実施例における半導体装置の一製造
工程におけるウェーハの構造を示し、(a)は平面図(
b)は(a)のA−Aにおける断面図、(C)は(a)
の半導体基体lの要部断面図である。拡散等の技術を用
いてウェーハ10上にPN接合5を形成し、このウェー
ハ10の表面に格子状に溝2を掘る。
FIG. 1 shows the structure of a wafer in one manufacturing process of a semiconductor device according to an embodiment of the present invention, and (a) is a plan view (
b) is a cross-sectional view taken along A-A of (a), (C) is a cross-sectional view of (a)
FIG. A PN junction 5 is formed on the wafer 10 using a technique such as diffusion, and grooves 2 are dug in a grid pattern on the surface of the wafer 10.

この際溝2の終端は他の溝との交差部より突出した位置
まで溝3として掘られる。これらの溝は半導体ウェーハ
に設けられているPN接合5を超える深さまで堀り、こ
の溝2に沿って露出したPN接合5をパッシベーション
膜4で被覆する。次にダイサーを用いてその溝に沿って
ウェーハを切断し、半導体基体lを分割するようにする
。本実施例においては、格子状に形成された溝2とこの
溝が延長され形成された溝3を設けるようにしたので、
格子状に形成された最外周の半導体基体IAも、その周
囲の溝はかならず2個の溝が直交しており、この溝に沿
ってウェーハをダイサーで切断する際、半導体基体の周
囲で溝のある部分から溝のない部分を、あるいは溝のな
い部分から溝のある部分を切断することはなくなり、こ
れによりウェーハにか−る応力は低下し半導体基体は機
械的ダメージにより特性が低下することは避けられる。
At this time, the end of the groove 2 is dug as a groove 3 to a position protruding from the intersection with another groove. These grooves are dug to a depth exceeding the PN junction 5 provided in the semiconductor wafer, and the PN junction 5 exposed along the groove 2 is covered with a passivation film 4. Next, the wafer is cut along the grooves using a dicer to divide the semiconductor substrate l. In this embodiment, grooves 2 formed in a lattice shape and grooves 3 formed by extending this groove are provided, so that
The outermost semiconductor substrate IA formed in a lattice shape also has two grooves that are perpendicular to each other, and when cutting the wafer along these grooves with a dicer, the grooves around the semiconductor substrate are It is no longer necessary to cut a non-grooved section from a section or a grooved section from a non-grooved section, which reduces stress on the wafer and prevents the semiconductor substrate from having its properties deteriorated due to mechanical damage. can avoid.

なお、この延長された溝3はウェーハの外周端まで掘る
とウェーハの機械強度が低下するので、この溝はウェー
ハ10の外周端まで至らぬようにし、ウェーハ10の周
辺部に機械強度から必要とされる溝のない部分を設ける
ことが望ましい。
Note that if this extended groove 3 is dug all the way to the outer edge of the wafer, the mechanical strength of the wafer will decrease, so this groove should not reach the outer edge of the wafer 10, and it should be placed around the periphery of the wafer 10, which is necessary for mechanical strength. It is desirable to provide a section without grooves.

〔発明の効果〕〔Effect of the invention〕

本発明の半導体装置の製造方法においては、ウェーハ上
に格子状に形成された溝を、谷溝の終端を他の溝との交
差部より突出させて設け、ウェーハ切断時半導体基体に
機械的ダメージが与えられないようにしたので、この種
の原因による特性劣化はなくなり、歩留りの向上に大き
な効果があった。
In the method for manufacturing a semiconductor device of the present invention, grooves are formed in a lattice pattern on a wafer so that the terminal ends of the valley grooves protrude from the intersections with other grooves, thereby preventing mechanical damage to the semiconductor substrate when cutting the wafer. Since this structure prevents the deterioration of characteristics due to this type of cause, it has a great effect on improving the yield.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の半導体装置の製造方法の一実施例にお
ける一製造工程のウェーハの構造を示しくa)は平面図
、(b)は(a)のA−Aにおける断面図、(C)は(
a)の半導体基体1の要部断面図、第2図は従来の半導
体装置の製造方法における一製造工程のウェーハの構造
を示しくa)は平面図、(b)は(a)のB−Bにおけ
る断面図、(C)は(a)の半導体基体1の要部断面図
である。 1:半導体基体、2:溝(半導体基体周囲の)、3:溝
(延長された)、4:パッシベーション膜、5 : P
N接合、10:半導体ウェーハ。 く− (b) (C)
FIG. 1 shows the structure of a wafer in one manufacturing step in an embodiment of the semiconductor device manufacturing method of the present invention, in which a) is a plan view, (b) is a cross-sectional view taken along line A-A in (a), and (C )teeth(
FIG. 2 shows the structure of a wafer in one manufacturing step in a conventional semiconductor device manufacturing method, FIG. 2 shows a top view, and FIG. FIG. 2B is a cross-sectional view of the semiconductor substrate 1 shown in FIG. 1: Semiconductor substrate, 2: Groove (around semiconductor substrate), 3: Groove (extended), 4: Passivation film, 5: P
N junction, 10: semiconductor wafer. Ku- (b) (C)

Claims (1)

【特許請求の範囲】[Claims] 1)表面に平行な少なくとも1個のPN接合を形成した
半導体ウェーハの表面から格子状にPN接合を超える深
さまで溝を堀り、この溝に沿って露出したPN接合をパ
ッシベーション膜で被覆し、前記溝に沿って半導体ウェ
ーハを切断し、複数個の半導体基体を得る半導体装置の
製造方法において、前記各溝の終端を他の溝との交差部
より突出させて設けることを特徴とする半導体装置の製
造方法。
1) trenches are dug in a lattice pattern from the surface of a semiconductor wafer on which at least one PN junction has been formed parallel to the surface to a depth exceeding the PN junction, and the exposed PN junctions are covered with a passivation film along the trenches; A method for manufacturing a semiconductor device in which a semiconductor wafer is cut along the grooves to obtain a plurality of semiconductor substrates, characterized in that the terminal end of each groove is provided to protrude from the intersection with another groove. manufacturing method.
JP2128220A 1990-05-18 1990-05-18 Manufacture of semiconductor device Pending JPH0423451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2128220A JPH0423451A (en) 1990-05-18 1990-05-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2128220A JPH0423451A (en) 1990-05-18 1990-05-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0423451A true JPH0423451A (en) 1992-01-27

Family

ID=14979467

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2128220A Pending JPH0423451A (en) 1990-05-18 1990-05-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0423451A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000059050A1 (en) * 1999-03-31 2000-10-05 Seiko Epson Corporation Method of manufacturing semiconductor device, semicondutor device, narrow pitch connector, electrostatic actuator, piezoelectric actuator, ink jet head, ink jet printer, micromachine, liquid crystal panel, and electronic device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5253667A (en) * 1975-10-29 1977-04-30 Hitachi Ltd Production of semiconductor device
JPS584815A (en) * 1981-06-26 1983-01-12 Teijin Ltd Polyester fiber having honeycomb-like structure and its preparation
JPS5893333A (en) * 1981-11-30 1983-06-03 Nec Corp Manufacture of semiconductor device
JPS6142932A (en) * 1984-08-07 1986-03-01 Mitsubishi Electric Corp Manufacture of mesa-type semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5253667A (en) * 1975-10-29 1977-04-30 Hitachi Ltd Production of semiconductor device
JPS584815A (en) * 1981-06-26 1983-01-12 Teijin Ltd Polyester fiber having honeycomb-like structure and its preparation
JPS5893333A (en) * 1981-11-30 1983-06-03 Nec Corp Manufacture of semiconductor device
JPS6142932A (en) * 1984-08-07 1986-03-01 Mitsubishi Electric Corp Manufacture of mesa-type semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000059050A1 (en) * 1999-03-31 2000-10-05 Seiko Epson Corporation Method of manufacturing semiconductor device, semicondutor device, narrow pitch connector, electrostatic actuator, piezoelectric actuator, ink jet head, ink jet printer, micromachine, liquid crystal panel, and electronic device
US6573157B1 (en) 1999-03-31 2003-06-03 Seiko Epson Corporation Method of manufacturing semiconductor device, narrow pitch connector, electrostatic actuator, piezoelectric actuator, ink jet head, ink jet printer, micromachine, liquid crystal panel, and electronic device
US6794746B2 (en) 1999-03-31 2004-09-21 Seiko Epson Corporation Method of manufacturing semiconductor device, semiconductor device, narrow-pitch connector, electrostatic actuator, piezoelectric actuator, ink jet head, ink jet printer, micromachine, liquid crystal panel, and electronic device

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