JPH0244729A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To obtain stable characteristics by forming a recess surrounded by an oblique face at each of a plurality of bases on one face of a substrate, forming an opposite conductivity type layer to that of the substrate, forming a mesa groove which has the outer periphery of an opening on the surface near the periphery of the base and narrows toward its bottom, and so cutting the substrate as to pass the bottom of each groove. CONSTITUTION:After one face of an n<-> type silicon substrate is formed with parts covered with a resist film in a lattice state, recesses 8 are formed by etching, an impurity is diffused in its whole face, a P<+> type layer is formed on the side having the recesses and an N<+> type layer 3 is formed on the other side. In this case, an oblique face 41 is formed at a P-N junction between the original N<-> type layer 1 of the substrate. Then, the inner face of the recess 8 and the narrow part of the flat face of the outer periphery are protected with resist films, a base for surrounding the recess is etched to the depth exceeding the junction to form a mesa groove 5. Then, the inner face of the groove 5 is covered with a passivation film 6, and cut into diode chips at the cutting face of a chain line 7. Thus, high breakdown strength and stable characteristics are obtained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a method for removing P from one surface of a semiconductor substrate on which a P-N junction is formed.
A method for manufacturing a semiconductor device in which a mesa groove having a depth exceeding an N junction is formed, at least the inner surface of the mesa groove is covered with a passivation film, and a substrate is cut so that a dividing plane passes through the bottom of the mesa groove to obtain an element chip. Regarding.

[Conventional technology]

A conventional method for obtaining element chips by dividing a semiconductor substrate with a PN junction formed therein, unlike the planar method, will be explained with reference to FIG. Diffuse impurities and form P layer 2 on one side
, an N° layer 3 is formed on the other side. As a result, a mask (not shown) is formed on the surface of the 0th and 20th layers, where a PN junction plane 4 parallel to the substrate surface is formed, and a mesa groove 5 deeper than the PN junction is dug by etching from the portion not covered by the mask. The inner surface of each mesa groove 5 is coated with an organic film such as polyimide to form a passivation film 6. Thereafter, a large number of diode chips can be obtained by performing dicing along the cut plane indicated by the chain line 7.

[Problem to be solved by the invention]

However, in the diode chip obtained by the above method, since the mesa groove 5 gradually becomes narrower from the opening on the substrate surface, the bevel angle θ1 of the PN junction becomes smaller than that of P with a high impurity concentration.
It becomes an acute angle on the layer 2 side and has a negative bevel. Therefore, the electric field strength at the surface near the PN junction becomes stronger than inside, resulting in a disadvantage that the withstand voltage becomes low. To overcome this drawback,
A processing method is sometimes used in which the mesa groove becomes wider as it progresses from the surface to the inside, but with this mesa groove structure, it is difficult to protect the surface uniformly, and another drawback is that it is difficult to obtain stable characteristics. there were.

The object of the present invention is to eliminate each of the above-mentioned drawbacks, form a mesa groove that gradually narrows as it gets deeper than the normal surface opening, and still obtain a positive bevel near the brazing position of the PN junction.
An object of the present invention is to provide a method for manufacturing a semiconductor element with stable characteristics.

[Means to solve the problem]

In order to solve the above problems, the method of the present invention involves forming a recess surrounding a plurality of pedestals with an inclined surface on one surface of a semiconductor substrate, and then diffusing impurities from the surface to form a recess of a conductivity type opposite to that of the substrate. A layer is formed, the outer periphery of the opening is on the surface near the periphery of the pedestal, and mesa grooves are formed that become narrower toward the bottom.The substrate is cut so that the dividing plane passes through the bottom of each mesa groove. You shall receive a tip.

[Effect]

The PN junction caused by the diffusion layer from the surface forming the depression is parallel to the surface and has an inclined surface parallel to the inclined surface of the surface, and the inner surface of the mesa groove has the outer periphery of the opening near the periphery of the pedestal. exposes the sloped surface of the PN junction. The angle between this inclined PN junction and the inner surface of the mesa groove, which becomes narrower toward the bottom, forms an acute angle on the side of the original layer of the substrate with low impurity concentration, so that a positive bevel is formed.

〔Example〕

FIG. 1 (al, l) shows a mesa groove forming process according to an embodiment of the present invention, and parts common to those in FIG. 2 are given the same reference numerals. In Figure 1 (al), after forming a portion covered with a resist film on one surface of an n-silicon substrate in a lattice shape, etching with a mixed acid, alkali, etc., creates depressions 8 to several dozen deep. Thereafter, impurities are diffused over the entire surface from both sides as in the conventional method, and the 21 layer 2 is formed on the side with the depression 8, and the N3 layer 3 is formed on the other side.In this case, the P' layer 2 Since it is parallel to the surface having the recess 8, an inclined surface 41 is generated in the PN junction between the substrate's original N-layer l. The narrow part of the groove is protected with a resist film, and the mesa groove 5 is formed by etching the platform surrounding the depression with a mixed acid to a depth exceeding the PN junction.Since the mesa groove is formed by a normal etching method, the opening The angle θ2 that intersects with the IIJ1 slope 41 of the exposed portion of the PN junction becomes an acute angle on the N− layer side.In other words, the area near the exposed portion of the PN junction becomes a positive bevel, and the electric field on the surface Since the strength is lower than the electric field strength inside the junction, the breakdown voltage characteristics are improved and stabilized.After this, the inner surface of the mesa 45 is covered with Vansivation II!6, and the diode chip is formed by dicing along the cut plane indicated by the chain line 7. The dividing process is the same as before.

〔Effect of the invention〕

According to the present invention, a mesa groove is formed on one surface of the semiconductor substrate and becomes gradually narrower as it gets deeper than the opening, and the element chip is cut by a dividing plane passing through the bottom of the mesa groove. When forming a positive bevel near the exposed part of the PN junction exposed on the inner surface of the mesa groove, a depression is formed on the semiconductor surface before the PN junction is formed, and the PN junction in the exposed part by the mesa groove is tilted. This was made possible by creating a surface. As a result, a semiconductor element with high breakdown voltage and stable characteristics can be obtained. Also, since a depression remains on one side of the element chip, it is formed in this depression! It becomes easier to braze the connection leads to the lead frame, and the recess can also be used for positioning when mounting the chip on the lead frame.

[Brief explanation of the drawing]

Figures 1+a) and (bl are cross-sectional views sequentially showing the mesa groove forming process in an embodiment of the present invention, and Figure 2 are cross-sectional views showing the conventional mesa groove forming process. 1: N-3i substrate, 2: P'' layer, 3: N9 layer, 4: PN
Bonding, 41: Inclined surface, 5: Mesa groove, 6: Pansibasic membrane, 7: Cut surface, 8: (indentation).

Claims (1)

[Claims] 1) After forming a depression surrounding a plurality of pedestals with an inclined surface on one surface of the semiconductor substrate, a layer of conductivity type opposite to that of the substrate is formed by diffusion of impurities from that surface, and a layer of conductivity type opposite to that of the substrate is formed on the surface near the periphery of the pedestal. A method for manufacturing a semiconductor device, characterized by forming a mesa groove that has an outer periphery of an opening and narrowing toward the bottom, and cutting the substrate so that a dividing plane passes through the bottom of each mesa groove to obtain an element chip. .