JPS63141376A - Semiconductor element - Google Patents

Abstract

PURPOSE:To enlarge a depletion layer of an external layer side at a P-N junction exposed part and prevent voltage breakdown at P-N junction exposed parts of the insides of mesa grooves, thereby obtaining bulk breakdown strength by providing guard rings surrounding P-N junctions at the base of the mesa grooves. CONSTITUTION:A P-layer 2 is formed by diffusing aluminum or galium having a large diffusion coefficient and mesa grooves 4 having depths which are deeper than those of final P-N junctions are formed through a selective etching commencing from the P-layer 2 side. Then, patterning of oxide films 6 is carried out. Further, a boron diffusion is performed as a P-type impurity of the second step and P<+> layers 71 and 72 are formed at the surface of the P-layer 2 as well as at the base of the mesa grooves 4. Subsequently, an N<+> layer 8 is formed by diffusing phosphorus at the opposite side of the P-layer 2 of an N-substrage 1 and the insides of the mesa grooves 4 are covered with passivation material layers 9 and then, metal electrodes 10 are adherent to both sides of the N<+> layer 8 and the P-layer 2. After that, the substrate is cut at a cross section passing through the base of mesa grooves 4 to obtain pellets. Thus, guard rings 72 are formed at depletion-occurrence regions of the outside of the P-N junction exposed part toward the inside of bevel grooves.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention involves forming a mesa groove having a depth exceeding the PN junction from the surface of a semiconductor substrate on which a PN junction parallel to the surface is formed, and then cutting the bottom of the groove. The present invention relates to a semiconductor device that is cut into a pellet by cutting along a cross section.

[Conventional technology]

A diode element, which is an example of a semiconductor element called a mesa type, is made by forming a layer P12 on an N-type silicon substrate 1 by a diffusion method, for example, as shown in FIG. A mesa groove 4 is formed. After that, the inner surface of the mesa groove 4 is coated with a metal material such as glass or polyimide, and electrode metal is coated on both sides of the substrate 1, and then a cross section passing through the bottom of the mesa groove 4 is coated with a dicing blade or a laser. It is manufactured by cutting the substrate at step 11 and forming it into pellets.

(Problems to be Solved by the Invention) In the diode manufactured as described above, the bevel formed by the mesa groove becomes a negative bevel as shown in FIG. depletion layer 5
becomes narrower on the bevel surface, and the depletion layer width II on the bevel surface is the depletion layer width at the center of the pellet! , because it is smaller, voltage breakdown will occur on the surface at a voltage lower than the withstand voltage of the bulk, which is disadvantageous when high withstand voltage is required. 1 N
A method is sometimes taken in which the mesa groove 4 is formed from the N side to a depth exceeding the PN junction 3. However, in this case, since mesa tR4 is deep, the etching depth varies widely, it becomes difficult to deposit the pancibasin material, and the remaining thickness of the mesa groove becomes thin, which may cause wafer cracking during wafer processing. There was a problem that occurred. On the other hand, in an element having two or more PN junctions, 1
Forming a mesa groove by repeated etching has the drawback that it is not possible to make all PN junctions positive bevels, and it is not possible to obtain a similar high breakdown voltage at all PN junctions.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a semiconductor element that can obtain a high breakdown voltage by forming a shallow mesa groove.

[Means for solving problems]

To achieve the objective of the wafer, the present invention provides a semiconductor device having a mesa groove extending from a surface layer of a first conductivity type to a layer of a second conductivity type adjacent to the surface layer via a PN junction parallel to the surface. , a first conductivity type layer surrounding the PN junction at a narrow interval is provided on the bottom surface of the mesa groove.

[Effect]

The layer of the second quaternary electric type surrounding the PN junction provided at the bottom of the mesa groove acts as a so-called guard ring, and the depletion layer expands on the surface exposed to the mesa groove, eliminating voltage breakdown at the surface and eliminating the pellet. The withstand voltage of the bulk directly becomes the withstand voltage of the element, and a high withstand voltage can be obtained.

〔Example〕

FIG. 1 (Ill to +81 shows the manufacturing process of one embodiment of the present invention, and the same parts as in FIG. 2 are given the same reference numerals. First, aluminum or gallium, which has a large diffusion coefficient, is diffused from one surface of the N-type silicon substrate as the first P-type impurity.
Next, by selective etching, a mesa groove 4 with a depth exceeding the final PN junction depth is formed from the PJ'J2 side (Fig. b). The oxide film 6 is patterned by etching as shown in FIG. 1(e). Furthermore, boron is diffused as a second P-type impurity to form P'Jli 71 and 72 on the surface of the second layer 2 and the bottom of the mesa groove 4 (Figure d). Phosphorus is diffused on the P layer 2 side to form an N ``'' layer 8, the inner surface of the mesa groove 4 is coated with a banci basin material N9, and metal electrodes 10 are coated on both sides (Fig. e). Cut the substrate at a cross section passing through the bottom of 4 to obtain pellets. This results in
A guard ring 72 can be formed in the depletion layer generation region outside the PN junction exposed portion to the inner surface of the bevel groove, and even in the negative bevel shape, the depletion layer outside the PN junction exposed portion is expanded, and the reverse breakdown voltage with respect to the PN junction is improved.

In a transistor or thyristor in which two PN junctions are formed parallel to the surface of a semiconductor substrate, by forming a mesa groove from both sides over the nearby PN junction and providing a guard ring at the bottom of each mesa groove, the withstand voltage can be increased at both negative bevels. can be improved.

〔Effect of the invention〕

According to the present invention, by providing a guard ring surrounding the PN junction at the bottom of the mesa groove, it is possible to expand the depletion layer on the internal layer side in the exposed PN junction, so that voltage breakdown at the exposed PN junction on the inner surface of the mesa groove can be expanded. It is possible to prevent this and obtain bulk pressure resistance.

Therefore, even if a negative bevel occurs when forming a shallow mesa groove in a mesa type, a high withstand voltage device can be obtained.There is no variation in groove depth, and it is easy to uniformly apply the pancibasin to the entire groove. Effects such as a reduction in defects and a reduction in the occurrence of wafer cracking during the wafer process due to the large remaining thickness of the mesa groove can be obtained.

[BRIEF DESCRIPTION OF THE DRAWINGS] Figures 1 (al to el are cross-sectional views sequentially showing the manufacturing process of an embodiment of the present invention, Figure 2 is a cross-sectional view of a conventional mesa diode element in the manufacturing process, Figure 3 is a cross-sectional view of the pellet of the element shown in the second session, and Figure 4 is a cross-sectional view of the positive bevel pellet. ljN type silicon substrate, l: pJll, 3: PN
Connection figure 2L, figure 3

Claims (1)

[Claims] 1) In a device having a mesa groove extending from a surface layer of a first conductivity type to a layer of a second conductivity type adjacent to the surface layer via a PN junction parallel to the surface, the PN junction is provided on the bottom surface of the mesa groove. A semiconductor device characterized in that a layer of a first conductivity type is provided surrounding the layer with a narrow gap therebetween.