JPS6350066A - Power semiconductor device and manufacture thereof - Google Patents
Power semiconductor device and manufacture thereofInfo
- Publication number
- JPS6350066A JPS6350066A JP19426786A JP19426786A JPS6350066A JP S6350066 A JPS6350066 A JP S6350066A JP 19426786 A JP19426786 A JP 19426786A JP 19426786 A JP19426786 A JP 19426786A JP S6350066 A JPS6350066 A JP S6350066A
- Authority
- JP
- Japan
- Prior art keywords
- circular
- groove
- main surface
- chip
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000011521 glass Substances 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 9
- 238000002161 passivation Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 13
- 229910045601 alloy Inorganic materials 0.000 claims description 10
- 239000000956 alloy Substances 0.000 claims description 10
- 238000005219 brazing Methods 0.000 claims description 7
- 239000007772 electrode material Substances 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 6
- 239000011733 molybdenum Substances 0.000 abstract description 6
- 230000006378 damage Effects 0.000 abstract description 5
- 229910003460 diamond Inorganic materials 0.000 abstract description 3
- 239000010432 diamond Substances 0.000 abstract description 3
- 229910000679 solder Inorganic materials 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 17
- 238000003776 cleavage reaction Methods 0.000 description 7
- 230000007017 scission Effects 0.000 description 7
- 239000013078 crystal Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000009740 moulding (composite fabrication) Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Thyristors (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電力半導体素子の構造および製造方法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure and manufacturing method of a power semiconductor device.
第４図は従来の電力用サイリスク素子の製造過程を示す
。第４図（ａ）は、大口径ウェハ１に、公知の拡散およ
び写真製版技術により、角形チップ領域２を形成した状
態を示す斜視図であり、３はゲート極となるｐ ＋ｗ４
域、４は陰極となるＮ６領域、破線は個々のチップに分
−断するための仮想線である。この場合、５の領域は、
ＰＮ接合部のパッシベーションのために化学的エツチン
グにより掘設したメサ溝に鉛系ガラスを塗布・焼成した
ガラスパッシベーション領域である。FIG. 4 shows the manufacturing process of a conventional power cyrisk element. FIG. 4(a) is a perspective view showing a state in which a square chip region 2 is formed on a large-diameter wafer 1 by known diffusion and photolithography techniques, and 3 is a gate electrode p + w4.
The area 4 is the N6 area which becomes a cathode, and the broken line is an imaginary line for dividing into individual chips. In this case, the area of 5 is
This is a glass passivation area in which lead-based glass is applied and fired in a mesa groove dug by chemical etching for passivation of a PN junction.
第４図（ｂｌは個々のチップ６に分断されたチップの一
部を示す斜視図であり、分断はダイヤモンドホイールに
より傷を入れ、その後ウェハ全体を押し割って、エキス
バンドフィルム上で個々のチップ６を拾う方式が採られ
ている。FIG. 4 (bl is a perspective view showing a part of the chip that has been divided into individual chips 6; the division is performed by making scratches with a diamond wheel, then breaking the entire wafer, and separating the chips into individual chips on an expanded film. A method of picking up 6 is adopted.
第４図（Ｃ）および（ｄｌは、熱補償板として半導体シ
リコンと熱膨張率の近似したモリブデン板を合金固着さ
せた電力サイリスク素子の斜視図および断面図を示す。FIGS. 4(C) and 4(dl) show a perspective view and a cross-sectional view of a power silica element in which a molybdenum plate having a coefficient of thermal expansion similar to that of semiconductor silicon is fixed as an alloy as a heat compensating plate.
同図において、７はＮゆ領域４にアルミニウムを厚く蒸
着した陰極、８はＰ″領域３にアルミニウムを蒸着した
ゲート極、９は陽極としての熱補償板であり、アルミニ
ウム又はアルミニウム・シリコン合金１０を熱補償板９
の主面に予め蒸着しておき、チップ６と合金固着したも
のを示す。In the figure, 7 is a cathode in which aluminum is thickly vapor-deposited in the Ny region 4, 8 is a gate electrode in which aluminum is vapor-deposited in the P'' region 3, and 9 is a heat compensation plate as an anode. The heat compensation plate 9
It is shown that it has been vapor-deposited in advance on the main surface of the chip 6 and is fixed to the chip 6 with an alloy.
元来、半導体単結晶ウェハは、例えば結晶方位が＜１．
１．１ ＞のものであれば、ある結晶軸を基準にして互
いに６０度の角度をなす所に次の結晶軸があり、そこが
機械的にへき開割れを起こし易いという性質がある。Originally, semiconductor single crystal wafers have crystal orientations of, for example, <1.
1.1>, the next crystal axis is located at an angle of 60 degrees with respect to one crystal axis, and there is a property that mechanical cleavage cracking is likely to occur there.
角形チップの場合、最終エキスバンド工程で、大口径半
導体ウェハを押し割りし易いように、結晶軸に従って少
なくとも１方向のメサ溝を形成する必要がある。従って
、元来へき開割れを生じ易い所にメサ溝を掘設し、電力
半導体の高耐圧指向から、ベース領域に対するエミッタ
領域の厚さは、一般に、ベース領域（ＮＢ）（第４図（
ｄｌ参照）の１００μｍに対してエミッタ領域が５０μ
ｍ程度、同じくベースの４００μｍに対してエミッタ領
域が８０μｍと大きい。しかもメサ溝は、エミッタ領域
よりも深くベース領域に食い込む形で掘設ず必要がある
から、最終的には、メサ溝の深さは、エミッタ領域が５
０μｍのものは７０μｍ１同じく８０μｍのものは１０
０μｍとより深く形成する必要がある。従って、前者の
場合、メサ溝部分の残り厚みは１００μｍ−２０μｍ−
８０μｍとなり、対象がサイリスク素子であれば１００
μｍ−（２０Ｘ２）μｍ−６０μｍとなって、第５図に
示すように、極めて大口径半導体ウェハは割れ易いこと
が分かる。In the case of a square chip, it is necessary to form a mesa groove in at least one direction along the crystal axis so that it is easy to push and break a large diameter semiconductor wafer in the final expansion process. Therefore, mesa grooves are dug in places where cleavage cracks are naturally likely to occur, and the thickness of the emitter region relative to the base region is generally determined by the thickness of the base region (NB) (Fig. 4 (Fig. 4)).
dl)), the emitter area is 50μm compared to 100μm.
Similarly, the emitter region is large at 80 μm compared to 400 μm for the base. Moreover, the mesa groove needs to be dug deeper into the base region than the emitter region, so the final depth of the mesa trench is that the emitter region is 5
0μm is 70μm1 Similarly, 80μm is 10
It is necessary to form it deeper to 0 μm. Therefore, in the former case, the remaining thickness of the mesa groove portion is 100 μm-20 μm-
80 μm, and 100 μm if the target is a Cyrisk element.
μm-(20×2) μm-60 μm, and as shown in FIG. 5, it can be seen that extremely large-diameter semiconductor wafers are easily broken.
上記のような従来の電力サイリスク素子の構造および製
法では、大口径半導体ウェハ１に縦および横方向に直線
状に掘設したメサ溝に沿ってウェハ１が破れ易いこと（
第５図参照）、熱補償板９と千ツブ６とを合金固着する
ときにアルミニウム、アルミニウム・シリコン合金１０
などのろう材のはみ出し１０ａの影響でガラスパッシベ
ーション領域５を破壊すること（第４図ｆｄｌ参照）、
角形チップ６の場合はゲート点弧からＮ Ｅ ｊＪｆ域
４の全域に点弧電流が広がる際に隅の部分に遅れが生じ
てしまうこと、合金固着時の熱ストレスも角形チップ６
の隅の部分で高くなったりして取扱上破損し易いことな
ど、多くの欠点があった。With the structure and manufacturing method of the conventional power silicon risk element as described above, the wafer 1 is easily torn along the mesa grooves that are linearly dug in the vertical and horizontal directions in the large-diameter semiconductor wafer 1 (
(See Fig. 5), aluminum, aluminum-silicon alloy 10
Destruction of the glass passivation region 5 due to the influence of the protruding brazing material 10a (see Fig. 4 fdl),
In the case of the square chip 6, when the ignition current spreads from the gate ignition to the entire area of the N E
It had many drawbacks, such as being high at the corners and being easily damaged during handling.
本発明はこのような点に鑑みてなされたものであり、そ
の目的とするところは、大口径半導体ウェハがメサ溝に
沿って破損することを防止し、分断されたチップを熱補
償板と合金固着する際にガラスパッシベーション領域が
ろう材で、破壊されないようにすること、また、点弧が
ＮＥ領域全域に速く拡大するようにすること、さらに、
角形チップの場合に生じ易い合金固着時の隅の部分での
熱ストレスおよび破損を防止することにある。The present invention has been made in view of these points, and its purpose is to prevent large-diameter semiconductor wafers from being damaged along mesa grooves, and to prevent separated chips from being damaged by alloying them with a thermal compensating plate. To ensure that the glass passivation area is not destroyed by the brazing material during fixing, and to ensure that the ignition spreads rapidly throughout the NE area, and
The purpose is to prevent thermal stress and breakage at the corners when the alloy is fixed, which tends to occur in the case of square chips.
このような目的を達成するために本発明は、主面にリン
グ状の溝が形成された円形の熱補償板と、両主面の外周
に外縁と同心円のメサ溝が形成され、一方の主面に電極
材料が設置され、他方の主面が熱補償板の主面側にリン
グ状の溝にメサ溝が対向するような位置関係で合金固着
された円形チップとから電力半導体素子を構成するよう
にしたものである。In order to achieve such an object, the present invention has a circular heat compensating plate having a ring-shaped groove formed on its main surface, a mesa groove concentric with the outer edge formed on the outer periphery of both main surfaces, and one main surface having a ring-shaped groove formed thereon. A power semiconductor element is constituted by a circular chip having an electrode material placed on one surface and an alloy fixed to the other main surface in such a positional relationship that a mesa groove faces a ring-shaped groove on the main surface side of a heat compensator plate. This is how it was done.
また、電力半導体素子の製造方法として、大口径半導体
ウェハに円形チップ領域を拡散および写真製版により多
数個形成する工程と、円形チップ領域の両主面の外周に
円形チップ領域と同心円のメサ溝を各々独立して掘設し
たのちメサ溝にガラスパッシベーションを施す工程と、
円形チップ領域を囲んだメサ溝の外周を円形にくり抜い
て個々の円形チップと成す工程と、メサ溝の位置に対応
する個所に予め溝を掘設した熱補償板の主面にろう材を
設置する工程と、円形チップの主面と熱補償板とを合金
固着せしめる工程と、円形チップの他の主面に電極材料
を設置する工程とを設けるようにしたものでる。In addition, the manufacturing method for power semiconductor devices includes a process of forming a large number of circular chip regions on a large-diameter semiconductor wafer by diffusion and photolithography, and forming a mesa groove concentric with the circular chip region on the outer periphery of both main surfaces of the circular chip region. A process of applying glass passivation to the mesa grooves after excavating each mesa groove independently,
A process of hollowing out the outer periphery of the mesa groove surrounding the circular chip area to form individual circular chips, and installing a brazing material on the main surface of the heat compensator plate with grooves previously dug at locations corresponding to the mesa groove positions. The method includes a step of bonding the main surface of the circular chip to the heat compensating plate with an alloy, and a step of installing an electrode material on the other main surface of the circular chip.
本発明においては、余剰ろう材は熱補償板の溝に流れ込
み、ガラスパッシベーション領域が破壊されることはな
い。In the present invention, excess brazing filler metal flows into the grooves of the heat compensator plate and does not destroy the glass passivation area.
まず、本発明の概要について述べると、本発明に係わる
電力半導体素子はメサ溝が円形であり、各々の円形溝が
重なることなく独立しており、しかも半導体のへき開方
向が直線であることと無関係である。このため、へき開
方向で大口径半導体ウェハが割れることを大幅に回避す
ることができる。First, to give an overview of the present invention, the power semiconductor device according to the present invention has a circular mesa groove, each circular groove is independent without overlapping, and the cleavage direction of the semiconductor is straight. It is. Therefore, it is possible to largely prevent the large-diameter semiconductor wafer from being broken in the cleavage direction.
第１図は本発明に係わる電力半導体素子の一実施例を示
す斜視図および断面図である。第１図（ａｌにおいて、
■は大口径半導体ウェハ、３はゲート領域となるＰ＋領
域、１１は公知の方法により形成した円形チップ領域、
１２は陰極となるＮ ｔ ６５域、１３は化学エツチン
グにより個々のチップに独立して掘設したメサ溝に鉛系
ガラス例えば米国イノチック社のＩＰ７６０ＴＦを塗布
したガラスパッシベーション領域であり、破線は個々の
チップに（り抜くための仮想線である。なお、サイリス
クチップであれば、他主面側にも同様のメサ溝を同時に
形成して、ガラスパッシベーション領域を形成するが、
図は省略する。FIG. 1 is a perspective view and a sectional view showing an embodiment of a power semiconductor device according to the present invention. Figure 1 (in al.
2 is a large-diameter semiconductor wafer, 3 is a P+ region that becomes a gate region, 11 is a circular chip region formed by a known method,
12 is a N t 65 region which becomes a cathode, 13 is a glass passivation region in which lead-based glass, such as IP760TF from Inochik of the United States, is applied to mesa grooves independently dug in each chip by chemical etching. This is an imaginary line for drilling into the chip.In addition, if it is a SIRISK chip, similar mesa grooves are simultaneously formed on the other main surface side to form a glass passivation region,
Illustrations are omitted.
このような構成のウェハにおいては、両生面にメサ溝が
形成された後の機械的な強度は元のウェハに比べて大き
く減少する訳であるが、前述したように角形チップに比
べてへき開割れの機会が極めて少なく、ウェハの加工処
理ラインにおけるへき開割れ率は激減する。In a wafer with such a configuration, the mechanical strength after mesa grooves are formed on the bidirectional surface is greatly reduced compared to the original wafer, but as mentioned above, cleavage cracking is more likely to occur than with square chips. There are extremely few opportunities for this to occur, and the cleavage cracking rate on the wafer processing line is drastically reduced.
次に、第２図（ａ）および第２図（ｂ）に示すように、
円形のガラスパッシベーション領域１３の外周に円筒形
のダイヤモンドブレード１８を当接し、これを高速で回
転させて第１図（ｂｌのような円形チップ１４をくり抜
く。さらに、第１図（Ｃ，ｌおよび第１図（ｄｌに示す
ように、予め円周状の溝１７ａを掘設したモリブデン板
１７の主面にアルミニウム１０を蒸着し、円形チップ１
４を合金固着する。そして、円形チップ１４のＮゆ領域
１２およびＰ′″領域３にそれぞれアルミニウムを厚く
蒸着し、それぞれ陰極１５およびゲート極１６を形成し
て、電力半導体素子とする。Next, as shown in FIG. 2(a) and FIG. 2(b),
A cylindrical diamond blade 18 is brought into contact with the outer periphery of the circular glass passivation region 13 and rotated at high speed to cut out a circular chip 14 as shown in FIG. 1 (bl). As shown in FIG. 1 (dl), aluminum 10 is vapor-deposited on the main surface of a molybdenum plate 17 in which a circumferential groove 17a has been dug in advance, and a circular chip 1
4 is fixed to the alloy. Then, aluminum is deposited thickly on the N region 12 and the P'' region 3 of the circular chip 14 to form a cathode 15 and a gate electrode 16, respectively, to form a power semiconductor device.
第３図は第１図（ｄｌの示す素子を拡大して詳細に示す
拡大断面図である。FIG. 3 is an enlarged sectional view showing in detail the element shown in FIG. 1 (dl).
上記電力半導体素子においては、熱補償板と円形チップ
との合金固着による余剰ろう材が発生しても、第３図に
示すように、熱補償板１７に設けた溝１７ａにろう材１
０が流れ込んでガラスパッシベーション領域１３を破壊
することがなく、しかも円形の溝１７ａであるので、加
工が極めて容易である。In the power semiconductor device described above, even if surplus brazing material is generated due to alloy adhesion between the heat compensating plate and the circular chip, as shown in FIG.
Since the glass passivation region 13 is not destroyed by zero flowing in and the groove 17a is circular, processing is extremely easy.
また、チップ形状が円形であるので、角形に比べてゲー
ト点弧データの広がりは当然均一になる。Further, since the chip shape is circular, the spread of gate firing data is naturally more uniform compared to a square chip shape.
このことは、特にセンタゲート構造の場合により明確に
なる。すなわち、円の中心にゲート極を配置すると、タ
ーンオンの際、まずゲート極に最も近い所よりターンオ
ンし、時間の経過と共に陰極全体に広がっていくが、チ
ップに流れる負荷電流の上昇率（ｄｉ／ｄｔ）が急峻な
場合は局部に過大な電流が集中して材料のシリコンを破
壊に至らしめることがある。ターンオン領域の広がり速
度は１０’ｃｍ／ｓｅｃ程度であり、陰極の外周がゲー
ト極に近づく程、ｄ ｉ ／ ｄ ｔに対して好ましい
ことが分かる。このために、特に電力半導体用のチップ
は円形の方が信頼性が高い。This becomes especially clear in the case of a center gate structure. In other words, if the gate electrode is placed in the center of the circle, when it is turned on, it will first turn on from the part closest to the gate electrode, and over time it will spread to the entire cathode, but the rate of increase in the load current flowing through the chip (di/ If dt) is steep, excessive current may concentrate locally and destroy the silicon material. The spreading speed of the turn-on region is about 10 cm/sec, and it can be seen that the closer the outer periphery of the cathode is to the gate electrode, the better it is for di/dt. For this reason, chips for power semiconductors in particular are more reliable when they are circular.
更に、合金固着工程では熱による膨張と収縮が発生する
が、材料シリコンと熱補償板例えばモリブデン板とは、
熱膨張率は近似こそすれども同一ではなく、必ず若干量
の歪応力を内在させることになる。この場合、角形のチ
ップであれば、構造的に歪応力を受は易く、チップは円
形の方が優れている。Furthermore, expansion and contraction occur due to heat during the alloy fixing process, but the silicon material and the heat compensating plate, such as a molybdenum plate,
Although the coefficients of thermal expansion are approximate, they are not the same, and there is always some inherent strain stress. In this case, a square chip is structurally more susceptible to strain stress, and a circular chip is better.
上述した電力半導体素子およびその製法においては、主
にサイリスクについて述べたが、これに限定せず、ＧＴ
Ｏサイリスク・逆導通サイリスク・トライチック・大容
量トランジスタ、ダイオード等のメサ形電力半導体素子
に応用できることはもちろんである。さらに、熱補償板
材料としてはモリブデンに限らず、タングステン・コバ
ール等の半導体シリコンと熱膨張率の近似したものでも
よく、円形チップにくり抜く手段としては、サンドブラ
スト法、エツチング法やレーザによる切断でも本発明の
実施に有効である。In the above-mentioned power semiconductor device and its manufacturing method, we mainly talked about cyrisk, but it is not limited to this.
Of course, it can be applied to mesa-type power semiconductor devices such as O-Sirisk, reverse conduction Sirisk, tritic, large-capacity transistors, and diodes. Furthermore, the material for the thermal compensator plate is not limited to molybdenum, but may also be a material with a coefficient of thermal expansion similar to that of semiconductor silicon, such as tungsten or kovar.Methods for hollowing out circular chips include sandblasting, etching, and laser cutting. Effective for carrying out the invention.
なお、ダイオードのようにガラスパッシベーションを１
主面のみに形成する場合は、熱補償板に溝を掘設する必
要はないが、ガラス焼付けで生ずるチップの両生面の熱
ストレスを打ち消すため、ガラスパッシベーション領域
を形成する場合は、熱補償板への溝形成は極めて有効で
ある。In addition, glass passivation is used like a diode.
It is not necessary to dig a groove in the thermal compensator plate when forming it only on the main surface, but if a glass passivation area is formed to cancel the thermal stress on the bidirectional surfaces of the chip caused by glass baking, it is necessary to dig a groove in the thermal compensator plate. Forming grooves in the grooves is extremely effective.
以上説明したように本発明は、チップ形状を円形にし、
各々独立したメサ溝とし、熱補償板にメサ溝に合う溝を
設けることにより、半導体のへき開方向が直線であるこ
とと無関係なものとすることができ、余剰ろう材を熱補
償板の溝に流し込むことができるので、大口径半導体ウ
ェハの破損を大幅に少なくすることができ、余剰ろう材
がガラスパッシベーション領域を破壊するのを防止でき
る効果がある。また、ターンオン広がりの均一化を図る
ことができ、角形チップに多い周縁部の破損を防止する
ことができる効果がある。As explained above, the present invention makes the chip shape circular,
By making each mesa groove independent and providing a groove that matches the mesa groove on the heat compensation plate, the cleavage direction of the semiconductor can be made independent of the fact that it is a straight line. Since it can be poured, damage to large-diameter semiconductor wafers can be significantly reduced, and excess brazing material can be prevented from destroying the glass passivation area. In addition, it is possible to make the turn-on spread uniform, and there is an effect that damage to the peripheral portion, which is common in square chips, can be prevented.
第１図〜第３図は本発明に係わる電力半導体素子の一実
施例およびその製造方法を示す斜視図および断面図、第
４図は従来の電力半導体素子およびその製造方法を示す
斜視図および断面図、第５図は従来の大口径半導体ウェ
ハの典型的な破損例を示す斜視図である。
１・・・大口径半導体ウェハ、３・・・Ｐ＋領域、１０
・・・アルミニウム、１１・・・円形チップ領域、１２
・・・Ｎｔｅｌ域、１３・・・ガラスパッシベーション
領域、１４・・・円形チップ、１５・・・陰極、１６・
・・ゲート極、１７・・・モリブデン板、１７ａ・・・
溝。1 to 3 are a perspective view and a sectional view showing an embodiment of a power semiconductor device according to the present invention and a method for manufacturing the same, and FIG. 4 is a perspective view and a sectional view showing a conventional power semiconductor device and a method for manufacturing the same. FIG. 5 is a perspective view showing a typical example of damage to a conventional large-diameter semiconductor wafer. 1... Large diameter semiconductor wafer, 3... P+ region, 10
... Aluminum, 11 ... Circular chip area, 12
... Ntel region, 13... Glass passivation region, 14... Circular chip, 15... Cathode, 16.
...Gate electrode, 17...Molybdenum plate, 17a...
groove.
Claims (2)
と、両主面の外周に外縁と同心円のメサ溝が形成され、
一方の主面に電極材料が設置され、他方の主面が前記熱
補償板の主面側に前記リング状の溝にメサ溝が対向する
ような位置関係で合金固着された円形チップとを備えた
ことを特徴とする電力半導体素子。(1) A circular heat compensator plate with a ring-shaped groove formed on its main surface, and a mesa groove concentric with the outer edge formed on the outer periphery of both main surfaces,
An electrode material is installed on one main surface, and the other main surface includes a circular chip having an alloy fixed to the main surface side of the heat compensator plate in a positional relationship such that a mesa groove faces the ring-shaped groove. A power semiconductor device characterized by:
び写真製版により多数個形成する工程と、前記円形チッ
プ領域の両主面の外周に前記円形チップ領域と同心円の
メサ溝を各々独立して掘設したのち前記メサ溝にガラス
パッシベーションを施す工程と、前記円形チップ領域を
囲んだ前記メサ溝の外周を円形にくり抜いて個々の円形
チップと成す工程と、前記メサ溝の位置に対応する個所
に予め溝を掘設した熱補償板の主面にろう材を設置する
工程と、前記円形チップの主面と熱補償板とを合金固着
せしめる工程と、前記円形チップの他の主面に電極材料
を設置する工程とを備えたことを特徴とする電力半導体
素子の製造方法。(2) A step of forming a large number of circular chip regions on a large-diameter semiconductor wafer by diffusion and photolithography, and independently digging mesa grooves concentric with the circular chip regions on the outer periphery of both main surfaces of the circular chip regions. a step of applying glass passivation to the mesa groove after forming the mesa groove; a step of hollowing out the outer periphery of the mesa groove surrounding the circular chip region to form individual circular chips; A step of installing a brazing material on the main surface of the heat compensator plate in which grooves have been dug in advance, a step of fixing the main surface of the circular chip and the heat compensator plate with an alloy, and a step of installing an electrode material on the other main surface of the circular chip. A method for manufacturing a power semiconductor device, comprising the step of installing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19426786A JPS6350066A (en) | 1986-08-19 | 1986-08-19 | Power semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19426786A JPS6350066A (en) | 1986-08-19 | 1986-08-19 | Power semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6350066A true JPS6350066A (en) | 1988-03-02 |
Family
ID=16321782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19426786A Pending JPS6350066A (en) | 1986-08-19 | 1986-08-19 | Power semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6350066A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7776423B2 (en) | 2003-09-29 | 2010-08-17 | Dai Nippon Printing Co., Ltd. | Decorating sheet, decorated molded product, and in-injection-mold decorating method |
| US7968174B2 (en) | 2004-09-30 | 2011-06-28 | Dai Nippon Printing Co., Ltd. | Decorative material having low-gloss pattern ink layer formed on part of a substrate and a surface protective layer on the pattern in K layer, and decorative plate including such material |
-
1986
- 1986-08-19 JP JP19426786A patent/JPS6350066A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7776423B2 (en) | 2003-09-29 | 2010-08-17 | Dai Nippon Printing Co., Ltd. | Decorating sheet, decorated molded product, and in-injection-mold decorating method |
| US7968174B2 (en) | 2004-09-30 | 2011-06-28 | Dai Nippon Printing Co., Ltd. | Decorative material having low-gloss pattern ink layer formed on part of a substrate and a surface protective layer on the pattern in K layer, and decorative plate including such material |
| KR101165111B1 (en) | 2004-09-30 | 2012-07-12 | 다이니폰 인사츠 가부시키가이샤 | Dressed lumber |
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