JPS635537A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS635537A JPS635537A JP61150341A JP15034186A JPS635537A JP S635537 A JPS635537 A JP S635537A JP 61150341 A JP61150341 A JP 61150341A JP 15034186 A JP15034186 A JP 15034186A JP S635537 A JPS635537 A JP S635537A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- heat sink
- grooves
- die
- depth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000000034 method Methods 0.000 claims description 10
- 229910000679 solder Inorganic materials 0.000 abstract description 16
- 230000035882 stress Effects 0.000 abstract description 14
- 230000002093 peripheral effect Effects 0.000 abstract description 3
- 230000008646 thermal stress Effects 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 229910000831 Steel Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002360 explosive Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83051—Forming additional members, e.g. dam structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.
し従来の技術〕
−ｍに、半導体装置は所定の大きさに形成されたヒート
−シンクの一表面上のソルダー上に半導体素子を位置決
めしダイボンディング処理によりソルダーを熔融したの
ち冷却して固着することにより作製されるものである。[Prior art]-m, a semiconductor device is manufactured by positioning a semiconductor element on a solder on one surface of a heat sink formed to a predetermined size, melting the solder by a die bonding process, and then cooling and fixing it. It is made by
ヒートシンクは、シリコンあるいはダイヤモンド等の薄
板（ウェハー）であり、半導体素子の放熱機能を有する
。ヒート−シンクの半導体素子の固着面はダイボンディ
ングによる爆着を確実・容易にするため表面にＴｉ。The heat sink is a thin plate (wafer) made of silicon or diamond, and has a heat dissipation function for the semiconductor element. The surface of the heat sink to which the semiconductor element is fixed is coated with Ti to ensure and facilitate explosive bonding by die bonding.
Ｐｔ、およびＳｎ、またはＡｕＳｎ合金が金属層として
蒸着されている。Pt and Sn or AuSn alloys are deposited as metal layers.
従来の一例について第４図（ａ）・（ｂ）および第５図
（ａ）・ （ｂ）を参照して説明する。第４図（ａ）・
（ｂ）のそれぞれはヒートシンク上に半導体素子を固
着した従来の半導体装置の一例を示す平面図およびＥ−
Ｅ縦断面図、また第５図（ａ）・（ｂ）のそれぞれは半
導体素子を配設する以前の第４図のヒート−シンクを示
す正面図およびＤ−Ｄ断面図である。A conventional example will be explained with reference to FIGS. 4(a) and 5(b) and FIGS. 5(a) and 5(b). Figure 4(a)・
(b) is a plan view showing an example of a conventional semiconductor device in which a semiconductor element is fixed on a heat sink, and E-
E longitudinal sectional view, and FIGS. 5(a) and 5(b) are a front view and a DD sectional view showing the heat sink of FIG. 4 before a semiconductor element is disposed thereon.
第４図（ａ）・ （１つ）において半導体装置はヒート
シンク３０にソルダー４２をもって半導体素子４３を固
着したものである。ヒートシンク３０は平坦な薄板状で
あり上面の所定位置の所定量のソルダー４２によって半
導体素子４３が固着されている。第５図（ａ）・ （ｂ
）に示すようにヒートシンク３０の平坦な上面の所定位
置には所定量のソルダー３１が配設される。半導体装置
は半導体素子（図示されず）をペレットとしてソルダー
３１の上に配設し、ダイボンデング処理によりソルダー
３１を加熱熔融させて半導体素子をヒートシンク３０に
熔着させて作成する。In the semiconductor device shown in FIG. 4(a) (one), a semiconductor element 43 is fixed to a heat sink 30 with a solder 42. The heat sink 30 has a flat thin plate shape, and a semiconductor element 43 is fixed thereto by a predetermined amount of solder 42 at a predetermined position on the upper surface. Figure 5 (a) and (b)
), a predetermined amount of solder 31 is disposed at a predetermined position on the flat upper surface of the heat sink 30. The semiconductor device is manufactured by disposing a semiconductor element (not shown) in the form of a pellet on a solder 31, heating and melting the solder 31 through a die bonding process, and welding the semiconductor element to the heat sink 30.
また、半導体装置は製造工程でヒートシンクの下面が鋼
材のような熱伝導率の高い材質のステムに固定されてボ
ンディング処理工程に入る。半導体装置が例えば半導体
レーザで光半導体素子をＧａＡｓ、ヒートシンクをシリ
コン、またステムを鋼材により製造される場合、それぞ
れの素材の熱膨張係数は６．８６ Ｘ １０−６／”Ｃ
・２．６Ｘ１０−’／℃・１．６５ ｘ １０−５／”
Ｃである。ダイボンデイン・グ処理を２５０〜２６０℃
で行ない、ソルダーによる応力緩和等を無視する場合、
半導体素子の中央でのヒートシンクとの密着部の応力は
５ Ｘ １０８ダイン／ ｃｒａ ２となる。Further, during the manufacturing process of a semiconductor device, the lower surface of the heat sink is fixed to a stem made of a material with high thermal conductivity, such as steel, and then enters a bonding process. If a semiconductor device is, for example, a semiconductor laser, and the optical semiconductor element is made of GaAs, the heat sink is made of silicon, and the stem is made of steel, the coefficient of thermal expansion of each material is 6.86 x 10-6/"C.
・2.6X10-'/℃・1.65 x 10-5/"
It is C. Die bonding treatment at 250-260℃
If you ignore stress relaxation etc. due to solder,
The stress at the center of the semiconductor element in close contact with the heat sink is 5×108 dynes/cra2.
通常の半導体レーザは１０８ダイン／Ｃ１１２を超える
応力ではすべり転位が発生する可能性を有する。Ordinary semiconductor lasers have the possibility of generating slip dislocations under stress exceeding 108 dynes/C112.
上述のように従来の半導体装置は熱伝導率の高いステム
に固定したヒートシンクの平坦な上面に半導体素子を配
設し、加熱してソルダーを熔融させることにより熔着し
て製造しているので、ステム、ヒートシンクおよび半導
体素子それぞれの熱膨張係数の違いにより半導体素子に
大きな熱応力が発生し、半導体素子にすべり転位が発生
して信頼性が低下することがあるという問題点があった
。As mentioned above, conventional semiconductor devices are manufactured by placing a semiconductor element on the flat top surface of a heat sink fixed to a stem with high thermal conductivity, and welding it by heating and melting the solder. There has been a problem in that a large thermal stress is generated in the semiconductor element due to the difference in the coefficient of thermal expansion of the stem, the heat sink, and the semiconductor element, which may cause slip dislocation in the semiconductor element and reduce reliability.
本発明の目的は上記問題点を解決した半導体装１を提供
することにある。An object of the present invention is to provide a semiconductor device 1 that solves the above problems.
本発明による半導体装１は半導体素子をダイボンディン
グ処理する側の面上で且つダイボンディングされた半導
体素子の外周部分に溝を形成したヒートシンクを有する
。The semiconductor device 1 according to the present invention has a heat sink in which a groove is formed on the side on which the semiconductor element is die-bonded and in the outer peripheral portion of the die-bonded semiconductor element.
次に本発明の半導体装置について図面を参照して説明す
る。Next, the semiconductor device of the present invention will be explained with reference to the drawings.
第１図（ａ）は本発明の一実施例を示す平面図・第１図
（ｂ）・（ｃ）はそれぞれ第１図（ａ）のＡ−Ａ断面図
およびＢ−Ｂ断面図である。FIG. 1(a) is a plan view showing one embodiment of the present invention. FIGS. 1(b) and (c) are sectional views taken along line AA and line BB in FIG. 1(a), respectively. .
第１図（ａ）・ （ｂ） ・ （ｃ）において、ヒート
シンク１０は上面に溝１１を有し、ｉ１！１１で仕切ら
れた面の一つに半導体素子１３がソルダー１幅５０μｍ
・深さ１４０μｍの溝１１が縦方向１ｍｍ・横方向０．
５ ｍ ｍの間隔で形成される。またヒートシンク１０
は図示されるように縦方向の満１１がほぼ中央に、また
横方向の溝１１はそれぞれ外縁から０．２５ ｍ ｍの
位置になるように１ｍｍの間隔で２０〜３０μｍ残して
切取られて形成される。ヒートシンク１０の表面はダイ
ボンディング処理のための金属層が蒸着され、更に金属
マスクによりヒートシンク１０の溝１１により形成され
る台面にソルダー１２となる金属層により半導体素子１
３が熔着されている。ソルダー１２は半導体素子１３を
熔着すると共に半導体素子１３の周辺の溝１１に落ち込
み固形化して熔着する。In FIGS. 1(a), (b), and (c), the heat sink 10 has a groove 11 on its upper surface, and a semiconductor element 13 is placed on one of the surfaces partitioned by i1!11 with a solder 1 having a width of 50 μm.
- Groove 11 with a depth of 140 μm is 1 mm in the vertical direction and 0.0 mm in the horizontal direction.
They are formed at intervals of 5 mm. Also heat sink 10
As shown in the figure, the vertical grooves 11 are cut out approximately at the center, and the horizontal grooves 11 are cut out at 1 mm intervals, leaving 20 to 30 μm, so that each groove is 0.25 mm from the outer edge. be done. A metal layer for die bonding processing is deposited on the surface of the heat sink 10, and a metal layer that becomes a solder 12 is formed on the base surface formed by the grooves 11 of the heat sink 10 using a metal mask to bond the semiconductor element 1.
3 is welded. The solder 12 welds the semiconductor element 13, falls into the groove 11 around the semiconductor element 13, solidifies, and welds the semiconductor element 13.
半導体素子１３の中央部でヒートシンク１０との接着部
分の応力と、？４１１の深さとの関係は第２図に一例を
示して説明する。第２図は半導体素子（ＧａＡｓ）の厚
さ１００μｍ−幅２００ａｍ、並びにシリコンヒートシ
ンクの厚さ２８０μｍ・幅１ｍｍの例における溝の深さ
〔μｍ〕に対する主応力〔ダイン／Ｃ１１〕値を有限要
素法（ツィエンキーウ“′イッツ：基礎工学におけるマ
トリクス有限要素法等参照）によって求めた応力の変化
を示す図である。The stress at the bonded part to the heat sink 10 at the center of the semiconductor element 13 and ? The relationship with the depth of 411 will be explained by showing an example in FIG. Figure 2 shows the principal stress [dyne/C11] value with respect to groove depth [μm] in an example of a semiconductor element (GaAs) with a thickness of 100 μm and a width of 200 am, and a silicon heat sink with a thickness of 280 μm and a width of 1 mm using the finite element method. FIG. 2 is a diagram showing changes in stress determined by (Zienkiewiw "'its: matrix finite element method in basic engineering, etc.)".
第２図で示されるように、溝の深さが小さい範囲では半
導体素子中央部の主応力は大きく、溝の深さが大きく深
くなるにしたがって主応力は小さくなり、特にこの例で
は深さが１２０μｍ以上で主応力が１０８ダイン／ｃｍ
２以下となる。しかし、深い溝はヒートシンクの厚さが
小さいので機械的強度を小さく弱くすると共に溝の底部
がくびれでネックとなり放熱特性も悪化させる。従って
、この実施例では厚さ２８０μｍのヒートシンクに対し
て１４０ＡＬｍの深さの溝を設けた。溝の深さはヒート
シンクの材質および厚さ、並びに放熱性と機械強度との
何れを重視するかによって最適値が決められる。As shown in Figure 2, the principal stress at the center of the semiconductor element is large in the range where the depth of the groove is small, and as the depth of the groove increases, the principal stress decreases. Principal stress is 108 dynes/cm at 120 μm or more
2 or less. However, deep grooves reduce the thickness of the heat sink, resulting in a small and weak mechanical strength, and the bottom of the groove becomes a neck, which deteriorates heat dissipation characteristics. Therefore, in this example, a groove having a depth of 140 ALm was provided for a heat sink having a thickness of 280 μm. The optimum depth of the groove is determined depending on the material and thickness of the heat sink, and whether heat dissipation or mechanical strength is more important.
第３図（ａ）、（ｂ）は第１図（ａ＞において半導体素
子を爆着するまえのヒートシンクを示す正面図およびＣ
−Ｃ断面図である。ヒートシンク１０には縦・横に溝１
１が形成され、溝１１により形成される台形上面の一つ
にソルダー２２の金属層があり、半導体素子（図示され
ない）はソルダー２２の上に配置され、ダイボンディン
グ処理により爆着される。ヒートシンク１０の表面は爆
着の便宜のため周知の技術により金属層が形成されてい
る。FIGS. 3(a) and 3(b) are front views showing the heat sink before the semiconductor elements are bonded in FIG. 1(a) and C.
-C sectional view. The heat sink 10 has grooves 1 vertically and horizontally.
1 is formed, and a metal layer of a solder 22 is located on one of the upper surfaces of the trapezoid formed by the groove 11, and a semiconductor element (not shown) is placed on the solder 22 and is explosively bonded by a die bonding process. A metal layer is formed on the surface of the heat sink 10 by a well-known technique to facilitate explosive bonding.
上記実施例では半導体素子の材質をＧａＡｓ、ヒートシ
ンクとしてシリコン、且つステムとして銅を用いて説明
したが、他の材料においても応用できることは云うまで
もない。溝の間隔１幅、深さは一例を数値で示して説明
したが、半導体装置およびダイボンディング処理装置の
種類によりそれぞれの場合に最適化をはかって決定され
るもので形状も含め上記説明に限定されるものではない
。In the above embodiment, GaAs is used as the material of the semiconductor element, silicon is used as the heat sink, and copper is used as the stem, but it goes without saying that other materials can be used. Although the width and depth of the grooves have been explained using numerical values as an example, they are determined by optimizing each case depending on the type of semiconductor device and die bonding processing equipment, and are limited to the above explanation including the shape. It is not something that will be done.
以上に説明したように本発明の単導体装置は、爆着され
た半導体素子の外周部分のヒートシンク上に溝を有する
ことにより、半導体素子９ヒートシンク、およびステム
の材料の違いによる熱膨張係数差に起因し、ダイボンデ
ィング処理後に半導体素子に生ずる応力を大幅に軽減し
半導体装置のすべり転位の発生を防止できる効果がある
。As explained above, the single-conductor device of the present invention has grooves on the heat sink at the outer periphery of the exploded-bonded semiconductor element, so that differences in thermal expansion coefficient due to differences in the materials of the semiconductor element 9 heat sink and stem can be avoided. This has the effect of significantly reducing the stress generated in the semiconductor element after the die bonding process and preventing the occurrence of slip dislocations in the semiconductor device.
第１図（ａ）・（ｂ）・（Ｃ）は本発明の半導体装置の
一実施例を示す平面図、Ａ−Ａ断面図、およびＢ−Ｂ断
面図、第２図は第１図（ｃ）における溝の深さに対する
半導体素子中の応力変化図、第３図（ａ＞・（ｂ）のそ
れぞれは第１図（ａ）で半導体素子溶着前の正面図およ
びＣ−Ｃ断面図、第４図（ａ）・（ｂ）のそれぞれは従
来の一例を示す半導体°素子溶着前の正面図およびＥ−
Ｅ断面図、第５図（ａ）・（ｂ）のそれぞれは第４図（
ａ）において半導体素子溶着前の正面図およびＤ−Ｄ断
面図である。
１０．３０・・・・・・ヒートシンク、１１・・・・・
・溝、１２．２２．４２・・・・・・ソルダー、１３．
４３・・・・・・半導体素子。
（Ｃ）
￥３１図
［り゛イＡ−・］
４２図
′Ｊｆ５３図
ｔ（Ｌン
（Ｅ））
万４図
αす
（ｂ）
￥ｉ５図FIGS. 1(a), (b), and (C) are a plan view, an AA sectional view, and a BB sectional view showing one embodiment of the semiconductor device of the present invention, and FIG. The stress change diagram in the semiconductor element with respect to the groove depth in c), Figure 3 (a> and (b)) are the front view and C-C sectional view of the semiconductor element before welding in Figure 1 (a), respectively. FIGS. 4(a) and 4(b) respectively show a front view and an E-
Each of E cross-sectional views and Figures 5(a) and (b) is similar to Figure 4(
FIG. 3A is a front view and a cross-sectional view taken along line DD before the semiconductor element is welded in FIG. 10.30...Heat sink, 11...
・Groove, 12.22.42...Solder, 13.
43... Semiconductor element. (C) ￥31 figure [Riii A-・] 42 figure 'Jf53 figure t (Ln (E)) ￥4 figure αsu (b) ￥i5 figure
Claims (1)
ボンディング処理する半導体素子の外周部分に溝を形成
したヒートシンクを有することを特徴とする半導体装置
。1. A semiconductor device comprising a heat sink having a groove formed on a surface on which a semiconductor element is subjected to a die bonding process and in an outer periphery of a semiconductor element to be subjected to a die bonding process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61150341A JPS635537A (en) | 1986-06-25 | 1986-06-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61150341A JPS635537A (en) | 1986-06-25 | 1986-06-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS635537A true JPS635537A (en) | 1988-01-11 |
Family
ID=15494877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61150341A Pending JPS635537A (en) | 1986-06-25 | 1986-06-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS635537A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01310055A (en) * | 1988-06-03 | 1989-12-14 | Inax Corp | Tile sticking device to panel |
| JPH02274955A (en) * | 1989-04-17 | 1990-11-09 | Inax Corp | Device of applying tile to panel |
| JPH02274956A (en) * | 1989-04-17 | 1990-11-09 | Inax Corp | Device of applying tile to panel |
| US7235876B2 (en) * | 2005-09-12 | 2007-06-26 | Denso Corporation | Semiconductor device having metallic plate with groove |
| JP2019062245A (en) * | 2019-01-29 | 2019-04-18 | ローム株式会社 | Semiconductor device |
| US10777542B2 (en) | 2014-03-04 | 2020-09-15 | Rohm Co., Ltd. | Power semiconductor module for an inverter circuit and method of manufacturing the same |
-
1986
- 1986-06-25 JP JP61150341A patent/JPS635537A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01310055A (en) * | 1988-06-03 | 1989-12-14 | Inax Corp | Tile sticking device to panel |
| JPH02274955A (en) * | 1989-04-17 | 1990-11-09 | Inax Corp | Device of applying tile to panel |
| JPH02274956A (en) * | 1989-04-17 | 1990-11-09 | Inax Corp | Device of applying tile to panel |
| US7235876B2 (en) * | 2005-09-12 | 2007-06-26 | Denso Corporation | Semiconductor device having metallic plate with groove |
| US10777542B2 (en) | 2014-03-04 | 2020-09-15 | Rohm Co., Ltd. | Power semiconductor module for an inverter circuit and method of manufacturing the same |
| JP2019062245A (en) * | 2019-01-29 | 2019-04-18 | ローム株式会社 | Semiconductor device |
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