JPS6142854B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention controls the carrier lifetime.
The present invention relates to a method of manufacturing a semiconductor device having a PN junction.

In order to shorten the charge accumulation time in semiconductor devices with PN junctions formed, various methods have been used to introduce lifetime killers, which act as recombination centers for minority carriers, into semiconductor devices by proton injection, gold diffusion, etc. .

The introduction of a lifetime killer, which serves as a recombination center, by proton injection, gold diffusion, etc. has the problem of extremely poor controllability.

For example, in the case of the gold diffusion method, the heat treatment for gold diffusion requires setting the temperature and time with careful consideration of the thickness of the silicon substrate. It is technically very difficult to control the gold concentration distribution because gold is concentrated or segregated in the crystal defects that have formed.

On the other hand, in the case of the proton injection method, the number of crystal defects that become recrystallization centers formed by proton injection is 500.
Since it tends to be easily destroyed by heat treatment at a low temperature of about 600 °C to 600 °C, there is a problem that a manufacturing process that involves heat treatment at 500 °C or higher cannot be used in the process of semiconductor devices after proton implantation.

The present invention is a novel method that solves the above problems by accurately forming a stable crystal defect layer at a predetermined position with good reproducibility even through heat treatment, which is the center of recombination.
This provides a method for manufacturing a semiconductor device having a PN junction, in which a predetermined amount of silicon ions are implanted into a single-conductivity single crystal layer on a silicon substrate using an ion implantation method to form an amorphous layer with a predetermined thickness. Then, after implanting a predetermined amount of impurity ions of the opposite conductivity type to a shallower depth than the silicon ions to form an impurity implanted region on the surface of the amorphous layer, heat treatment is performed at a temperature of 450°C to 600°C to form the amorphous layer. Recrystallizing the surface of the amorphous layer including the PN junction formed between the crystalline layer and the impurity implanted region, and forming a crystal lattice defect layer near the interface between the amorphous layer and the single crystal layer. Features.

Next, embodiments of the present invention will be described with reference to the drawings.

1 to 4 show a part of the manufacturing process of a silicon substrate for a switching diode.

Figure 1 shows a silicon substrate 1 with an n ⁺ type carrier concentration of 10 ¹⁵ cm ^{-3 and} an n type carrier concentration of 10 ²⁰ cm with a thickness of about 10 μ.
³ shows a silicon single crystal substrate on which an epitaxial layer 3 of -3 is formed.

A dose of 5× is applied to the surface of such a single crystal substrate using an ion implantation method with an implantation energy of 150KeV.
10 ¹⁵ cm ^-3 of silicon (Si ⁺ ) is implanted to form an amorphous layer 3 as shown in FIG. Next, boron fluoride ions (BF ₂ ⁺ ) were implanted at a dose of 1×10 ¹⁵ cm ^-2 using a third implantation method with an implantation energy of 45 KeV.
As shown in the figure, impurity is implanted into the surface of the amorphous layer to form an impurity implanted region 4.

Next, when heat treatment is performed for 100 minutes in a nitrogen atmosphere at 550°C, the amorphous layer 3 is recrystallized from the substrate surface to form a single crystal layer 2', as shown in FIG. Only the bottom of the layer 3, that is, the interface with the n-type epitaxial layer 2 remains in an amorphous state. The portion remaining in this amorphous state becomes the crystal lattice defect layer 5. By this heat treatment, the impurity implanted region 4 on the surface of the amorphous layer 3 is also recrystallized to become a single crystal layer 4'.

Figures 5 and 6 show the results of investigating the process by which an amorphous layer formed by Si ⁺ and BF ₂ ⁺ implantation is recrystallized by heat treatment using the helium ion backscattering method. The axis shows the number of channels, that is, the depth [Å] from the substrate surface, and the vertical axis shows the number of counts per channel. In Figure 5,
51 is immediately after Si ⁺ and BF ₂ ⁺ implantation, 52 is Si ⁺ and BF ₂ ⁺
53 shows the results after heating in a nitrogen atmosphere at 550° C. for 10 minutes after injection, and after heating at 550° C. for 100 minutes.

The amorphous layer formed from the crystal surface to a thickness of about 230 Å, as shown at 51 in Figure 5, gradually recrystallizes as shown in 52 through heat treatment, and when heated further, becomes as shown in 53. The peak D in the figure becomes noticeable, and a residual defect layer is formed near the interface between the amorphous layer and the single crystal substrate, that is, at a depth of about 2300 Å from the substrate surface. The peak D in the figure becomes prominent, and a residual defect layer is formed near the interface between the amorphous layer and the single crystal substrate, that is, at a depth of about 2300 Å from the substrate surface.

In FIG. 6, 61 is the same sample as 53 in FIG. 5, and 62 is the result of examining a silicon substrate before ion implantation, about 2300 Å from the substrate surface.
The fact that 61 and 62 overlap to a depth near , indicates that the amorphous layer formed by ion implantation has recovered the same crystallinity as the silicon substrate before implantation.

It should be noted that if the heat treatment temperature for recrystallization is set to 450° C. or lower, the recrystallization rate is too slow to be practical. Furthermore, if the recrystallization treatment is performed at a temperature of 600° C. or higher, boron, which is a P ⁺ impurity, will be re-diffused and the PN junction position will change, which is not desirable.

Next, the substrate was etched away in the depth direction from the substrate surface after recrystallization treatment, and the PN judgment was performed by thermoelectromotive force measurement to measure the depth of the PN junction. As a result, the PN junction was found to be deeper than the substrate surface. It was formed at a depth of 1900 Å. This was consistent with the position of the PN junction established during BF ₂ ⁺ injection.

Using a silicon substrate having a PN junction formed in this way, a switching diode is formed by a normal switching diode forming process.
The switching speed of the diode was the same as the conventional one.

In addition, according to the conventional gold diffusion method, the switching speed varies from 5 μsec for each semiconductor substrate to approximately 100 μsec for a slow one even though the same manufacturing process is performed.
sec, but according to the present invention, a diode with a switching speed of 10 μsec was formed with good reproducibility with an error of about 20%.

As described above, according to the present invention, an amorphous layer of a predetermined thickness can be formed on a single crystal surface with good controllability by implanting silicon ions at a predetermined implantation energy and implantation amount. Since it is recrystallized in the treatment process and a crystal defect region is formed near the interface between the amorphous layer and the single crystal layer, a crystal defect layer centered on recombination is formed at a predetermined position with good reproducibility. At the same time, by implanting P-type impurities,
There is an advantage that a PN junction can be formed at a predetermined position and a semiconductor device having predetermined characteristics can be formed with good reproducibility.

[Brief explanation of the drawing]

Figures 1 to 4 are diagrams explaining some of the manufacturing steps according to the present invention, and Figures 5 and 6 are energy spectra obtained by backscattering experiments of helium ions, showing the crystallinity of the substrate. . DESCRIPTION OF SYMBOLS 1...Silicon single crystal substrate, 2...Epitaxial single crystal layer of one conductivity type, 3...Amorphous layer, 4...
Opposite conductivity type impurity layer, 5...crystal defect layer.

Claims (1)

[Claims] 1. A predetermined amount of silicon ions are implanted into a single conductivity type single crystal layer on a silicon substrate by an ion implantation method to form an amorphous layer with a predetermined thickness, and then a predetermined amount of inverse After implanting conductive type impurity ions to a shallower depth than the silicon ions to form an impurity implanted region on the surface of the amorphous layer, heat treatment is performed at a temperature of 450° C. to 600° C. to form the amorphous layer and the impurity implanted region. Manufacturing a semiconductor device characterized by recrystallizing the surface of an amorphous layer including a PN junction formed with and forming a crystal lattice defect layer near the interface between the amorphous layer and the single crystal layer. Method.