JPH06342805A - Manufacture of semiconductor device composed of silicon - Google Patents

Manufacture of semiconductor device composed of silicon

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Publication number
JPH06342805A
JPH06342805A JP3292664A JP29266491A JPH06342805A JP H06342805 A JPH06342805 A JP H06342805A JP 3292664 A JP3292664 A JP 3292664A JP 29266491 A JP29266491 A JP 29266491A JP H06342805 A JPH06342805 A JP H06342805A
Authority
JP
Japan
Prior art keywords
surface zone
amorphous
temperature
silicon
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3292664A
Other languages
Japanese (ja)
Other versions
JP2585489B2 (en
Inventor
Heinz-Achim Hefner
ヘフナー ハインツ−アッヒム
Joachim Imschweiler
イムシュヴァイラー ヨアヒム
Michael Seibt
ザイプト ミヒャエル
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefunken Electronic GmbH
Original Assignee
Telefunken Electronic GmbH
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Filing date
Publication date
Application filed by Telefunken Electronic GmbH filed Critical Telefunken Electronic GmbH
Publication of JPH06342805A publication Critical patent/JPH06342805A/en
Application granted granted Critical
Publication of JP2585489B2 publication Critical patent/JP2585489B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE: To enable a planar junction where an amorphous surface layer is surely crystallized without defects to be manufactured in silicon by a method, wherein final and short heating is carried out at temperatures sufficiently high to activate injected impurity atoms and for a sufficiently short time to keep impurities small in redistribution. CONSTITUTION: A collector electrode 2 and a collector electrode 3 both embedded are formed on a semiconductor substrate 1. A P<+> -doped polysilicon layer 4 is made to serve as both a base electrode and a dopant source for the formation of an extrinsic base 5 by diffusion and penetration. After another coating layer has been formed, an extrinsic base 6 is turned amorphous by a germanium injection. Dopant which is contained in the base region 6 is activated by a short heating, carried out at a temperature of 1000 to 1200 deg.C, and an emitter region 9 is diffused and penetrated. Furthermore, a short-time heating is varied by 5 to 30 seconds, whereby a transistor with a base large in width is manufactured.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、表面帯域のアモルファ
ス化、熱処理による前記表面領域の次のド−ピングおよ
びこの表面帯域の最終的な再結晶化のために、珪素イオ
ンまたはゲルマニウムイオンの注入による珪素の中の平
面接合の製造方法に関する。更に、本発明は、かかる平
面接合を有する半導体構成部材に関する。The invention relates to the implantation of silicon or germanium ions for the amorphization of the surface zone, the subsequent doping of said surface zone by heat treatment and the final recrystallization of this surface zone. The present invention relates to a method for manufacturing a plane junction in silicon according to. Furthermore, the invention relates to a semiconductor component having such a planar bond.

【０００２】[0002]

【従来の技術】珪素の中に平面のｐｎ接合を製造するた
めに、単結晶の珪素の表面帯域が、珪素イオンまたはゲ
ルマニウムイオンの注入によって、アモルファスの状態
へ送りこまれる方法も使用される。有利に、この方法で
予め処理された帯域へ注入された、Ｂ、ＢＦ2 +、Ｐまた
はＡｓのようなド−ピング剤は、侵入深さ、変則的な
（加速された）拡散および通路形成を極めて強力に制限
している。急激なド−ピングの輪郭が発生する。固体相
のエピタキシャル成長によるアモルファス表面帯域の再
結晶化の場合、温度選択の際に、ド−ピングの輪郭を維
持しつづけるようにド−ピング剤が拡散し過ぎないよう
に気をつけねばらない。In order to produce planar pn junctions in silicon, a method is also used in which the surface zone of monocrystalline silicon is driven into the amorphous state by implantation of silicon or germanium ions. Advantageously, the doping agent, such as B, BF 2 + , P or As, injected into the zone pretreated in this way, has a penetration depth, anomalous (accelerated) diffusion and channel formation. Is extremely strongly restricted. A sharp doping contour occurs. In the case of recrystallization of the amorphous surface zone by epitaxial growth of the solid phase, care must be taken during temperature selection not to overdiffuse the doping agent so as to maintain the doping profile.

【０００３】”Ｊ．Ａｐｐｌ．Ｐｈｙｓ．５４巻、Ｎ
ｏ．１２、１９８３年１２月６８７９〜６８８９頁”に
は、再結晶化が、９２５℃の温度で２０分間に亘って行
われる方法が記載されている。"J. Appl. Phys. 54, N"
o. 12, December 1983, pages 6879-6899 "describes a method in which recrystallization is carried out at a temperature of 925 ° C for 20 minutes.

【０００４】欧州特許第０２０１５８５号明細書には、
アモルファス表面の再結晶化のための２段階工程が記載
され、この工程では半導体試料は、まず約３０分間６０
０℃で維持され、この場合、アモルファス層は、固体相
エピタキシャル（ＳＰＥ）によって、再結晶化され、引
き続き１秒以内に、注入されたド−ピング剤が活性化さ
れる１０００℃以上に加熱される。European Patent No. 02015585 describes
A two-step process for recrystallizing an amorphous surface is described, in which the semiconductor sample is first sintered for about 30 minutes 60
Maintained at 0 ° C., in which case the amorphous layer is recrystallized by solid phase epitaxial (SPE) and subsequently heated within 1 second to above 1000 ° C. at which the injected doping agent is activated. It

【０００５】この２つの公知の方法は、再結晶化した状
態で、アモルファスから結晶の材料の接合領域が見出さ
れる場所に、結晶構造における欠陥が存在するという欠
点を有する。これらの欠点とは、第１に積層欠陥および
転位欠陥であり、これらの欠陥は、接合の電気的性質を
損なうものである。The two known methods have the disadvantage that, in the recrystallized state, there are defects in the crystal structure where the junction regions of amorphous to crystalline material are found. These defects are firstly stacking faults and dislocation defects, which impair the electrical properties of the junction.

【０００６】”ＩＥＥＥ １９９０ Ｂｉｐｏｌａｒ
Ｃｉｒｃｕｉｔｓ ａｎｄ Ｔｅｃｈｎｏｌｏｇｙ Ｍ
ｅｅｔｉｎｇ ７．３、１６２〜１６５頁”の記載か
ら、アモルファス表面帯域と結晶ベ−ス材料との間の接
合領域の再結晶化の前に、４５０℃での温度過程で、３
０分間に亘って研磨するという方法は公知である。１０
７５℃および１０秒で、後に続く短時間の全快過程（Ｒ
ＴＡ）の場合に、表面帯域は再結晶化し、同時にド−ピ
ング剤は活性化される。これらの公知の方法を使用した
後に、確かに、もはや何ら、原因を接合領域に有するよ
うな欠陥を見出すことは出来なかったが、しかし、その
代りに高いＲＴＡ温度の故に、増幅された硼素拡散を甘
受しなければならない。"IEEE 1990 Bipolar
Circuits and Technology M
See, e.g. 7.3, pp. 162-165 ", prior to recrystallization of the junction region between the amorphous surface zone and the crystalline base material, a temperature process at 450 DEG C.
The method of polishing for 0 minutes is known. 10
At 75 ° C and 10 seconds, the short-term complete recovery process (R
In the case of TA), the surface zone recrystallizes and at the same time the doping agent is activated. After using these known methods, it was certainly no longer possible to find defects which had their origin in the junction region, but instead, instead of the amplified RTA temperature, the amplified boron diffusion was increased. Have to accept.

【０００７】[0007]

【発明が解決しようとする課題】本発明には、アモルフ
ァス表面層の欠陥の無い再結晶化が保証されるような珪
素中の平面接合（≦０．１マイクロメ−トル）の製造方
法を記載するという課題が課された。SUMMARY OF THE INVENTION The present invention describes a process for the production of planar junctions (.ltoreq.0.1 micrometer) in silicon which guarantees defect-free recrystallization of the amorphous surface layer. The subject was imposed.

【０００８】[0008]

【課題を解決するための手段】この課題は、請求項１の
特徴部に記載された方法により解決される。本発明の別
の有利な実施態様は、従属請求項より生じる。This problem is solved by the method described in the characterizing part of claim 1. Further advantageous embodiments of the invention result from the dependent claims.

【０００９】本発明は、以下に実施例に基づいて詳説さ
れる。The invention is explained in more detail below on the basis of examples.

【００１０】珪素の平面接合の製造のために、まずアモ
ルファス表面層が、単結晶の基礎物質上でイオンの注入
されることによって製造される。この場合、ＧｅＨ4／
Ｈ2の混合物が、イオンの供給源として使用され、この
場合、70Ｇｅアイソト−プまたは74Ｇｅアイソト−プが
アモルファス化剤として使用される。２・１０14ｃｍ-2
〜９・１０14ｃｍ-2のイオン配量の場合、注入剤のエネ
ルギ−は、５０ｋｅＶ〜１５０ｋｅＶの範囲内である。
３〜５・１０14ｃｍ-2のイオン配量の場合に約７０ｋｅ
Ｖのエネルギ−が、特に有利なものであることが判明し
た。For the production of planar junctions of silicon, an amorphous surface layer is first produced by implanting ions on a monocrystalline base material. In this case, GeH 4 /
A mixture of H 2 is used as a source of ions, in this case 70 Ge or 74 Ge isotope is used as amorphizing agent. 2 · 10 14 cm -2
For an ion dose of ~ 9 · 10 14 cm -2 , the energy of the implant is in the range of 50 keV to 150 keV.
Approximately 70 ke in the case of ion dose of 3 to 5 · 10 14 cm -2
The energy of V has been found to be particularly advantageous.

【００１１】このようにして、例えば、３・１０14ｃｍ
-2のイオン配量の場合に７０ｋｅＶのＧｅイオンの注入
は、約８５ｎｍのアモルファス層を生じた。基体に向か
って、約１５ｎｍの厚さを有する接合領域は接続し、該
接合領域の中で、基体のアモルファス層と結晶材料との
間の境界面は極めて目が粗くおよび該接合領域の中で結
晶島状構造もしくはアモルファス島状構造が、それぞれ
正反対の構造の領域内に存在している。前記の島状構造
を有する目の粗い接合帯域は、格子欠陥、殊に積層欠陥
および転位欠陥の形成のための種晶を、更に後の再結晶
化の際に製出する。In this way, for example, 3 · 10 14 cm
Implantation of 70 keV Ge ions for an ion dose of -2 resulted in an amorphous layer of about 85 nm. To the substrate, a junction region having a thickness of about 15 nm is connected, in which the interface between the amorphous layer of the substrate and the crystalline material is very open and in the junction region. The crystalline island structure or the amorphous island structure exists in the regions of the diametrically opposite structures. The coarse junction zone with the island structure described above produces seed crystals for the formation of lattice defects, in particular stacking faults and dislocation defects, during further recrystallization.

【００１２】次の処理工程において、アモルファス表面
層は、Ｂイオン、ＢＦ2 +イオン、ＰイオンまたはＡｓイ
オンの注入によって配量される。アモルファス層の中
で、注入されたイオンの異常な拡散および通路形成作用
は理想的な方法で抑えられる。イオンエネルギ−の選択
によって、所望のド−ピングの輪郭が調整できる。２・
１０14ｃｍ-2の配量の場合に２５ｋｅＶの注入エネルギ
−を、約７０ｋｅＶの場合でＢＦ2 +イオンおよびＧｅ前
アモルファス化の際に示した。In the next processing step, the amorphous surface layer is dosed by implantation of B ions, BF 2 + ions, P ions or As ions. In the amorphous layer, the abnormal diffusion of implanted ions and the path-forming effect are suppressed in an ideal way. By selecting the ion energy, the desired doping profile can be adjusted. 2.
An implantation energy of 25 keV for a dose of 10 14 cm -2 was shown for BF 2 + ions and Ge pre-amorphization at about 70 keV.

【００１３】アモルファス層の再結晶化には、目の粗い
接合帯域の研磨を惹起する、別の処理工程が先行する。
このために半導体試料は、窒素雰囲気の炉の中で約４０
０〜４６０℃の温度で約３０〜５０分間前処理される。
前記の温度では、まだアモルファス層の変換は起こらな
いが、しかし、分画した接合帯域は既に研磨され、この
場合殊に、アモルファス島状構造および結晶島状構造が
再形成する。Recrystallization of the amorphous layer is preceded by another processing step which causes the polishing of the open bond zone.
For this reason, the semiconductor sample is approximately 40 in a nitrogen atmosphere furnace.
It is pretreated at a temperature of 0 to 460 ° C. for about 30 to 50 minutes.
At these temperatures, conversion of the amorphous layer has not yet taken place, but the fractionated junction zones have already been polished, in which case especially amorphous and crystalline island structures are reformed.

【００１４】５００〜６００℃の温度で、３０〜５０分
間に亘って引き続き熱処理した場合に、アモルファス層
は固体相エピタキシャル成長によってサブストレ−トの
基礎結晶体の上に再結晶する。本来の再結晶化の前に目
の粗い接合帯域は研磨されたので、エピタキシャル成長
の後には、以前のアモルファス層中での積層欠陥および
転位欠陥は認められなかった。殊に、固体相エピタキシ
ャルのために窒素雰囲気中で４０分の間では５５０℃の
温度が、特に有利であることが判明した。Upon subsequent heat treatment at a temperature of 500 to 600 ° C. for 30 to 50 minutes, the amorphous layer recrystallizes on the substrate of the substratum by solid phase epitaxial growth. After the epitaxial growth, stacking faults and dislocation defects in the former amorphous layer were not observed since the coarse junction zone was polished before the original recrystallization. In particular, for solid phase epitaxy a temperature of 550 ° C. for 40 minutes in a nitrogen atmosphere has been found to be particularly advantageous.

【００１５】引き続き短時間の加熱は、ド−ピング原子
を１０００〜１１００℃の温度の場合に、ド−ピングの
輪郭が５〜１０秒の短い時間の間に本質的に幅が広がら
ずに活性化する。本来の再結晶化が、６００℃の温度で
行われ、ただ単にド−ピングが活性化されるので、この
処理工程中には結晶体の構成において何ら付加的な欠陥
は発生しない。Subsequent heating for a short period of time activates the doping atoms at a temperature of 1000 to 1100 ° C. without a broadening of the doping profile during a short period of 5 to 10 seconds. Turn into. Since the actual recrystallization takes place at a temperature of 600 ° C. and merely activates the doping, no additional defects in the crystal structure occur during this process step.

【００１６】上述の平面接合の典型的な使用の場合の例
は、双極性高周波トランジスタである。しかし、例えば
ダイオ−ドのような別の構成部材においても、かかる平
面接合は有利に使用してもよい。An example of a typical use of the above-mentioned planar junction is a bipolar high frequency transistor. However, such planar bonding may also be used to advantage in other components, such as diodes.

【００１７】[0017]

【実施例】図１は、１つのトランジスタを通った横断面
図を示し、そのベース帯域６を本発明による方法によっ
て製造した。以下に、図に基づいて、かかるトランジス
タの構成を詳説した。半導体サブストレ−ト１の上に、
公知の方法により、まず、埋設されたコレクタ電極２お
よびコレクタ３を製造した。ｐ+ド−ピングされたポリ
珪素層４を、ベ−ス電極としておよび源として、外性ベ
−ス５の拡散侵入のために使用した。別の被覆層の後
に、内性ベ−ス部６をゲルマニウムの注入によってアモ
ルファス化した。この場合、ゲルマニウムイオンのエネ
ルギ−は、７０ｋｅＶである。２・１０14ｃｍ-2の配量
を注入した。引き続き以前アモルファス化された帯域
を、２５ｋｅＶのエネルギ−および３・１０14ｃｍ-2の
配量を有するＢＦ2 +イオンの注入によってド−ピングし
た。アモルファスの材料に注入したので、理想的な分布
のド−ピング輪郭が発生した。注入されたイオンの通路
形成および異常な拡散を著しく減少させた。そして、ア
モルファス化された層を炉処理にて結晶させた。第１の
処理工程において、４５０℃で、アモルファス層と結晶
性のベ−ス結晶体との間の接合領域を研磨した。アモル
ファス層の再結晶化は、この処理工程の際には、まだ行
われなかった。それというのも、温度が固体相エピタキ
シャル成長にとっては、充分には高くなかったからであ
る。約４０分後に温度を、炉の中で５５０℃に上昇させ
た。この第２の処理工程においてアモルファス層は、４
０分の内に殆ど欠陥のない再結晶をした。それというの
も、接合領域中の欠陥種晶を先行の処理工程中にて除去
したからである。そして、短時間の加熱を用いてド−ピ
ング剤を活性化する前に、公知の方法によってポリ珪素
８を塗布し、その後に続いてＡｓ注入によってド−ピン
グした。このポリ珪素層８は、２つの機能を有する。一
方で、このポリ珪素層はエミッタ電極として使用され、
他方では、このポリ珪素層はエミッタ９のための拡散侵
入の源として作用するのである。そして、本発明による
熱処理の第３部が続くのである。１０００〜１２００℃
への短時間の加熱によって、ベ−ス帯域６のド−ピング
剤を活性化し、同時にエミッタ帯域９を拡散侵入させ
る。その上、５〜３０秒の範囲内で短時間の加熱の時間
を変化させることによって、トランジスタの幅の広いベ
−スを製造することが出来る。引き続き、表面不働態化
および金属化１０を公知の方法で実現化した。1 shows a cross-section through one transistor, the base band 6 of which was produced by the method according to the invention. The configuration of such a transistor is described in detail below with reference to the drawings. On the semiconductor substrate 1,
First, the buried collector electrode 2 and the buried collector 3 were manufactured by a known method. The p + -doped polysilicon layer 4 was used as a base electrode and as a source for the diffusion penetration of the external base 5. After another coating layer, the internal base 6 was made amorphous by implanting germanium. In this case, the energy of germanium ion is 70 keV. A dose of 2 · 10 14 cm −2 was injected. The previously amorphized zone was subsequently doped by implantation of BF 2 + ions with an energy of 25 keV and a dose of 3 · 10 14 cm −2 . Implanting into an amorphous material produced an ideal distribution of doping contours. It significantly reduced the passage formation and abnormal diffusion of the implanted ions. Then, the amorphized layer was crystallized by furnace treatment. In the first processing step, the bonding region between the amorphous layer and the crystalline base crystal was polished at 450 ° C. Recrystallization of the amorphous layer has not yet occurred during this processing step. This is because the temperature was not high enough for solid phase epitaxial growth. After about 40 minutes the temperature was raised to 550 ° C in the furnace. In this second processing step, the amorphous layer has 4
Recrystallization with almost no defects was carried out within 0 minutes. This is because the defect seed crystal in the bonding region was removed in the previous processing step. Then, before activating the doping agent by using heating for a short time, polysilicon 8 was applied by a known method, and subsequently, doping was performed by As implantation. This polysilicon layer 8 has two functions. On the other hand, this polysilicon layer is used as an emitter electrode,
On the other hand, this polysilicon layer acts as a source of diffusion penetration for the emitter 9. And the third part of the heat treatment according to the invention follows. 1000-1200 ° C
The heating for a short time activates the doping agent in the base zone 6 and at the same time causes the emitter zone 9 to diffuse and penetrate. Moreover, by changing the heating time for a short time within the range of 5 to 30 seconds, a wide base of the transistor can be manufactured. Subsequently, surface passivation and metallization 10 were realized by known methods.

【００１８】前記の方法で製造されたトランジスタを用
いて、約３０ＧＨｚの境界周波数を達成した。A boundary frequency of about 30 GHz was achieved with the transistor manufactured by the above method.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明により製造することができる、珪素から
なる半導体装置の１実施例を示す略字縦断面図。FIG. 1 is a schematic vertical sectional view showing an embodiment of a semiconductor device made of silicon which can be manufactured by the present invention.

【符号の説明】[Explanation of symbols]

１ 半導体サブストレート、 ２ コレクタ電極、 ３
コレクタ、 ４ ポリ珪素、 ５ 外性ベース、 ６
内性ベース、 ８ ポリ珪素、 ９ エミッタ1 semiconductor substrate, 2 collector electrode, 3
Collector, 4 polysilicon, 5 extrinsic base, 6
Internal base, 8 Polysilicon, 9 Emitter

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/265 8617−4Ｍ Ｈ０１Ｌ 21/265 Ｗ 8617−4Ｍ Ｑ (72)発明者 ハインツ−アッヒム ヘフナー ドイツ連邦共和国 ブラッケンハイム シ ュペルバーヴェーク 17 (72)発明者 ヨアヒム イムシュヴァイラー ドイツ連邦共和国 ハイルブロン−ベッキ ンゲン シャーフベルク 25 (72)発明者 ミヒャエル ザイプト ドイツ連邦共和国 ゲッティンゲン ペー ター デバイエ シュティーク 16─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI Technical indication location H01L 21/265 8617-4M H01L 21/265 W 8617-4M Q (72) Inventor Heinz-Achheim Hefner Federal Republic of Germany Brackenheim Supperberweg 17 (72) Inventor Joachim Im Schweiler Federal Republic of Germany Heilbronn-Beckingen Schafberg 25 (72) Inventor Michael Ziept Göttingen Peter Debayer Steig 16

Claims (9)

【特許請求の範囲】[Claims] 【請求項１】 半導体装置の製造のために、１つの単結
晶の半導体の表面に、電気的にニュ−トラルな、表面帯
域をアモルファス化するイオンが注入され、その後、表
面帯域が注入された不純物を用いてド−ピングされ、最
終的にアモルファス層が熱処理によって再結晶化される
ように、僅かな侵入深さの表面帯域を有する珪素からな
る半導体装置の製造方法において、熱処理が、まだアモ
ルファス層の再結晶化を起こさないが、しかし既にアモ
ルファス表面帯域と単結晶半導体との間の接合領域の研
磨が行われるように温度を選択した第１の炉処理工程
と、この第１の炉処理工程に続いて、アモルファス表面
帯域が再結晶化するには充分に高くかつ注入された不純
物原子の移動度が小さいままであるには充分に低い温度
の第２の炉処理工程と、この第２の炉処理工程に後続す
る最終的な短時間の加熱とからなり、この場合この温度
は、注入された不純物原子を活性化のに充分に高く、か
つ所要時間は不純物の再分布を小さく維持するために充
分に短いことを特徴とする、珪素からなる半導体装置の
製造法。1. For the manufacture of a semiconductor device, an electrically neutral ion for amorphizing a surface zone is implanted into the surface of a single-crystal semiconductor, and then the surface zone is implanted. In a method for manufacturing a semiconductor device made of silicon having a surface zone with a slight penetration depth, such that the amorphous layer is doped with impurities and finally the amorphous layer is recrystallized by the thermal treatment, the thermal treatment is still amorphous. A first furnace treatment step in which the temperature is selected so as not to cause recrystallization of the layer, but to already carry out the polishing of the junction region between the amorphous surface zone and the single crystal semiconductor; The process is followed by a second furnace treatment step at a temperature sufficiently high for the amorphous surface zone to recrystallize and low enough for the mobility of the implanted impurity atoms to remain low. This second furnace treatment step is followed by a final brief heating, where the temperature is high enough to activate the implanted impurity atoms and the time required is the redistribution of the impurities. A method for manufacturing a semiconductor device made of silicon, characterized in that it is sufficiently short to maintain a small value. 【請求項２】 表面帯域が、ゲルマニウムイオンまたは
珪素イオンの注入によってアモルファス化される、請求
項１記載の方法。2. The method of claim 1, wherein the surface zone is amorphized by implantation of germanium or silicon ions. 【請求項３】 表面帯域が、ゲルマニウムイオンの注入
によって、約７０ｋｅＶのエネルギ−および約３・１０
14ｃｍ-2の用量の場合にアモルファス化される、請求項
１または２記載の方法。3. The surface zone has an energy of about 70 keV and about 3.10 by implantation of germanium ions.
The method according to claim 1 or 2, which is amorphized at a dose of 14 cm -2 . 【請求項４】 表面帯域が、Ｂ、ＢＦ2 +、ＰまたはＡｓ
の注入によってド−ピングされる、請求項１から３まで
のいずれか１項記載の方法。4. The surface zone is B, BF 2 + , P or As.
4. The method according to any one of claims 1 to 3, wherein the method is doped by injection. 【請求項５】 表面帯域が、ＢＦ2 +注入によって、１５
ｋｅＶ〜２５ｋｅＶのエネルギ−および３・１０13ｃｍ
-2〜３・１０14ｃｍ-2の用量の場合にド−ピングされ
る、請求項１から４までのいずれか１項記載の方法。5. A surface zone of 15 by BF 2 + implantation.
Energy of keV to 25 keV and 3 · 10 13 cm
The method according to any one of claims 1 to 4, wherein the method is doped at a dose of -2 to 3 · 10 14 cm -2 . 【請求項６】 第１の炉処理工程が、４００〜４６０℃
の温度で、３０〜５０分間継続する請求項１から５まで
のいずれか１項記載の方法。6. The first furnace treatment step is 400 to 460 ° C.
6. The method according to claim 1, which lasts 30 to 50 minutes at the temperature of. 【請求項７】 第２の炉処理工程が、５００〜６００℃
の温度で、３０〜５０分間継続する請求項１から６まで
のいずれか１項記載の方法。7. The second furnace treatment step is performed at 500 to 600 ° C.
The method according to any one of claims 1 to 6, which is continued at the temperature of 30 to 50 minutes. 【請求項８】 短時間の加熱が、１０００〜１２００℃
の温度で、５〜３０秒間継続する請求項１から７までの
いずれか１項記載の方法。8. The heating for a short time is 1000 to 1200 ° C.
The method according to any one of claims 1 to 7, which lasts 5 to 30 seconds at the temperature of. 【請求項９】 双極性高周波トランジスタのベ−ス領域
を製造する方法において、請求項１から８までのいずれ
か１項記載の方法を使用することを特徴とする、双極性
高周波トランジスタのベ−ス領域を製造する方法。9. A method for producing a base region of a bipolar high-frequency transistor, characterized in that the method according to any one of claims 1 to 8 is used. Method for manufacturing an area.
JP3292664A 1990-11-10 1991-11-08 Method for manufacturing semiconductor device made of silicon Expired - Fee Related JP2585489B2 (en)

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DE4035842A DE4035842A1 (en) 1990-11-10 1990-11-10 METHOD FOR RECRISTALLIZING PREAMORPHIZED SEMICONDUCTOR SURFACE ZONES

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