JPS6142428B2 - - Google Patents

Info

Publication number
JPS6142428B2
JPS6142428B2 JP56047057A JP4705781A JPS6142428B2 JP S6142428 B2 JPS6142428 B2 JP S6142428B2 JP 56047057 A JP56047057 A JP 56047057A JP 4705781 A JP4705781 A JP 4705781A JP S6142428 B2 JPS6142428 B2 JP S6142428B2
Authority
JP
Japan
Prior art keywords
resin part
resin
chip
lead frame
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56047057A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57162352A (en
Inventor
Hideo Tanaka
Kyoshi Kakya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56047057A priority Critical patent/JPS57162352A/ja
Publication of JPS57162352A publication Critical patent/JPS57162352A/ja
Publication of JPS6142428B2 publication Critical patent/JPS6142428B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/18—Circuits for erasing optically
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP56047057A 1981-03-30 1981-03-30 Manufacture of resin-sealed semiconductor device Granted JPS57162352A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56047057A JPS57162352A (en) 1981-03-30 1981-03-30 Manufacture of resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56047057A JPS57162352A (en) 1981-03-30 1981-03-30 Manufacture of resin-sealed semiconductor device

Publications (2)

Publication Number Publication Date
JPS57162352A JPS57162352A (en) 1982-10-06
JPS6142428B2 true JPS6142428B2 (enrdf_load_stackoverflow) 1986-09-20

Family

ID=12764521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56047057A Granted JPS57162352A (en) 1981-03-30 1981-03-30 Manufacture of resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS57162352A (enrdf_load_stackoverflow)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4766095A (en) * 1985-01-04 1988-08-23 Oki Electric Industry Co., Ltd. Method of manufacturing eprom device
JPS61156249U (enrdf_load_stackoverflow) * 1985-03-18 1986-09-27
US5026667A (en) * 1987-12-29 1991-06-25 Analog Devices, Incorporated Producing integrated circuit chips with reduced stress effects
US6165816A (en) * 1996-06-13 2000-12-26 Nikko Company Fabrication of electronic components having a hollow package structure with a ceramic lid
KR101032337B1 (ko) 2002-12-13 2011-05-09 가부시키가이샤 한도오따이 에네루기 켄큐쇼 발광장치 및 그의 제조방법
JP2009267272A (ja) * 2008-04-29 2009-11-12 New Japan Radio Co Ltd 半導体中空パッケージ及びその製造方法
JP2010062232A (ja) * 2008-09-02 2010-03-18 Nec Electronics Corp 素子の機能部を露出させた半導体装置の製造方法

Also Published As

Publication number Publication date
JPS57162352A (en) 1982-10-06

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