JPS6139742B2 - - Google Patents
Info
- Publication number
- JPS6139742B2 JPS6139742B2 JP15129281A JP15129281A JPS6139742B2 JP S6139742 B2 JPS6139742 B2 JP S6139742B2 JP 15129281 A JP15129281 A JP 15129281A JP 15129281 A JP15129281 A JP 15129281A JP S6139742 B2 JPS6139742 B2 JP S6139742B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- metal film
- substrate
- film
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052751 metal Inorganic materials 0.000 claims description 32
- 239000002184 metal Substances 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 15
- 239000011347 resin Substances 0.000 claims description 12
- 229920005989 resin Polymers 0.000 claims description 12
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 229910052763 palladium Inorganic materials 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/62—Protection against overvoltage, e.g. fuses, shunts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
この発明は、特に外部サージ電圧に対する保護
回路を改善した集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit with improved protection circuitry, particularly against external surge voltages.
一般に過電圧等の外部サージ電圧の影響を受け
やすい環境に設けられる集積回路には、外部サー
ジに対する保護回路が必要である。例えば、自動
車用点火装置等に使用されるハイブリツド厚膜集
積回路には、その外部端子に点火火花等によつて
発生する外部サージ電圧が印加され、その点火火
花等のエネルギーが大きい場合には上記厚膜集積
回路の回路素子が破壊されることがある。このよ
うな外部サージ電圧に対して回路素子を保護する
ため、従来第1図A,Bに示すように集積回路1
1には保護回路が設けられる。すなわち、図Aに
示すように外部配線と内部回路12を接続するた
めの外部端子13に十分大きな容量を有するコン
デンサ14を設ける。このコンデンサ14からな
る保護回路によつて、外部サージのエネルギーを
吸収して内部回路12の回路素子を保護すること
ができる。また、図Bに示すようにコンデンサ1
4の代りに大きな電力特性を有するツエナーダイ
オード15を設けてもよい。しかしながら、この
ような保護回路では、大容量のコンデンサ14を
使用する場合、集積回路11の周波数応答の劣
化、チツプ面積の増大、および大容量のコンデン
サ14のコストが高いなどの欠点が生ずる。ま
た、ツエナーダイオード15を使用した場合に
は、集積回路11の入力信号等の振幅が制限され
て、ダイナミツクレンジが十分取れないなどの欠
点がある。 Generally, integrated circuits installed in environments susceptible to external surge voltages such as overvoltage require a protection circuit against external surges. For example, an external surge voltage generated by an ignition spark is applied to a hybrid thick film integrated circuit used in an automobile ignition system, etc. to its external terminal, and if the energy of the ignition spark is large, the above-mentioned Circuit elements of thick film integrated circuits may be destroyed. In order to protect circuit elements from such external surge voltages, an integrated circuit 1 is conventionally constructed as shown in FIGS.
1 is provided with a protection circuit. That is, as shown in FIG. A, a capacitor 14 having a sufficiently large capacitance is provided at the external terminal 13 for connecting the external wiring and the internal circuit 12. The protection circuit made up of the capacitor 14 can protect the circuit elements of the internal circuit 12 by absorbing the energy of external surges. Also, as shown in Figure B, capacitor 1
4 may be replaced by a Zener diode 15 having large power characteristics. However, such a protection circuit has drawbacks such as deterioration of the frequency response of the integrated circuit 11, increase in chip area, and high cost of the large capacitance capacitor 14 when a large capacitance capacitor 14 is used. Further, when the Zener diode 15 is used, the amplitude of the input signal to the integrated circuit 11 is limited, and there is a drawback that a sufficient dynamic range cannot be obtained.
このような欠点を解決する手段として、第2図
A(平面図で必要な部分のみ示す)に示すよう
に、集積回路11の基板(例えばセラミツク)2
1上に外部端子(図示せず)と接続される銀・パ
ラジウム等の例えばパツド部22を設け、このパ
ツド部22と所定の間隔、すなわちギヤツプ23
をもつて銀・パラジウム等の金属膜24を設け
る。この金属膜23は、接地電位を得るように、
例えば回路の接地電源線(図示せず)に接続す
る。このような保護回路では、パツド部22に外
部サージ電圧が印加された場合、ギヤツプ23の
部分に例えば空気の絶縁破壊が生じて外部サージ
が接地電位の金属膜24へ放電することによつ
て、パツド部22に接続されている回路素子を保
護することができる。また、上記のように集積回
路11の周波数応答および振幅特性などが悪化す
ることもない。 As a means to solve such drawbacks, as shown in FIG. 2A (only necessary parts are shown in the plan view), a substrate (for example, ceramic) 2
A pad part 22 made of silver, palladium, etc., which is connected to an external terminal (not shown), is provided on the pad part 1, and a gap 23 is formed between the pad part 22 and a predetermined distance, that is, a gap 23.
A metal film 24 of silver, palladium, etc. is provided using the following steps. This metal film 23 is arranged so as to obtain a ground potential.
For example, it is connected to a circuit ground power line (not shown). In such a protection circuit, when an external surge voltage is applied to the pad portion 22, dielectric breakdown of air occurs at the gap 23, and the external surge is discharged to the metal film 24 at ground potential. The circuit elements connected to the pad portion 22 can be protected. Furthermore, the frequency response and amplitude characteristics of the integrated circuit 11 do not deteriorate as described above.
ところで、上記のような厚膜集積回路は耐湿性
対策等のために、第2図B(断面図)に示すよう
に、基板21全体をシリコンゲル等の樹脂25で
被覆することが多い。このような樹脂25は、通
常空気と比較して絶縁耐圧が非常に大きい。した
がつて、外部端子13から外部サージ電圧がパツ
ド部22に印加された場合、ギヤツプ23の部分
に存在する樹脂25に絶縁破壊が生ずることな
く、外部サージが接地電位の金属膜24に放電さ
れない状態があるなど、保護動作が不安定になる
欠点がある。 Incidentally, in the thick film integrated circuit as described above, the entire substrate 21 is often coated with a resin 25 such as silicone gel, as shown in FIG. 2B (cross-sectional view), for moisture resistance and the like. Such resin 25 has a much higher dielectric strength voltage than normal air. Therefore, when an external surge voltage is applied to the pad portion 22 from the external terminal 13, no dielectric breakdown occurs in the resin 25 existing at the gap 23, and the external surge is not discharged to the metal film 24 at the ground potential. There is a drawback that the protection operation becomes unstable due to the presence of certain conditions.
この発明は、上記の事情を鑑みてなされたもの
で、外部端子に印加される外部サージ電圧に対し
て、回路素子の保護を確実に行なうことができ、
回路動作の安定な高い信頼性を有する集積回路を
提供することを目的とする。 This invention was made in view of the above circumstances, and can reliably protect circuit elements against external surge voltages applied to external terminals.
An object of the present invention is to provide an integrated circuit with stable circuit operation and high reliability.
以下図面を参照してこの発明の一実施例につい
て説明する。第3図A,Bは、この発明の一実施
例に係る集積回路11の構成(必要な部分のみ示
す)を示すもので、図A(平面図)に示すように
セラミツク等の基板21上に回路を構成する回路
素子(図示せず)と接続される銀・パラジウム等
の例えばパツド部22が設けられる。このパツド
部22と所定の間隔、すなわちギヤツプ23をも
つて銀・パラジウム等の金属膜24が設けられ、
この金属膜24は接地電位を得るように例えば集
積回路の接地電源線(図示せず)に接続される。
そして、このギヤツプ23の部分にパツド部22
と金属膜24が接続する如く十分絶縁耐圧の低い
例えばハンダレジスト等の絶縁膜31が設けられ
る。さらに、このような基板21全体に対して、
図B(断面図)に示すように耐湿性対策等のため
に絶縁耐圧の高いシリコンゲル等の樹脂25によ
つて被覆される。 An embodiment of the present invention will be described below with reference to the drawings. 3A and 3B show the configuration (only necessary parts are shown) of an integrated circuit 11 according to an embodiment of the present invention, and as shown in FIG. A pad portion 22 made of, for example, silver or palladium is provided to be connected to a circuit element (not shown) constituting the circuit. A metal film 24 of silver, palladium, etc. is provided at a predetermined distance from this pad portion 22, that is, with a gap 23.
This metal film 24 is connected to, for example, a ground power line (not shown) of the integrated circuit so as to obtain a ground potential.
Then, a pad part 22 is attached to this gap 23.
An insulating film 31, such as a solder resist, having a sufficiently low dielectric strength voltage is provided so that the metal film 24 and the metal film 24 are connected to each other. Furthermore, for the entire substrate 21,
As shown in FIG. B (cross-sectional view), it is coated with a resin 25 such as silicone gel having a high dielectric strength for moisture resistance and the like.
このように構成される集積回路において、第3
図Bに示すように、パツド部22に接続される外
部端子13から外部サージ電圧が印加された場
合、絶縁膜31は例えば樹脂25に比較して十分
絶縁耐圧が低いため、外部サージの過電圧等によ
つて絶縁破壊が比較的容易に発生する。したがつ
て、パツド部22と接地電位の金属膜24は導通
状態となり、外部サージの大部分は、パツド部2
2から金属膜24へ放電されることになり、外部
サージ電圧から回路素子を保護することができ
る。 In the integrated circuit configured in this way, the third
As shown in Figure B, when an external surge voltage is applied from the external terminal 13 connected to the pad portion 22, the insulating film 31 has a sufficiently lower dielectric strength voltage than, for example, the resin 25, so the overvoltage due to the external surge etc. dielectric breakdown occurs relatively easily. Therefore, the pad portion 22 and the metal film 24 at the ground potential are in a conductive state, and most of the external surge is caused by the pad portion 2.
2 to the metal film 24, the circuit elements can be protected from external surge voltage.
第4図A,Bはこの発明の他の実施例を示すも
ので、上記実施例においてパツド部22に印加さ
れた外部サージの放電のバイパスである絶縁膜3
1の代りに例えば100KΩ以上の高抵抗で金属酸
化物等の膜(以下高抵抗膜と称する)41を設け
た集積回路である。この場合でも、上記実施例と
ほぼ同様の効果を有するが、絶縁膜31に対して
高抵抗膜41の方がバイパス効果、すなわち外部
サージの放電が発生しやすいため、比較的確実な
保護動作を行なうことができる。但し、この場合
には、外部サージ以外の回路動作に必要な入力信
号等の一部がパツド部22から接地電位の金属膜
24へ流れることになるため、集積回路の回路動
作上さしつかえない部分に上記高抵抗膜41を設
けることが望ましい。なお、他の構成および動作
は上記実施例と同様であるため説明は省略する。 4A and 4B show another embodiment of the present invention, in which an insulating film 3 serves as a bypass for discharge of an external surge applied to the pad portion 22 in the above embodiment.
1 is replaced by a film 41 made of metal oxide or the like (hereinafter referred to as a high resistance film) having a high resistance of, for example, 100 KΩ or more. In this case as well, the effect is almost the same as in the above embodiment, but the high resistance film 41 is more likely to have a bypass effect, that is, to cause external surge discharge than the insulating film 31, so that a relatively reliable protective operation can be achieved. can be done. However, in this case, a part of the input signals necessary for circuit operation other than external surges will flow from the pad section 22 to the metal film 24 at ground potential, so that the input signals, etc. that are necessary for circuit operation other than external surges will flow from the pad section 22 to the metal film 24 at the ground potential. It is desirable to provide the high resistance film 41. Note that the other configurations and operations are the same as those in the above embodiment, so explanations will be omitted.
第5図は、この発明のさらに他の実施例を示す
もので、パツド部22および接地電位の金属膜2
4a〜24c間に複数のギヤツプ23a〜23c
が設けられ、この各ギヤツプ23a,23bの部
分に絶縁耐圧の低い絶縁膜31および高抵抗膜4
1がそれぞれ設けられ、パツド部22と金属膜2
4a,24bが接続される。さらに、パツド部2
2と金属膜24cのギヤツプ23cには、通常基
板21を被覆する際のシリコンゲル等の樹脂が設
けられる。 FIG. 5 shows still another embodiment of the present invention, in which a pad portion 22 and a metal film 2 at ground potential are shown.
Multiple gaps 23a-23c between 4a-24c
An insulating film 31 with a low dielectric strength and a high resistance film 4 are provided at each gap 23a, 23b.
1 are provided respectively, and a pad portion 22 and a metal film 2 are provided.
4a and 24b are connected. Furthermore, the pad part 2
A resin such as silicon gel, which is normally used to cover the substrate 21, is provided in the gap 23c between the metal film 24c and the metal film 24c.
このような構成の集積回路では、パツド部22
に印加される外部サージの放電のバイパスが複数
であり、また各バイパスが異なる材質である絶縁
膜31および高抵抗膜41からなるため、過電圧
等が広範囲の外部サージに対してより確実に保護
動作が行なわれる効果がある。なお、他の構成お
よび動作は上記実施例と同様であるため説明は省
略する。 In an integrated circuit having such a configuration, the pad portion 22
Since there are multiple bypasses for discharging external surges applied to the circuit, and each bypass is made of an insulating film 31 and a high-resistance film 41 made of different materials, protection can be performed more reliably against external surges over a wide range of overvoltage, etc. The effect is that Note that the other configurations and operations are the same as those in the above embodiment, so explanations will be omitted.
なお、上記実施例において接地電位の金属膜2
4と絶縁膜31または高抵抗膜41を介して接続
される部分は、パツド部22に限ることなく回路
素子および外部端子と接続されている金属膜であ
ればよい。また、高抵抗膜41は、金属酸化物に
限ることなく半導体等の他のものでもよい。 In addition, in the above embodiment, the metal film 2 at the ground potential
4 via the insulating film 31 or the high resistance film 41 is not limited to the pad portion 22, but may be any metal film connected to a circuit element and an external terminal. Further, the high resistance film 41 is not limited to metal oxide, and may be made of other materials such as a semiconductor.
以上詳述したようにこの発明によれば、集積回
路の外部端子に印加される外部サージ電圧に対し
て、予め設けた接地電位の金属膜に外部サージを
確実に放電して、回路素子の保護を確実に行なう
ことができる。しかも、保護回路にはコンデンサ
およびツエナーダイオード等は使用しないため、
集積回路の周波数応答および振幅特性等には悪影
響が及ぶことがなく、回路動作を常に安定に保持
することができる。 As described in detail above, according to the present invention, the external surge voltage applied to the external terminals of the integrated circuit is reliably discharged to the metal film at ground potential provided in advance, thereby protecting the circuit elements. can be done reliably. Moreover, since capacitors and Zener diodes are not used in the protection circuit,
The frequency response, amplitude characteristics, etc. of the integrated circuit are not adversely affected, and the circuit operation can always be kept stable.
第1図A,Bは、従来の集積回路の構成図、第
2図A,Bは従来の集積回路の保護回路部を示す
図で、同図Aは平面図、同図Bは断面図、第3図
A,Bはこの発明の一実施例に係る集積回路の保
護回路部を示す図で、同図Aは平面図、同図Bは
断面図、第4図A,Bはこの発明の他の実施例に
係る集積回路の保護回路部を示す図で、同図Aは
平面図、同図Bは断面図、第5図はこの発明のさ
らに他の実施例に係る集積回路の保護回路部を示
す平面図である。
11…集積回路、13…外部端子、14…コン
デンサ、15…ツエナーダイオード、21…基
板、22…パツド部、23,23a〜23c…ギ
ヤツプ、24,24a〜24c…金属膜、25…
樹脂、31…絶縁膜、41…高抵抗膜。
1A and 1B are block diagrams of a conventional integrated circuit, and FIGS. 2A and 2B are diagrams showing a protection circuit section of a conventional integrated circuit, in which figure A is a plan view, figure B is a cross-sectional view, 3A and 3B are diagrams showing a protection circuit section of an integrated circuit according to an embodiment of the present invention, in which FIG. 3A is a plan view, FIG. 3B is a sectional view, and FIGS. FIG. 5 is a diagram showing a protection circuit section of an integrated circuit according to another embodiment, where A is a plan view, B is a sectional view, and FIG. 5 is a protection circuit of an integrated circuit according to still another embodiment of the present invention. FIG. DESCRIPTION OF SYMBOLS 11... Integrated circuit, 13... External terminal, 14... Capacitor, 15... Zener diode, 21... Substrate, 22... Pad part, 23, 23a-23c... Gap, 24, 24a-24c... Metal film, 25...
Resin, 31... Insulating film, 41... High resistance film.
Claims (1)
の回路の一部で外部配線と接続される第1の金属
膜と、この第1の金属膜と所定の間隔をもつて上
記基板上に設けられる接地電位の第2の金属膜
と、上記回路の保護用で上記基板上に設けられる
樹脂と、上記基板上で上記第1および第2の金属
膜間に設けられ、上記第1および第2の金属膜間
を接続する少なくとも上記樹脂よりも絶縁耐圧の
小さい絶縁膜とを具備したことを特徴とする集積
回路。 2 所定の回路が構成される基板と、この基板上
の回路の一部で外部配線と接続される第1の金属
膜と、この第1の金属膜と所定の間隔をもつて上
記基板上に設けられる接地電位の第2の金属膜
と、上記回路の保護用で上記基板上に設けられる
樹脂と、上記基板上で上記第1および第2の金属
膜間に設けられ、上記第1および第2の金属膜間
を接続する高抵抗の膜とを具備したことを特徴と
する集積回路。[Claims] 1. A substrate on which a predetermined circuit is configured, a first metal film connected to external wiring as part of the circuit on this substrate, and a predetermined interval between the first metal film and the first metal film. a second metal film with a ground potential provided on the substrate; a resin provided on the substrate for protection of the circuit; and a resin provided between the first and second metal films on the substrate. and an insulating film having a dielectric strength lower than at least the resin, which connects the first and second metal films. 2. A substrate on which a predetermined circuit is configured, a first metal film connected to external wiring as part of the circuit on this substrate, and a first metal film on the substrate with a predetermined distance from the first metal film. a second metal film provided at a ground potential, a resin provided on the substrate for protection of the circuit, and a resin provided between the first and second metal films on the substrate, and An integrated circuit comprising: a high resistance film connecting two metal films.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15129281A JPS5852866A (en) | 1981-09-24 | 1981-09-24 | Integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15129281A JPS5852866A (en) | 1981-09-24 | 1981-09-24 | Integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5852866A JPS5852866A (en) | 1983-03-29 |
JPS6139742B2 true JPS6139742B2 (en) | 1986-09-05 |
Family
ID=15515488
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15129281A Granted JPS5852866A (en) | 1981-09-24 | 1981-09-24 | Integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5852866A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6392653U (en) * | 1986-11-30 | 1988-06-15 | ||
JP2007251216A (en) * | 2007-07-05 | 2007-09-27 | Denso Corp | Wiring board |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6211554B1 (en) * | 1998-12-08 | 2001-04-03 | Littelfuse, Inc. | Protection of an integrated circuit with voltage variable materials |
-
1981
- 1981-09-24 JP JP15129281A patent/JPS5852866A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6392653U (en) * | 1986-11-30 | 1988-06-15 | ||
JP2007251216A (en) * | 2007-07-05 | 2007-09-27 | Denso Corp | Wiring board |
Also Published As
Publication number | Publication date |
---|---|
JPS5852866A (en) | 1983-03-29 |
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