JPS6138503B2 - - Google Patents
Info
- Publication number
- JPS6138503B2 JPS6138503B2 JP56126579A JP12657981A JPS6138503B2 JP S6138503 B2 JPS6138503 B2 JP S6138503B2 JP 56126579 A JP56126579 A JP 56126579A JP 12657981 A JP12657981 A JP 12657981A JP S6138503 B2 JPS6138503 B2 JP S6138503B2
- Authority
- JP
- Japan
- Prior art keywords
- address
- buffer
- data
- memory
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
- G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56126579A JPS5829186A (ja) | 1981-08-14 | 1981-08-14 | 情報処理装置 |
US06/294,121 US4467414A (en) | 1980-08-22 | 1981-08-19 | Cashe memory arrangement comprising a cashe buffer in combination with a pair of cache memories |
FR8116082A FR2489021B1 (fr) | 1980-08-22 | 1981-08-21 | Agencement d'antememoires comprenant une antememoire tampon en combinaison avec une paire d'antememoires |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56126579A JPS5829186A (ja) | 1981-08-14 | 1981-08-14 | 情報処理装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5829186A JPS5829186A (ja) | 1983-02-21 |
JPS6138503B2 true JPS6138503B2 (enrdf_load_stackoverflow) | 1986-08-29 |
Family
ID=14938659
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56126579A Granted JPS5829186A (ja) | 1980-08-22 | 1981-08-14 | 情報処理装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5829186A (enrdf_load_stackoverflow) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60181942A (ja) * | 1984-02-29 | 1985-09-17 | Fujitsu Ltd | メモリ制御装置 |
US20070288725A1 (en) * | 2006-06-07 | 2007-12-13 | Luick David A | A Fast and Inexpensive Store-Load Conflict Scheduling and Forwarding Mechanism |
-
1981
- 1981-08-14 JP JP56126579A patent/JPS5829186A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5829186A (ja) | 1983-02-21 |
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