JPS6138503B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus that uses a buffer memory such as a cache memory in place of a main memory to exchange information with an arithmetic processing unit at high speed.

In general, in this type of information processing device, the buffer memory is accessed when reading and writing data, such as reading instructions from an arithmetic processing unit and reading and writing operands. Buffer memory is faster than large-capacity main memory, so
An information processing apparatus having a buffer memory can significantly improve throughput compared to an information processing apparatus having no buffer memory that directly accesses the main memory.

Here, in order to point out the problems of an information processing device having a buffer memory, its operation will be briefly described. First, when a read request is received from the arithmetic processing section, the buffer memory is accessed and if the buffer memory exists, data is directly taken out. Therefore, the slow main memory is activated only when there is no desired data in the buffer memory and one block of data containing the desired data is to be transferred from the main memory to the buffer memory.

In response to a write request from the arithmetic processing unit, the buffer memory is a copy of the main memory, and in order to avoid discrepancies in the data content between the buffer memory and the main memory, the main The same data must also be written to the storage device. That is, in a write operation, it is necessary to start up the slow main storage device.

To avoid this, when a write request is received from the arithmetic processing unit, the write operation is limited to the buffer memory for the time being, and replacement is performed at an appropriate time, for example, when one block of the buffer memory needs to be replaced. There is also a method in which if a write operation has been performed on the target block, that block is written to the main memory. This method is called the store-swap method, but in systems where multiple information processing devices share the memory area of the main memory, it is difficult to synchronize the data in the main memory and buffer memory. Specifically, the information processing device stores 1
When a block read request is issued, it is necessary to always check the buffer memories of other information processing devices to see if the latest data is present. Therefore, the currently implemented writing method is called a store-through method, and data is synchronized between the buffer memory and the main storage by writing to the buffer memory and the main storage at the same time.

A write operation to a buffer memory usually requires more time than a read operation due to its control and the characteristics of the memory element used. In other words, a write operation has a longer cycle time than a read operation. In addition, in the store-through method, it is necessary to write to the buffer memory and the main memory at the same time, and if the main memory is processing a request from another information processing device and cannot accept the write request, the write request is made. The processing of the information processing device that issued the error will have to be temporarily suspended.

In order to solve the above problems, it has been proposed to provide a store buffer within the information processing device to hold address information and data accompanying write requests from the arithmetic processing unit (Japanese Patent Application No. 55-115533).
(see specification). In the information processing device according to this proposal, once address information and data associated with a write request are stored in the store buffer, the operation for the write request is temporarily terminated, and the state is such that the next request can be accepted from the arithmetic processing unit. becomes. The store buffer finds free time in buffer memory and main memory to perform write operations. The store buffer is treated as part of the buffer memory, and is naturally referenced in response to a read request from the arithmetic processing unit. If desired data exists in the store buffer in response to a read request, that data must be transferred to the arithmetic processing section.

On the other hand, in this type of information processing apparatus, a virtual storage method is often adopted. In this case, the program is arranged in a logical space, and a read/write request from the arithmetic processing unit to the buffer memory is accompanied by a logical address. Furthermore, since the buffer memory and the main memory are accessed using real addresses, an address conversion mechanism for converting logical addresses into real addresses is usually provided in the information processing device.

In this way, it is commonly used. When the address conversion mechanism is applied to an information processing device having a store buffer, the logical address accompanying a read or write request from the arithmetic processing unit is converted into a real address by the address conversion mechanism and then given to the buffer memory and store buffer. Become.

Here, the case where a read request is given will be explained in more detail. In this case, the real address from the address translation mechanism is provided to the buffer memory as well as the store buffer. The buffer memory is referenced by this real address, and if the desired data exists in the buffer memory, the reply data will be transferred from the buffer memory to the arithmetic processing section. On the other hand, if data related to the real address also exists in the store buffer, it is necessary to suppress the reply sent from the buffer memory to the arithmetic processing section and instead send the write data existing in the store buffer to the arithmetic processing section. This is because the data in the buffer memory has not been rewritten by the data in the corresponding store buffer memory.

In a high-performance information processing device, the clock that operates the hardware is fast, and the requirements for the delay time of the logic circuit are strict. Therefore, as described above, after converting the logical address required for reading from the arithmetic processing unit into a real address, referencing and indexing the store buffer to detect the presence or absence of desired data, the arithmetic processing unit reads the data from the buffer memory. If you suppress replies sent to , you will no longer be able to suppress replies.

An object of the present invention is to suppress read data from the buffer memory before transferring it in an information processing device having a store buffer in addition to a buffer memory, when data corresponding to a logical address accompanying a read request exists in both the buffer memory and the store buffer. The objective is to provide an information processing device that can.

According to the present invention, access is performed using a logical address,
The buffer memory has an address conversion mechanism that converts a logical address into a real address, and includes at least an address array that holds information including address information regarding a block of the buffer memory, and a data array that is the data storage thereof. The information processing device includes a store buffer that holds write requests in response to write requests, and the store buffer stores all or part of the logical address accompanying the write request as address information and the logical address obtained by address conversion. When a read request occurs, it has means for determining whether data exists in the buffer memory and store buffer, and in particular, for the store buffer index, it stores the logical address and store buffer associated with the read request. The present invention provides an information processing apparatus having means for determining whether or not desired data exists in the store buffer by comparing it with the logical address associated with the write request stored in the store buffer.

The present invention will be described below with reference to the drawings.

Referring to FIG. 1, an information processing device 1 to which the present invention is applied is connected to a main storage device 2 via an interface 3. This information processing device 1 includes an arithmetic processing section 11, and the arithmetic processing section 11 sends out read and write requests accompanied by logical addresses. Write data associated with a write request is provided from the arithmetic processing section 11 to the store buffer 13. The logical address is converted into a real address by an address conversion mechanism 12, which will be described later, and is transferred to a buffer memory 14.
access. The logical address is also supplied to the store buffer 13, and when a read request is made, the desired data is transferred to the store buffer 13 by comparing the logical address associated with the write request stored in the store buffer 13 with the logical address associated with the read request. Investigate whether it exists or not.

As is clear from the above, the information processing device 1 according to the present invention includes, in addition to the buffer memory 14 such as a cache memory, the store buffer 1 that stores write addresses and data accompanying write requests.
3, it is possible to process write requests without depending on the state of the main storage device 2. In this way, store buffer 1
3, when making a read request, as mentioned above,
It must be taken into consideration that this store buffer 13 is also subject to indexing.

Referring to FIG. 2, in an information processing apparatus according to an embodiment of the present invention, parts corresponding to those in FIG. 1 are designated with the same reference numerals. In FIG. 2, the store buffer 13 is divided into an address section 13-1 and a write data section 13-2, and when a read request is made, an address associated with the read request is stored in the store buffer 13. In order to determine whether or not the address section 13-1 is the same, a determination circuit 40 comprising a comparison circuit 43 and a store buffer hit register (hereinafter abbreviated as SHR) 35 is connected to the address section 13-1. Furthermore, the store buffer address section 13-1 is a logical address section (hereinafter referred to as
(abbreviated as STB-LA) 25 and the real address part (hereinafter referred to as
STB-RA (abbreviated as STB-RA) 26.

First, a read request and a write request from the arithmetic processing unit 11 are determined by a circuit (not shown), and the logical address associated with each request is set in the logical address register (hereinafter abbreviated as LAR) 31 of the address translation mechanism 12. . The address translation mechanism 12 has a translation function as an address translation buffer.
A lookaside buffer (hereinafter referred to as TLB) is provided, and this TLB includes a TLBKEY section 21 that is a directory of registered entries, a data section 22 that stores real addresses, a comparison circuit 41, and an AND gate 47. have.
The TLB is indexed by the logical address set in the LAR 31, and it is detected whether a correspondence from a logical address to a real address is registered in the TLB. It is assumed that the TLB index is performed using the set association method.

If the address translation pair is registered in the TLB,
This means that the real page address is registered in the TLB data section 22. In this case, the first switching circuit 44 is applied via an AND gate 47.
The output of the TLB data section 22 is selected and sent to the physical address register (hereinafter abbreviated as PAR) 32. On the other hand, the intra-page address in the LAR 31 is selected by the second switching circuit 45 and sent to the PAR 32, and the PAR 32 obtains the real address by concatenating the real page address with the intra-page address. If no translation pair is registered in the TLB, perform address translation and send the result.
The information is registered in the TLB, but since this method is well known, the explanation will be omitted here.

Next, the write operation will be explained. in this case,
According to the above format, the output of the TLB data section 22 and the in-page address from the LAR 31 are STB-
It is stored in RA26 as a real address. At the same timing, the logical address set in LAR31 is stored in STB-LA25. In this embodiment, address section 1 of store buffer 13
Each memory used as the write data section 3-1 and the write data section 13-2 is of a first-in first-out type.

When both the logical address and the real address are stored in the address section 13-1 of the store buffer 13,
The information processing device 1 temporarily ends the write operation and becomes ready to accept the next request from the arithmetic processing unit 11. Note that in pipeline control, after the logical address and real address are stored in the address section 13-1, the write data is stored in the write data section 13-2.

In the case of a read operation, the real address is obtained in the same way as described above, and in parallel with this, the address array (hereinafter abbreviated as AA) 23 is indexed using the set association method, and the buffer memory 14 is indexed.
The comparison circuit 42 is used to check whether one block containing the desired data is registered in the address array hit register (hereinafter referred to as AHR).
) is set to 34. Normally, when registered in buffer memory 14, AHR34
Sends a FOUND BLOCK (hereinafter abbreviated as FDB) signal, and if not registered, NOT FOUND
Sends a BLOCK (hereinafter abbreviated as NFB) signal.

On the other hand, during this read operation, the logical address set in the LAR 31 is input to the comparison circuit 43 of the address match detection circuit 40 which is also connected to the STB-LA 25, and the desired read data is transferred to the store buffer 1.
It is detected whether or not it is stored in SHR35, and the result is set in SHR35. In this embodiment, it is assumed that the store buffer 13 is indexed using a full association method.

The data array (hereinafter abbreviated as DA) which is the data storage of the buffer memory 14 is determined by the real address set in PAR32 using TLB.
24 are accessed. In this case, the SHR 35 is checked and the desired read data is stored in the store buffer 13.
If it does not exist, check AHR34. At this time, if the FDB signal is sent out, the data read from the DA24 will be sent to the AND gate 48 and the third
is selected via the switching circuit 46 and is the request source as read data. The data is sent to the arithmetic processing unit 11. On the other hand, if the NFB signal is being sent from the AHR 34 and the desired data does not exist in the store buffer 13, the address conversion mechanism 12 sets a read request to the PAR 32 to read one block containing the desired data from the main storage device. It is sent along with the actual address that is being sent. Also, SHR3
5, if it is found that the desired data exists in the store buffer 13, the third switching circuit 46 selects the output from the write data section (STB-WD) 27 and sends it to the request source as the read data. It is sent to the arithmetic processing section 11.

As mentioned above, processing for write requests from the arithmetic processing unit 11 is performed by the store buffer address unit 13-
The process was temporarily terminated when the logical address and real address were stored in 1. However, the write data must ultimately be stored in the main memory and buffer memory 14. In this embodiment, when there is no read request from the arithmetic processing unit 11, the main storage device is ready to accept requests, and write data is prepared in the STB-WD 13-2, the data is stored in the store buffer 13. The real address and write data associated with the stored write request are transferred to buffer memory 1.
4 and sent to main storage. Specifically, the real address of the STB-RA 26 is given to the AA 23 through an output address register (hereinafter abbreviated as SAR) 33 and a second switching circuit 45. The index by the STB-RA 26 of the AA 23 is read by the first and second switching circuits 44 and 4 on the condition that no read request is issued from the arithmetic processing unit 11.
This is done by switching 5.
The index result of AA23 is given to AHR34, and the real address from SAR23 is set to PAR32.

When AHR34 is sending the FDB signal, the write data of STW-WD13-2 is sent to DA24.
In addition to being written to main memory, PAR
The real address set to 32 and STB-
The write data of WD 13-2 is sent together with the write request. When the AHR 34 is sending out the NFB signal, no write operation is performed on the DA 24, and only a write operation is performed on the main storage device.

As described above, processing for write requests from the store buffer 13 is performed without using the TLB. Therefore, during this processing period, it is possible to accept write requests from the arithmetic processing unit 11. In other words, it is possible to simultaneously flush out write requests from the store buffer and store write requests in the store buffer.

Referring to FIG. 3, the information processing apparatus according to another embodiment of the present invention has a first
and second buffer memories 14-1 and 14-
2. It is provided with first and second memory control circuits 15-1 and 15-2 that control each buffer memory. Here, each memory control circuit 15-1, 1
5-2 are the first to third switching circuits 44, 45, 46, SAR 33, and PAR 3 shown in FIG.
This corresponds to the interface shown between each circuit of the second class. Further, the store buffer 13 stores the logical address and real address associated with the write request given from the arithmetic processing unit 11 to the address translation mechanism 12 via the line 16 to the first and second address buffers 13-1 and 13-2. At the same time, the write data accompanying the write request is received via the line 17 to the first and second data buffer circuits 13-3 and 1.
Receive it 3-4.

In this embodiment, the operand read request and operand read address are also provided to the address translation mechanism 12 via line 16, and the instruction read request and instruction read address are provided to the address translation mechanism 12 via line 18.
It is assumed that the signal is supplied to the second memory control circuit 15-2 through the memory control circuit 15-2. Note that an address conversion mechanism is required to convert the instruction read address from a logical address to a real address, but its illustration is omitted here. In any case, the contents of the first and second address buffer circuits 13-1 and 13-2 are transmitted to the first and second address match detection circuits 40-1 and 40-2 when an operand and instruction read request is made. are compared with the logical addresses given as they are, and if a match is detected, the first and second match detection signals are output.
CD ₁ and CD ₂ are respectively sent out.

Upon receiving the first and second coincidence detection signals CD ₁ and CD ₂ , the first and second memory control circuits 15-1
and 15-2 process buffer store requests given from the first and second address buffer circuits 13-1 and 13-2 with priority, respectively, before operand and instruction read requests from the arithmetic processing unit 11. For example, in a state where the first coincidence detection signal CD ₁ is being sent out, the first memory control circuit 1
5-1 provides the real address accompanying the buffer store request from the first address buffer circuit 13-1 to the first buffer memory 14-1 together with the data from the first data buffer circuit 13-3, and If there is no corresponding address in the buffer memory 14-1, the write request, address and data are sent to the main memory. On the other hand, in a state where the first coincidence detection signal CD ₁ is not sent out, the converted real address associated with the read request is sent to the first buffer memory 14-1 via the first memory control circuit 15-1. and sends it to the main memory, and reads from the address specified by the real address. Note that when the second coincidence detection signal CD ₂ is not sent out, the second memory control circuit 15-2 performs the same operation as the first memory control circuit 15-1 described above.

In the embodiment described above, operand and instruction read requests can be made independently of each other, and processing delays due to conflicts between write requests and read requests can also be prevented.

As mentioned above, in the present invention, the store buffer
Since AA is indexed in parallel and the AA index result is set in register AHR, there is an advantage of indexing the store buffer using logical addresses. In other words, the index result of the store buffer is stored in a register.
Since it is set in SHR and the presence or absence of data in the store buffer and buffer memory can be determined directly from the output of the register (consisting of flips),
This is very advantageous for the hardware regarding the delay time of the logic elements, and therefore control becomes easier.

By the way, in the virtual memory system, the same real address may be assigned to different logical addresses. In this case, a condition is required that different logical addresses in one logical space must not point to the same real address at the same time.

When switching the logical space and page-in/page-out of the memory area of the main storage device, it is necessary to synchronize the address translation buffer, and
You must ensure that no write requests exist in the store buffer. If write requests are held in the store buffer, all write requests are purged from the store buffer, and after the write process is completed in the information processing device, the logical space is switched and the main memory page is It is possible to page in and page out. Such processing is commonly performed and is not a limitation for implementing the present invention.

As described above, by indexing the store buffer using logical addresses, the store buffer index result can be used as register output.
Control compatible with high-speed clocks becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an information processing apparatus according to an embodiment of the present invention, FIG. 2 is a block diagram for more specifically explaining the information processing apparatus shown in FIG. 1, and FIG. FIG. 3 is a block diagram showing an information processing device according to another embodiment of the present invention. 1... Information processing device, 2... Main storage device, 3...
...Interface, 11... Arithmetic processing unit, 12...
...Address translation mechanism, 13...Store buffer,
14...Batsufua Memory, 21...TLBKEY
Part, 22...TLB data part, 23...Address array Abbreviation AA, 24...Data array Abbreviation
DA, 13-1... address part of store buffer, 25... logical address part of store buffer
Abbreviation STB-LA, 26...Real address part of store buffer Abbreviation STB-RA, 13-2...Write data part of store buffer Abbreviation STB-WD, 31
...Logical address register Abbreviation: LAR, 32...
...Physical address register abbreviation PAR, 33...
Store buffer output address register Abbreviation
SAR, 34... Address array hit register Abbreviation AHR, 35... Store buffer hit register Abbreviation SHR, 41... Comparison circuit, 42...
...Comparison circuit, 43...Comparison circuit, 44...Switching circuit 1, 45...Switching circuit 2, 46...Switching circuit 3, 47...AND gate, 48...AND gate.

Claims (1)

[Claims] 1. In an information processing device that is equipped with a buffer memory, the buffer memory has an address array that holds address information regarding blocks of the buffer memory, and a data array that is data storage for the address array. an address translation mechanism that receives address information associated with a request in the form of a logical address and converts the logical address into a real address; and in response to the write request, at least a portion of the logical address associated with the write request. , and a store buffer that holds at least a real address obtained by converting the logical address by the address translation mechanism, and when the read request occurs, the logical address associated with the read request and the store buffer hold means for determining whether or not data related to the address to be read exists in the store buffer by comparing the data with the logical address that has been read, and when the read request occurs, the buffer memory An information processing device characterized in that the information processing device is accessed using a real address that has been converted into an address.