JPS6137780B2 - - Google Patents

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Publication number
JPS6137780B2
JPS6137780B2 JP11456580A JP11456580A JPS6137780B2 JP S6137780 B2 JPS6137780 B2 JP S6137780B2 JP 11456580 A JP11456580 A JP 11456580A JP 11456580 A JP11456580 A JP 11456580A JP S6137780 B2 JPS6137780 B2 JP S6137780B2
Authority
JP
Japan
Prior art keywords
film
semiconductor
psg
thermal oxide
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP11456580A
Other languages
Japanese (ja)
Other versions
JPS5737858A (en
Inventor
Juro Yasui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP11456580A priority Critical patent/JPS5737858A/en
Publication of JPS5737858A publication Critical patent/JPS5737858A/en
Publication of JPS6137780B2 publication Critical patent/JPS6137780B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 本発明は多層配線構造を有する半導体装置にお
ける配線間の絶縁膜を形成する半導体装置の製造
方法に関するものであり、特に二配線間の絶縁膜
の形成工程を簡単化することを目的とするもので
ある。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device that forms an insulating film between wirings in a semiconductor device having a multilayer wiring structure, and particularly to a method for simplifying the process of forming an insulating film between two wirings. The purpose is to

多層配線構造を有する半導体装置、例えばSiゲ
ートMOSLSIにおいては、配線間の絶縁膜として
気相化学蒸着(CVD)法により形成したSiO2
(以下CVDSiO2膜とよぶ)、あるいはリンを含ん
だリンケイ酸ガラス膜(以下PSG膜とよぶ)、あ
るいはCVDSiO2膜とPSG膜との積層膜が用いら
れる。これらのCVDSiO2膜やPSG膜は、例えば
450℃におけるSiH4とO2の反応により、あるいは
SiH4,O2,PH3の反応により形成される。
In semiconductor devices with a multilayer wiring structure, such as Si gate MOSLSI, an SiO 2 film (hereinafter referred to as CVDSiO 2 film) formed by vapor phase chemical vapor deposition (CVD) or a phosphorus-containing insulating film is used as an insulating film between wirings. An acid glass film (hereinafter referred to as PSG film) or a laminated film of a CVDSiO 2 film and a PSG film is used. These CVDSiO 2 films and PSG films are, for example,
By the reaction of SiH 4 and O 2 at 450 °C or
Formed by the reaction of SiH 4 , O 2 , and PH 3 .

特にPSG膜は外部から半導体基板表面、すなわ
ち半導体装置のFET等が形成されている能動領
域にまでアルカリイオン等が侵入するのを阻止
し、しきい電圧等電気的特性を安定化させる目的
で用いられる。
In particular, PSG films are used to prevent alkali ions from entering from the outside into the surface of a semiconductor substrate, that is, into the active region where FETs, etc. of semiconductor devices are formed, and to stabilize electrical characteristics such as threshold voltage. It will be done.

さらにPSG膜は高温の熱処理を施すと流動して
側面傾斜が急な下部配線の端部をもなだらかに覆
い、又基板表面の凹部と凸部の高低差を減少させ
ることができる。従つて流動させたPSG膜上に蒸
着法等で形成したAl膜は下部配線の側面上でも
十分な厚さを有し、写真蝕刻法で上部配線に成形
しても段切れを生ずることがない。又、下部配線
側面が急峻であつてもそれをなだらかに覆うPSG
膜上のAl膜は、ひさしを生じることがないため
写真蝕刻時にポジ型のホトレジスト膜を形成し、
紫外線を照射する際に露光量が不足して下部配線
側面にホトレジストが残ることがない。そのため
Al膜を蝕刻するのに横方向には殆んど蝕刻され
ることがなく、ホトレジストパターンに忠実に蝕
刻できる反応性スパツタリング法を用いて下部配
線側面のAl膜をも完全に蝕刻できるため、この
部分で短絡のない微細な上部電極を形成すること
ができる。
Furthermore, when subjected to high-temperature heat treatment, the PSG film flows and smoothly covers the edges of the lower wiring, which have steep side slopes, and can also reduce the difference in height between the concave and convex portions of the substrate surface. Therefore, the Al film formed by vapor deposition on the fluidized PSG film has sufficient thickness even on the side surfaces of the lower wiring, and does not cause breakage even when formed on the upper wiring by photolithography. . In addition, even if the side surface of the lower wiring is steep, the PSG gently covers it.
Since the Al film on the film does not produce any overhang, it forms a positive photoresist film during photolithography.
When irradiating ultraviolet rays, no photoresist remains on the side surface of the lower wiring due to insufficient exposure. Therefore
When etching the Al film, there is almost no etching in the lateral direction, and the Al film on the side surface of the lower wiring can be completely etched using the reactive sputtering method, which can etch faithfully to the photoresist pattern. It is possible to form a fine upper electrode without short circuits.

しかしながら、CVD法で形成した上記
CVDSiO2膜やPSG膜は、単結晶Si、あるいは多
結晶Siを熱酸化して形成したSiO2膜(以下熱酸化
膜とよぶ)に比較すると膜密度が小さく、又膜形
成中に生じた粒子状のSiO2あるいは反応装置か
ら剥離した粉末等が原因となる欠陥も多い。従つ
て配線間絶縁膜として用いる場合に上部、下部配
線間の短絡が生じたり、又膜の絶縁耐圧が低いた
め、電圧印加時にこの絶縁膜が局所的に破壊され
るなど、高密度、大面積のLSI、あるいは高い電
圧で動作させるLSIにおいては大きな問題とな
る。
However, the above formed by CVD method
CVDSiO 2 films and PSG films have lower film densities than SiO 2 films formed by thermally oxidizing single-crystalline Si or polycrystalline Si (hereinafter referred to as thermal oxide films), and they also contain particles generated during film formation. Many defects are caused by SiO 2 particles or powder exfoliated from the reactor. Therefore, when used as an inter-wiring insulating film, short circuits may occur between the upper and lower interconnects, and because the dielectric strength of the film is low, the insulating film may be locally destroyed when voltage is applied. This is a big problem for LSIs that operate at high voltages or for LSIs that operate at high voltages.

又前述のようにPSG膜を高温の熱処理を施して
流動させることによつて下部配線端部上での膜厚
が減少し、そのため通常でも電界が集中しやすい
この端部で絶縁破壊を生じやすくなる。
Furthermore, as mentioned above, by subjecting the PSG film to high-temperature heat treatment and causing it to flow, the film thickness on the lower wiring edge is reduced, and therefore dielectric breakdown is more likely to occur at this edge where electric fields tend to concentrate even under normal circumstances. Become.

本発明は前述したPSG膜が有する半導体装置の
特性の安定化、高熱処理時の流動という利点を十
分生かし、かつ欠陥が少なく絶縁耐圧も大きく
て、高電圧印加時にも配線間の短絡や局所的絶縁
破壊が生じない配線間絶縁膜を有する半導体装置
の製造方法に関するものであり、特にこの配線間
絶縁膜の形成工程を簡単化することを目的とする
ものである。
The present invention makes full use of the above-mentioned advantages of the PSG film, such as stabilization of the characteristics of semiconductor devices and flow during high heat treatment, and also has few defects and high dielectric strength, so that even when high voltage is applied, short circuits between wiring and local The present invention relates to a method of manufacturing a semiconductor device having an inter-wiring insulating film that does not cause dielectric breakdown, and is particularly aimed at simplifying the process of forming the inter-wiring insulating film.

配線間絶縁膜のうち欠陥が少ないものとして、
多結晶Si等の半導体よりなる下部配線の表面のみ
を熱酸化して得られる絶縁膜が用いられているが
特に下部配線の端部での絶縁破壊が起りやすく、
時には上部、下部配線間に5V程度印加されただ
けでも局所的に破壊されることがあり、又熱酸化
を進めると下部配線の厚さが小となるためこの絶
縁膜の厚さを大きくするのが困難である等の欠点
を有している。
Among inter-wiring insulating films, those with few defects are
An insulating film obtained by thermally oxidizing only the surface of the lower wiring made of a semiconductor such as polycrystalline Si is used, but dielectric breakdown is particularly likely to occur at the ends of the lower wiring.
Sometimes, even if only 5V is applied between the upper and lower wirings, local destruction may occur, and as thermal oxidation progresses, the thickness of the lower wiring becomes smaller, so it is necessary to increase the thickness of this insulating film. It has disadvantages such as difficulty in

本発明者は、半導体膜の表面だけを熱酸化する
のではなく、そのすべてを熱酸化膜に変換すると
欠陥も少なく、しかも絶縁耐圧も大きく、たとえ
急峻な傾斜の側面を有する下部配線の端部上をも
なだらかに覆うため電極間に電圧印加時に電界集
中が生じず、従つて局所的な絶縁破壊を生じるこ
とがない配線間絶縁膜が形成できることを見い出
した(これを半導体膜熱酸化法とよぶ)。
The inventor of the present invention has found that not only the surface of the semiconductor film is thermally oxidized, but the entire surface of the semiconductor film is converted into a thermal oxide film, which has fewer defects and has a high dielectric strength. We discovered that it is possible to form an inter-wiring insulating film that gently covers the top, so that no electric field concentration occurs when voltage is applied between the electrodes, and therefore no local dielectric breakdown occurs. ).

一方PSG膜は、その膜厚が0.5μmあるいはそ
れ以上であつてもウエツト酸素等の酸化性雰囲気
中で熱処理を施すと酸素や水酸基等の酸化剤が容
易に通過し、PSG膜下にある多結晶Si膜等の半導
体が容易に熱酸化されるという性質を有してい
る。
On the other hand, even if the PSG film has a thickness of 0.5 μm or more, if it is heat-treated in an oxidizing atmosphere such as wet oxygen, oxidizing agents such as oxygen and hydroxyl groups will easily pass through it. Semiconductors such as crystalline Si films have the property of being easily thermally oxidized.

本発明の製造方法は半導体よりなる下部配線の
表面に熱酸化膜を形成した後、半導体膜とPSG膜
を順次形成し、酸化性雰囲気中で熱処理を施す工
程を有し、前述のPSG膜が酸素等を容易に通過さ
せるという性質を利用して、PSG膜に覆われた状
態で前記半導体膜を完全に熱酸化膜に変換する
(前記の半導体膜熱酸化法)とともに、前記PSG
膜を流動させるものである。
The manufacturing method of the present invention includes a step of forming a thermal oxide film on the surface of a lower wiring made of semiconductor, then sequentially forming a semiconductor film and a PSG film, and performing heat treatment in an oxidizing atmosphere. Utilizing the property of allowing oxygen etc. to easily pass through, the semiconductor film covered with the PSG film is completely converted into a thermal oxide film (semiconductor film thermal oxidation method described above).
It allows the membrane to flow.

このように本発明は、PSG膜に覆われた半導体
膜の熱酸化する工程と、前記PSG膜を流動させて
上面を平坦にする工程とを同時に行なうため工程
が簡単化される。
As described above, the present invention simplifies the process because the process of thermally oxidizing the semiconductor film covered with the PSG film and the process of making the PSG film flow to flatten the top surface are performed simultaneously.

以下に本発明をSiゲートMOSLSIの製造に用い
た一実施例とともに各製造工程での部分断面を示
す第1図を用いて詳しく説明する。
The present invention will be described in detail below with reference to an embodiment in which the present invention is used in the manufacture of a Si gate MOSLSI, as well as FIG. 1 showing partial cross sections at each manufacturing process.

抵抗率が10ΩcmのP型Si基板1にフイールド部
のVTを大きくする為に1013/cm2のボロンイオン
を注入した後、Si3N4膜をマスクとした選択酸化
により厚さ0.7μmのフイールド酸化膜2を形成
し、厚さ0.1μmのゲート酸化膜3、n形不純物
であるリンを添加した厚さ0.5μmの多結晶Si膜
よりなるゲート電極や下部配線4を形成した後、
150KVの電圧で加速した4×1015/cm2の砒素イオ
ンを注入してソース、ドレイン5を形成する(第
1図a)。そして800℃のウエツト酸素雰囲気中で
加熱することにより、ゲート電極や下部配線4で
ある多結晶Si表面を酸化し、厚さ0.1μmの熱酸
化膜6を形成する(第1図b)。この熱酸化膜6
は後の熱酸化のストツパーの役目を果すものであ
り、多結晶Si4が高濃度のリンを添加されている
ため、熱酸化時の温度が800℃であつても容易に
0.1μmの熱酸化膜6を形成することができる。
一方この熱酸化時の温度が低いためソース、ドレ
イン5の領域上の熱酸化膜3は殆んど増大するこ
とがない。
Boron ions of 10 13 /cm 2 were implanted into a P-type Si substrate 1 with a resistivity of 10 Ωcm in order to increase the V T in the field portion, and then the Si 3 N 4 film was selectively oxidized to a thickness of 0.7 μm using the Si 3 N 4 film as a mask. After forming a field oxide film 2, a gate oxide film 3 with a thickness of 0.1 μm, and a gate electrode and lower wiring 4 made of a polycrystalline Si film with a thickness of 0.5 μm doped with phosphorus as an n-type impurity,
Arsenic ions of 4×10 15 /cm 2 accelerated at a voltage of 150 KV are implanted to form the source and drain 5 (FIG. 1a). By heating in a wet oxygen atmosphere at 800° C., the polycrystalline Si surfaces of the gate electrode and lower wiring 4 are oxidized to form a thermal oxide film 6 with a thickness of 0.1 μm (FIG. 1b). This thermal oxide film 6
serves as a stopper for later thermal oxidation, and because the polycrystalline Si4 is doped with a high concentration of phosphorus, it can be easily oxidized even at temperatures of 800°C during thermal oxidation.
A thermal oxide film 6 of 0.1 μm can be formed.
On the other hand, since the temperature during this thermal oxidation is low, the thermal oxide film 3 on the source and drain 5 regions hardly increases.

次に600℃におけるSiH4の熱分解により厚さ0.1
μmの半導体膜である多結晶Si膜7を形成し、さ
らに450℃におけるSiH4,O2の反応中にPH3を加
えることによつてリン濃度8wt%、厚さ0.5μmの
PSG膜8を形成した後(第1図c)、1000℃のウ
エツト酸素中で30分間熱処理を施すことによつ
て、PSG膜8を流動させると同時にPSG膜8下の
多結晶Si膜7を熱酸化膜70に変換する(第1図
d)。この熱処理中に、ゲート電極や下部配線4
はその表面に形成されている熱酸化膜6が酸素等
の酸化剤を阻止するためにこれ以上酸化されるこ
とはなく、又Si基板よりなるソース、ドレイン5
の領域も熱酸化膜3が形成されている為に酸化さ
れることはない。
Next, by thermal decomposition of SiH 4 at 600℃, the thickness of 0.1
A polycrystalline Si film 7, which is a semiconductor film of μm thickness, is formed, and by adding PH 3 during the reaction of SiH 4 and O 2 at 450°C, a phosphorus concentration of 8 wt% and a thickness of 0.5 μm is formed.
After forming the PSG film 8 (FIG. 1c), heat treatment is performed for 30 minutes in wet oxygen at 1000°C to flow the PSG film 8 and at the same time, to melt the polycrystalline Si film 7 under the PSG film 8. It is converted into a thermal oxide film 70 (FIG. 1d). During this heat treatment, the gate electrode and lower wiring 4
The thermal oxide film 6 formed on the surface of the source and drain 5 formed on the Si substrate is prevented from being further oxidized because it blocks oxidizing agents such as oxygen.
The area is also not oxidized because the thermal oxide film 3 is formed thereon.

その後は写真蝕刻法を用いてホトレジストをマ
スクにしてPSG膜8、多結晶Si膜より変換した熱
酸化膜70、さらに下部配線4表面の熱酸化膜6
あるいはSi基板表面の熱酸化膜3をHFのNH4Fに
よる希釈液等で蝕刻して、コンタクト窓9を開口
する。そして真空蒸着法等で厚さ1.2μmのAl膜
を形成し、写真蝕刻法で上部電極10を形成する
(第1図e)。
Thereafter, using a photolithography method, a photoresist is used as a mask to form a PSG film 8, a thermal oxide film 70 converted from a polycrystalline Si film, and a thermal oxide film 6 on the surface of the lower wiring 4.
Alternatively, the contact window 9 is opened by etching the thermal oxide film 3 on the surface of the Si substrate with a diluted solution of HF with NH 4 F or the like. Then, a 1.2 μm thick Al film is formed by vacuum evaporation or the like, and an upper electrode 10 is formed by photolithography (FIG. 1e).

前述のようにPSG膜8は酸化性雰囲気中での熱
処理により酸化剤を容易に通すのでその下の多結
晶Si膜のような半導体膜7は容易に熱酸化され、
そのすべてが熱酸化膜70に変換されるが、下部
配線4の表面にはPSG膜8の形成前に熱酸化膜6
が形成されているため酸化剤は阻止されて上記熱
処理中に下部配線4が熱酸化されることはない。
又Si基板よりなるソース、ドレイン5の領域の表
面に熱酸化膜3が形成されているため同様に熱酸
化されることはない。
As mentioned above, the PSG film 8 easily passes the oxidizing agent through heat treatment in an oxidizing atmosphere, so the underlying semiconductor film 7 such as a polycrystalline Si film is easily thermally oxidized.
All of it is converted into a thermal oxide film 70, but the surface of the lower wiring 4 is covered with a thermal oxide film 6 before the PSG film 8 is formed.
is formed, the oxidizing agent is blocked and the lower wiring 4 is not thermally oxidized during the heat treatment.
Further, since the thermal oxide film 3 is formed on the surface of the source and drain 5 regions made of the Si substrate, they are not thermally oxidized as well.

酸化性の雰囲気中での熱処理中に半導体膜7に
はその上に形成されているPSG膜8中に含まれる
リンが添加されて無添加の半導体膜よりも熱酸化
速度が大きくなつているが、半導体膜7の形成中
に前述のSiH4にPH3のような不純物ガスを混入す
ることによつて、あるいは膜形成後に熱拡散法等
によつてリン等の不純物を添加した半導体膜7を
形成すると、熱酸化速度をよりいつそう大きくす
ることができ、短時間の熱処理でも厚い熱酸化膜
70を形成することができる。さらに熱処理を行
う際に反応容器内の圧力を例えば7気圧と大きく
することにより、よりいつそう前述の酸化速度を
大きくすることができ、低温の熱処理でも同様の
効果を得ることができる。
During the heat treatment in an oxidizing atmosphere, the semiconductor film 7 is doped with phosphorus contained in the PSG film 8 formed thereon, resulting in a higher thermal oxidation rate than a semiconductor film without additives. The semiconductor film 7 is made by adding impurities such as phosphorus by mixing an impurity gas such as PH 3 into the SiH 4 described above during the formation of the semiconductor film 7, or by a thermal diffusion method after the film formation. When formed, the thermal oxidation rate can be further increased, and a thick thermal oxide film 70 can be formed even with a short heat treatment. Furthermore, by increasing the pressure in the reaction vessel to, for example, 7 atmospheres when performing heat treatment, the above-mentioned oxidation rate can be further increased, and the same effect can be obtained even with low-temperature heat treatment.

上記の実施例のように酸化性の雰囲気中での熱
処理後にホトレジストをマスクにしてHFの希釈
液でPSG膜や熱酸化膜等を蝕刻してコンタクト窓
を開口する場合には(第1図eに示す)PSG膜8
の蝕刻速度がその下の熱酸化膜70,6のそれよ
りも大きいために、PSG膜が蝕刻された後ひき続
いてその下の熱酸化膜70,6あるいは熱酸化膜
3が蝕刻される間にPSG膜8は横方向に大きく蝕
刻されその結果、開口されたコンタクト窓9はホ
トレジストの開口径よりも著しく大きくなる。こ
れをさけるため第2図に示すように、第1図のa
〜cに示す工程でPSG膜8を形成した後、コンタ
クト窓部を含みコンタクト窓よりも大なる領域の
PSG膜を写真蝕刻法で除去して開口部90を設け
(第2図a)た後に、前述の熱処理を施す。その
後で開口部90内に写真蝕刻法を用いてコンタク
ト窓9を開口する(第2図b)が、このコンタク
ト窓9開口時にはすでにPSG膜8は除去されてお
り、蝕刻速度が殆んど等しい熱酸化膜70,6あ
るいは熱酸化膜3のみを蝕刻するため横方向に大
きくエツチングされることはなく、従つて開口し
たコンタクト窓9が大きくなりすぎることがなく
微小なコンタクト窓を開口することができる。
As in the above embodiment, when a contact window is opened by etching the PSG film, thermal oxide film, etc. with a diluted HF solution using a photoresist as a mask after heat treatment in an oxidizing atmosphere (see Fig. 1e). ) PSG film 8
Since the etching speed of the PSG film is higher than that of the thermal oxide film 70, 6 below, the thermal oxide film 70, 6 or the thermal oxide film 3 below it is etched after the PSG film is etched. Then, the PSG film 8 is largely etched in the lateral direction, and as a result, the opened contact window 9 becomes significantly larger than the opening diameter of the photoresist. To avoid this, as shown in Figure 2, a
After forming the PSG film 8 in the steps shown in ~c, a region larger than the contact window including the contact window portion is formed.
After the PSG film is removed by photolithography to form an opening 90 (FIG. 2a), the heat treatment described above is performed. Thereafter, a contact window 9 is opened in the opening 90 using photolithography (FIG. 2b), but when this contact window 9 is opened, the PSG film 8 has already been removed, and the etching speed is almost the same. Since only the thermal oxide films 70, 6 or the thermal oxide film 3 are etched, they are not etched to a large extent in the lateral direction, and therefore the opened contact windows 9 do not become too large, making it possible to open minute contact windows. can.

以上述べた本発明の半導体装置の製造方法にお
いては、PSG膜に覆われた半導体膜を酸化する工
程と、前記PSG膜を流動させる工程とを同時に行
なうため製造工程が大幅に簡単化される効果があ
る。さらに、本発明の製造方法により形成された
第1の絶縁膜と、半導体膜より変換された熱酸化
膜と、流動したPSG膜の3層よりなる絶縁膜は、
前述のように絶縁耐圧の大きい熱酸化膜があるた
め配線間の短絡の原因となる欠陥が少なく絶縁耐
圧も大きいという配線間絶縁膜として十分な特性
を有している。又表面は流動したPSG膜のため、
前述のように微細な上部配線を容易に形成するこ
とができる。さらに半導体膜上のPSG膜は、熱処
理によつて流動しやすく、特にリンを添加した半
導体膜上のPSG膜は熱処理中に半導体膜へリンが
拡散することによるリン濃度の低下がないためい
つそう流動しやすく、より大きな効果を得ること
ができる。
In the method for manufacturing a semiconductor device of the present invention described above, the process of oxidizing the semiconductor film covered with the PSG film and the process of fluidizing the PSG film are performed simultaneously, so the manufacturing process is greatly simplified. There is. Furthermore, the insulating film consists of three layers: the first insulating film formed by the manufacturing method of the present invention, the thermal oxide film converted from the semiconductor film, and the fluidized PSG film.
As mentioned above, since there is a thermal oxide film with a high dielectric strength, it has sufficient characteristics as an inter-wiring insulating film, with few defects that cause short circuits between wires and a high dielectric strength. Also, because the surface is a fluidized PSG film,
As described above, fine upper wiring can be easily formed. Furthermore, PSG films on semiconductor films tend to flow during heat treatment, and in particular, PSG films on semiconductor films to which phosphorus has been added do not have a drop in phosphorus concentration due to diffusion of phosphorus into the semiconductor film during heat treatment. It flows easily and can produce greater effects.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a〜eは本発明の一実施例における半導
体装置の製造方法の各工程における部分断面図、
第2図a,bは同工程の一部を改良した製造方法
の各工程における部分断面図である。 1…半導体基板(P型Si基板)、4……下部配
線、6……第1の熱酸化膜、7……第2の半導体
膜(多結晶Si膜)、8……リンケイ酸ガラス膜
(PSG膜)、70……第2の熱酸化膜。
FIGS. 1a to 1e are partial cross-sectional views at each step of a method for manufacturing a semiconductor device according to an embodiment of the present invention,
FIGS. 2a and 2b are partial cross-sectional views of each step of the manufacturing method in which a part of the same process is improved. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate (P-type Si substrate), 4... Lower wiring, 6... First thermal oxide film, 7... Second semiconductor film (polycrystalline Si film), 8... Phosphorsilicate glass film ( PSG film), 70... second thermal oxide film.

Claims (1)

【特許請求の範囲】 1 第1の半導体膜よりなる下部配線が形成され
た半導体基板を酸化雰囲気中で熱処理を施し、前
記下部配線表面に第1の熱酸化膜を形成する工程
と、次に第2の半導体膜を形成する工程と、次に
リンケイ酸ガラス膜を形成する工程と、酸化雰囲
気中で熱処理を施して前記リンケイ酸ガラス膜を
流動させるとともに前記第2の半導体膜を第2の
熱酸化膜に変換する工程とよりなることを特徴と
する半導体装置の製造方法。 2 第2の半導体膜が、リンの添加された半導体
膜であることを特徴とする特許請求の範囲第1項
に記載の半導体装置の製造方法。
[Claims] 1. A step of heat-treating a semiconductor substrate on which a lower wiring made of a first semiconductor film is formed in an oxidizing atmosphere to form a first thermal oxide film on the surface of the lower wiring; A step of forming a second semiconductor film, a step of forming a phosphosilicate glass film, and a heat treatment in an oxidizing atmosphere to flow the phosphosilicate glass film and convert the second semiconductor film into a second semiconductor film. 1. A method for manufacturing a semiconductor device, comprising a step of converting into a thermal oxide film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the second semiconductor film is a semiconductor film doped with phosphorus.
JP11456580A 1980-08-19 1980-08-19 Manufacture of semiconductor device Granted JPS5737858A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11456580A JPS5737858A (en) 1980-08-19 1980-08-19 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11456580A JPS5737858A (en) 1980-08-19 1980-08-19 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5737858A JPS5737858A (en) 1982-03-02
JPS6137780B2 true JPS6137780B2 (en) 1986-08-26

Family

ID=14640991

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11456580A Granted JPS5737858A (en) 1980-08-19 1980-08-19 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5737858A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6214443A (en) * 1985-07-12 1987-01-23 Pioneer Electronic Corp Manufacture of semiconductor device
JP2964015B2 (en) * 1990-11-26 1999-10-18 富士写真フイルム株式会社 Silver halide color photographic materials

Also Published As

Publication number Publication date
JPS5737858A (en) 1982-03-02

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