JPS6137200U - semiconductor memory device - Google Patents
semiconductor memory deviceInfo
- Publication number
- JPS6137200U JPS6137200U JP12094584U JP12094584U JPS6137200U JP S6137200 U JPS6137200 U JP S6137200U JP 12094584 U JP12094584 U JP 12094584U JP 12094584 U JP12094584 U JP 12094584U JP S6137200 U JPS6137200 U JP S6137200U
- Authority
- JP
- Japan
- Prior art keywords
- field effect
- effect transistor
- memory device
- memory cell
- semiconductor memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Static Random-Access Memory (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の実施例を説明するための回路図、第２
図は第１図の回路の動作を説明するための図、第３図及
び第５図は従来のスタティックメモリの回路図、第４図
及び第６図はそれぞれ第３図及び第５図の回路の動作を
説明するための図である。
ＣＩ， Ｃ２・・・・・・メモリセル、Ｖｏ・・・・・
・定電位電源、Ｇ・・・・・・接地電位、Ｂ・・・・・
・非反転ビット線、百・・・・・・反転ビット線、Ｗｌ
， Ｗ２・・曲ワード線、Ｑ１１〜Ｑ１４・・・・・・
Ｅ．ＦＥＴ，Ｑｌ ５，Ｑｌ ６・・・・・・Ｄ．ＦＥ
ＴＸＱＢＩ，ＱＢ２，ＱＢ５，ＱＢ６・・・・・−Ｅ−
ＦＥＴプルアップ、ＱＢ３，ＱＢ４，ＱＢ７，ＱＢ８・
・・・・・Ｄ．ＦＥＴプルアップ、Ｎｌ，Ｎ２・・曲ノ
ード。Figure 1 is a circuit diagram for explaining an embodiment of the present invention, Figure 2 is a circuit diagram for explaining an embodiment of the present invention.
The figure is a diagram for explaining the operation of the circuit in Figure 1, Figures 3 and 5 are circuit diagrams of conventional static memory, and Figures 4 and 6 are the circuits in Figures 3 and 5, respectively. FIG. CI, C2...Memory cell, Vo...
・Constant potential power supply, G...Ground potential, B...
・Non-inverted bit line, 100...Inverted bit line, Wl
, W2...Curved word line, Q11~Q14...
E. FET, Ql 5, Ql 6...D. FE
TXQBI, QB2, QB5, QB6...-E-
FET pull-up, QB3, QB4, QB7, QB8・
...D. FET pull-up, Nl, N2... song node.
Claims (1)
、該スタテイクメモリセルのビット線にゲート電極及び
ソース蕾極が接続されたデプレツション型の第１電界効
果トランジスタと、前記スタテイクメモリセルの前記ビ
ット線にソース電極カ忙接続されたエンハンスメント型
あるいはデプレツション型の第２電界効果トランジスタ
と、前記第１電界効果トランジスタのドレイン電極が接
続され且つ前記第２電界効果トランジスタのドレイン電
極及びゲート電極が接続された定電位電源とを備えてな
ることを特徴とする半導体メモリ装置。a static memory cell using a field effect transistor; a first depletion type field effect transistor having a gate electrode and a source electrode connected to a bit line of the static memory cell; and the bit line of the static memory cell. a second enhancement type or depletion type field effect transistor having a source electrode connected to the drain electrode of the first field effect transistor, and a drain electrode and a gate electrode of the second field effect transistor connected to each other; A semiconductor memory device comprising a constant potential power source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12094584U JPS6137200U (en) | 1984-08-08 | 1984-08-08 | semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12094584U JPS6137200U (en) | 1984-08-08 | 1984-08-08 | semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6137200U true JPS6137200U (en) | 1986-03-07 |
Family
ID=30679742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12094584U Pending JPS6137200U (en) | 1984-08-08 | 1984-08-08 | semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6137200U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54148442A (en) * | 1978-05-15 | 1979-11-20 | Nec Corp | Memory unit |
-
1984
- 1984-08-08 JP JP12094584U patent/JPS6137200U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54148442A (en) * | 1978-05-15 | 1979-11-20 | Nec Corp | Memory unit |
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