JPH0522998B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a word selection line drive circuit for a semiconductor memory device, etc., and particularly relates to an improvement in the structure of the word selection line drive circuit for reducing power consumption and speeding up the operation.

(b) Background of the technology The scale of integration of semiconductor integrated circuit devices is rapidly expanding, and storage devices in particular are seen as a representative example of this, and are widely used in many systems, including the main storage devices of electronic computers. and contribute to its progress.

Furthermore, along with advances in semiconductor integrated circuit devices that use silicon (Si) as a semiconductor material, compound semiconductors such as gallium arsenide (GaAs), which have properties such as electron mobility that are far superior to Si, are being used to improve the physical properties of Si. The development of integrated circuit devices that go beyond their limits is progressing, and storage devices are also being developed using shot-barrier field effect transistors, modulation-doped heterojunction field effect transistors, and the like as elements.

(c) Conventional technology and problems Field effect transistor (hereinafter abbreviated as FET)
FIG. 1 shows an example of a semiconductor memory cell having a semiconductor memory cell as an element. In the figure, T ₁ to T ₆ are enhancement mode FETs, and FETs T ₁ and T ₂ are load elements.
A bistable flip-flop circuit is formed together with _T3 and _T4 , and binary information " ₁ " or "0" is stored when either T1 or _T2 is in a conductive state. Further, _T5 and _T6 are gate transistors for electrically connecting the cell and an external circuit in order to read information stored in the memory cell or to store new information, and are connected to the gate electrode. The flip-flop circuit and the digit signal line D are turned on and off by the selected word selection line W.

The memory cells are arranged in a matrix, the word selection lines being selected by a decoder and usually driven by a buffer amplifier. FIG. 2 shows an example of a conventional word selection line drive circuit.
_T11 is the drive FET of the inverter circuit, and _T12 is its load FET. The drive circuit sets the selected word selection line to a high level H to drive the gate FET of the memory cell.
T ₅ and T ₆ are turned on, and the unselected word selection line is set to low level L, and the gate FET T 5 and T ₆ of the memory cell are turned on.
T ₆ is kept off, but for this purpose the drive transistor T ₁₁ of the drive circuit of a number of unselected word selection lines must be turned on, except for only one selected word selection line. That is, the drive circuit as in the above example requires a large amount of current for the selection operation.

In semiconductor memory devices, reducing power consumption is extremely important for increasing the degree of integration and improving characteristics, and the word selection line drive circuit described above also needs to be improved.

(d) Purpose of the Invention The present invention addresses the above-mentioned problems and aims to reduce the power consumption of a non-selected word selection line drive circuit, thereby providing a low power consumption and high speed word selection line drive circuit. do.

(e) Structure of the Invention The object of the present invention is to provide a drive transistor element and a load element of the drive transistor element,
This is achieved by a word selection line drive circuit in which the load element is connected to the drive transistor element and a ground line, and an output is supplied to the word selection line from a connection point between the drive transistor element and the load element.

That is, in the present invention, contrary to the conventional example, by connecting the load element to the ground line side and the drive transistor to the ungrounded power supply side, the ground of the unselected word selection line is connected to the state where the drive transistor is off. , a high level H of the selected word selection line is formed by the ON state of the drive transistor.

As a result of this circuit configuration, sufficient drive current can be supplied to drive the selected word selection line, increasing operating speed, while many unselected word selection line driving circuits do not consume power. The power consumption of the entire drive circuit is significantly reduced.

(f) Embodiments of the Invention The present invention will be specifically described below using embodiments with reference to the drawings.

Figures 3a and 3b are circuit diagrams showing an embodiment of the invention. In the figure, T ₂₁ is the drive FET in n-channel enhancement mode, T ₂₂ is the load FET in n-channel depletion mode, R is the load resistor, W is the word selection line, V _ss is the ground line, and V _DD is ungrounded. Power bus, In indicates the input end.

In other words, the drain of drive FET T ₂₁ is the power bus
V _DD and its source is connected to load T ₂₂ or R. The opposite end of the load T ₂₂ or R is connected to the ground line V _SS and the output to the word selection line W is taken from the connection point between the drive FET T ₂₁ and the load T ₂₂ or R.

The operation of the drive circuit of the present invention is as follows.
In other words, the input of the drive circuit of the selected word selection line
In is set to high level, and the input In of the unselected drive circuit is set to low level. The drive FET T ₂₁ of the selected circuit is turned on, current flows through the load T ₂₂ or R, and the word selection line W becomes high level H. Further, the drive FET T ₂₁ of the non-selected circuit is off, and the word line selection line W is kept at a low level L. Since the drive circuit of the present invention operates as described above, sufficient drive current can be applied to the selected drive circuit to allow it to operate at high speed, while unselected drive circuits consume almost no power.

(g) Effects of the Invention As explained above, according to the present invention, a sufficient drive current is applied to the word selection line drive circuit when the word selection line drive circuit is selected;
Moreover, no power is consumed when it is not selected, which has the effect of making the semiconductor memory device faster and with lower power consumption.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a memory cell of a semiconductor memory device, FIG. 2 is a circuit diagram showing a conventional example of a word selection line drive circuit, and FIGS. 3 a and b are circuit diagrams showing an embodiment of the present invention. It is. In the figure, T ₂₁ is the drive FET and T ₂₂ is the load
FET, R is a load resistor, W is a word selection line, V _SS is a ground line, V _DD is an ungrounded power supply bus, and In is an input terminal.

Claims (1)

[Claims] 1 comprising a drive transistor element and a load element for the drive transistor element, the load element is connected to the drive transistor element and a ground line, and a word selection line is connected from a connection point between the drive transistor element and the load element; A word selection line drive circuit, characterized in that an output is supplied to the word selection line drive circuit.