JPS6136954A - High-frequency output transistor - Google Patents
High-frequency output transistorInfo
- Publication number
- JPS6136954A JPS6136954A JP15982084A JP15982084A JPS6136954A JP S6136954 A JPS6136954 A JP S6136954A JP 15982084 A JP15982084 A JP 15982084A JP 15982084 A JP15982084 A JP 15982084A JP S6136954 A JPS6136954 A JP S6136954A
- Authority
- JP
- Japan
- Prior art keywords
- electrode pad
- dielectric layer
- transistor
- electrode
- impedance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は高周波冨出力トランジスタに関し、特にインピ
ーダンス変換用の内部整合回路を有する高周波高出力ト
ランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a high frequency high power transistor, and more particularly to a high frequency high power transistor having an internal matching circuit for impedance conversion.
（従来の技術）
一般に、高周波路出力トランジスタは、高出力化に伴っ
て入力インピーダンスが低くなる。このため、外部回路
とのインピーダンスの整合が悪くなり、十分な性能で使
用することができなくなる。(Prior Art) Generally, the input impedance of a high-frequency path output transistor decreases as the output increases. As a result, impedance matching with external circuits deteriorates, making it impossible to use the device with sufficient performance.
これを改良するため、半導体素子用の容器内部に整合回
路用の受動素子を載置して、これによりインピーダンス
変換を行う方法が行なわれている。In order to improve this, a method has been used in which a passive element for a matching circuit is placed inside a container for a semiconductor element, and impedance conversion is performed using this element.
第４図は従来の高周波トランジスタのチップの一例の平
面図である。FIG. 4 is a plan view of an example of a conventional high frequency transistor chip.
第４図において、１はチップ基体、２は出力側電極パッ
ド、３は接地側電極パッド、４は入力側電極パッドであ
る。In FIG. 4, 1 is a chip base, 2 is an output side electrode pad, 3 is a ground side electrode pad, and 4 is an input side electrode pad.
第５図（ａｌ 、 （ｂｌは第４図に示すチップを用い
た高周波トランジスタの一例の平面図及び断面図である
。FIG. 5 (al and bl are a plan view and a sectional view of an example of a high frequency transistor using the chip shown in FIG. 4.
容器の一部を構成し接地電極として作用する放熱板１１
に容器の一部を構成するフレーム１２を取付ける。フレ
ーム１２は二段になっておシ、入力電極引出しリード１
３、出力電極引出しリードｌ４がフレーム１２内を通っ
て引出される。このようにして構成される容器内にトラ
ンジスタのチ、グｌ、容量素子５を取付け、ボンディン
グ線１６〜１９でそれぞれ結線する。容量素子５は前述
の整合回路用である。A heat sink 11 that forms part of the container and acts as a ground electrode.
A frame 12 constituting a part of the container is attached to the container. The frame 12 has two stages, and the input electrode lead 1
3. The output electrode extraction lead l4 passes through the frame 12 and is extracted. The transistors 1, 1, and capacitive element 5 are mounted in the container constructed in this way, and connected with bonding wires 16 to 19, respectively. The capacitive element 5 is for the above-mentioned matching circuit.
第６図は第５図（ａｌ 、 （ｂ）に示すトランジスタ
のインピーダンス変換軌跡を示すスミス図表である。FIG. 6 is a Smith chart showing the impedance transformation locus of the transistor shown in FIGS. 5(al) and (b).
このスミス図表は、トランジスタを１５ＧＨｚで動作さ
せた例を示した。今、容量素子５の容量を０．５ｐＦ、
ボンディング線１８．１９が共に直径３０μｍφ、長さ
４００μｍの金線で、ボンディング線１９はこの金線を
２本用いるものとする。This Smith chart shows an example in which the transistor is operated at 15 GHz. Now, the capacitance of capacitive element 5 is 0.5 pF,
The bonding wires 18 and 19 are both gold wires having a diameter of 30 μmφ and a length of 400 μm, and the bonding wire 19 uses two of these gold wires.
第６図において、ａをトランジスタのチ、ブｌの入力側
のインピーダンス・ポイントとすると、ボンディング線
ｔｓＶＣよ、？ ０．３ ｎＨのインダクタンス分でｂ
点までインピーダンス変換され、さらに容量素子５によ
りＣ点まで、そしてボンディング線１９により０．３ｎ
Ｈのインダクタンス６点までインピーダンス変換される
。In FIG. 6, if a is the impedance point on the input side of transistors 1 and 1, bonding line tsVC, ? b with an inductance of 0.3 nH
The impedance is converted to point C, and then the capacitive element 5 converts the impedance to point C, and the bonding wire 19 converts the impedance to 0.3n.
Impedance conversion is performed up to 6 points of inductance of H.
インピーダンス変換経路がスミス図表の周辺であり、明
らかに動作Ｑが高く不安定な素子と言える。The impedance conversion path is around the Smith diagram, and it can be said that the element has a clearly high operational Q and is unstable.
（発明が解決しようとする問題点）
このように、特に周波数の高いＧａＡｓ ＰＥＴのよう
な高周波素子においては、ボンディング線１８のインダ
クタンスの影響により、有効なインピーダンスの変換が
行なわれなくなっているという問題がある。(Problems to be Solved by the Invention) As described above, in high frequency devices such as GaAs PET, which has a particularly high frequency, the problem is that effective impedance conversion cannot be performed due to the influence of the inductance of the bonding wire 18. There is.
本発明の目的は、このようなボンディング線の影響を々
〈シ、入力インピーダンスを効果的に変換し、動作Ｑが
低く、広帯域で安定な動作が可能な、内部整合回路付き
の高周波夢出力トランジスタを提供することにある。The purpose of the present invention is to eliminate the influence of such bonding lines, effectively convert input impedance, and provide a high-frequency output transistor with an internal matching circuit that can effectively convert input impedance, have a low operation Q, and enable stable operation over a wide band. Our goal is to provide the following.
（問題点を解決するための手段）
本発明の高周波ｌ出力トランジスタは、トランジスタが
形成されている半導体チップと、該半導体チップの表面
に設けられた第１の電極パッドと、該第１の電極パッド
の少くとも一部を覆って設けられた誘電体層と、前記第
１の電極パッドに一部が重なるように前記誘電体層の上
に設けられた第２の電極とを有し、前記第１及び第２の
電極パッドと前記誘電体層とで容量を形成したことを特
徴として構成される。(Means for Solving the Problems) The high frequency l output transistor of the present invention includes a semiconductor chip on which the transistor is formed, a first electrode pad provided on the surface of the semiconductor chip, and a first electrode pad provided on the surface of the semiconductor chip. a dielectric layer provided to cover at least a portion of the pad; and a second electrode provided on the dielectric layer so as to partially overlap the first electrode pad; The structure is characterized in that a capacitor is formed by the first and second electrode pads and the dielectric layer.
（実施例） 次に、本発明の実施例について図面を用いて説明する。(Example) Next, embodiments of the present invention will be described using the drawings.
第１図（ａ） 、 （ｂ）は本発明の一実施例の平面図
及び断面図である。FIGS. 1(a) and 1(b) are a plan view and a sectional view of an embodiment of the present invention.
この実施例は、トランジスタが形成されている半導体チ
ップｌと、この半導体チップｌの表面に設けられた第１
の電極パッド（接地側電極バッド）３′と、この第１の
電極パッド３′の少くとも一部を覆って設けられた誘電
体層６と、第１の電極バ。This embodiment includes a semiconductor chip l on which a transistor is formed, and a first semiconductor chip provided on the surface of this semiconductor chip l.
an electrode pad (ground side electrode pad) 3', a dielectric layer 6 provided to cover at least a portion of the first electrode pad 3', and a first electrode pad.
ド３’に一部が重なるように誘電体層６の上に設けられ
た第２の電極（入力側電極パッド）４′とを有し、第１
及び第２の電極パッド３′、４′と誘電体層６との重な
り部分で容量を形成したこと１に特徴として構成される
。誘電体層６は、例えば５ｉ０２ｉＣＶＤ法で堆積して
形成する。a second electrode (input side electrode pad) 4' provided on the dielectric layer 6 so as to partially overlap the pad 3';
The second electrode pad 3', 4' and the dielectric layer 6 overlap each other to form a capacitor. The dielectric layer 6 is formed by depositing, for example, a 5i02i CVD method.
上記実施例では第１の電極パッドとして接地側電極パッ
ド、第２の電極パッドとして入力側電極パッドを選んだ
が、これは逆にしても差支えない。In the above embodiment, the ground-side electrode pad is selected as the first electrode pad, and the input-side electrode pad is selected as the second electrode pad, but this may be reversed.
第２図は第１図（ａｌ 、 （ｂｌに示した実施例の半
導体チップｌを用いて作った高周波高出力トランジスタ
の平面図である。第５図（ａｌ Ｋ示した従来例と同様
に製作する。同じ物に対しては同じ番号全村しである。Figure 2 is a plan view of a high-frequency, high-output transistor manufactured using the semiconductor chip l of the embodiment shown in Figures 1 (al, bl). The same number is used for all the same items.
第３図は第２図に示すトランジスタのインピー汐゛ンス
変換軌跡を示すスミス図表である。FIG. 3 is a Smith chart showing the impedance conversion locus of the transistor shown in FIG. 2.
第２図に示すトランジスタの第１の電極パッド３′と第
２の電極パッド４′の重なり部分の面積を１２０００μ
−９誘電体層６はＳｉＯ□をＣＶＤ法により２０００Ｘ
の厚さに堆積するものとする。これＫよシ約２ｐＦの容
量を得る。ボンディング線１８゜１９については従来例
と同じくシ、容量素子５として０．４ｐＦのものを選ぶ
。このようなトランジスタｅ１５ＧＨｚで動作させるも
のとする。このときの入力側インピーダンスの変換軌跡
をスεス図表上に示すと第３図のようになる。The area of the overlapping portion of the first electrode pad 3' and the second electrode pad 4' of the transistor shown in FIG. 2 is 12000μ.
-9 Dielectric layer 6 is made of SiO□ by CVD method at 2000X
shall be deposited to a thickness of . This gives a capacitance of about 2 pF compared to K. As for the bonding lines 18 and 19, a capacitive element 5 of 0.4 pF is selected as in the conventional example. It is assumed that such a transistor e is operated at 15 GHz. The transformation locus of the input side impedance at this time is shown in FIG. 3 on a graph.
半導体テップｌのインピーダンスはチップ上の容量によ
Ｆ）ｅ点まで変換される。次に、ボンディング線１８に
よＪｆ点へ、容量素子５によりｇ点へ、ボンディング線
１９によりｈ点へインピーダンス変換される。The impedance of the semiconductor chip l is converted to point F) by the capacitance on the chip. Next, the impedance is converted to point Jf by the bonding line 18, to point g by the capacitive element 5, and to point h by the bonding line 19.
（発明の効果）
以上説明したよう忙、本発明によれば、トランジスタチ
ップのインピーダンスがａ点からｅ点へ変換され、周波
数の高いトランジスタにおいても、動作Ｑが低く、安定
した内部整合回路付きの高周波高出力トランジスタが得
られる。(Effects of the Invention) As explained above, according to the present invention, the impedance of the transistor chip is converted from point a to point e, and even in high frequency transistors, the operation Q is low and the internal matching circuit is stable. A high frequency, high output transistor can be obtained.
第１図（ａｌ 、 （ｂ）は本発明の一実施例の平面図
及び断面図、第２図は第１図（ａｌ 、 （ｂｌＫ示し
た実施例を用いた製造した高周波高出力トランジスタの
平面図、第３図は第２図に示す高周波高出力トランジス
タのインピーダンス変換軌跡を示すスミス図、第４図は
従来の高周波トランジスタのチップの一例の平面図、第
５図ｆａｔ 、 （ｂ）は第４図に示したチ。
プを用いた高周波トランジスタの平面図及び断面図、第
６図は第５図ｆａｔ 、 （ｂ）に示した高周波トラン
ジスタのインピーダンスの変換軌跡に示すスミス図であ
る。
１・・・・・・半導体チップ、２・・・・・−出力側電
極パッド、３・・・・・・接地側電極パッド、３′・・
・・・・第１の電極パッド、４・・・・・・入力側電極
パッド、４′・・山・第２の電極パッド、５・・・・・
・容量素子、６・・・・・・誘電体層、１１・・・・・
・放熱板、１２・・・・・・フレーム、１３・旧・・入
力電極引出しリード、１４・・・・・・出力電極引出し
リード、１６．１７，１８．１９・・・・・・ボンディ
ング線。
す【１Figure 1 (al, (b) is a plan view and cross-sectional view of one embodiment of the present invention, and Figure 2 is a plan view of a high frequency, high power transistor manufactured using the embodiment shown in Figure 1 (al, (blK). Figure 3 is a Smith diagram showing the impedance transformation locus of the high-frequency, high-output transistor shown in Figure 2, Figure 4 is a plan view of an example of a conventional high-frequency transistor chip, Figure 5 is a Figure 4 is a plan view and cross-sectional view of a high-frequency transistor using a chip shown in Figure 4, and Figure 6 is a Smith diagram showing the impedance conversion locus of the high-frequency transistor shown in Figure 5 (b). ... Semiconductor chip, 2 ... - Output side electrode pad, 3 ... Ground side electrode pad, 3'...
...First electrode pad, 4...Input side electrode pad, 4'...Mountain/second electrode pad, 5...
・Capacitive element, 6...Dielectric layer, 11...
・Heat sink, 12... Frame, 13. Old... Input electrode lead, 14... Output electrode lead, 16.17, 18.19... Bonding wire . [1
Claims (1)
導体チップの表面に設けられた第１の電極パッドと、該
第１の電極パッドの少くとも一部を覆って設けられた誘
電体層と、前記第１の電極バッドに一部が重なるように
前記誘電体層の上に設けられた第２の電極とを有し、前
記第１及び第２の電極パッドと前記誘電体層とで容量を
形成したことを特徴とする高周波出力トランジスタ。a semiconductor chip on which a transistor is formed; a first electrode pad provided on a surface of the semiconductor chip; a dielectric layer provided covering at least a portion of the first electrode pad; a second electrode provided on the dielectric layer so as to partially overlap the first electrode pad, and a capacitance is formed by the first and second electrode pads and the dielectric layer. A high frequency output transistor characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15982084A JPS6136954A (en) | 1984-07-30 | 1984-07-30 | High-frequency output transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15982084A JPS6136954A (en) | 1984-07-30 | 1984-07-30 | High-frequency output transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6136954A true JPS6136954A (en) | 1986-02-21 |
Family
ID=15701961
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15982084A Pending JPS6136954A (en) | 1984-07-30 | 1984-07-30 | High-frequency output transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6136954A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54133952A (en) * | 1978-04-05 | 1979-10-18 | Sadaaki Takagi | Device for continuously making cushion material |
| JPS54138669A (en) * | 1978-04-19 | 1979-10-27 | Sadaaki Takagi | Cushion material and production |
| US5008141A (en) * | 1988-05-27 | 1991-04-16 | Paramount Bed Co., Ltd. | Cushioning material for mattresses |
-
1984
- 1984-07-30 JP JP15982084A patent/JPS6136954A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54133952A (en) * | 1978-04-05 | 1979-10-18 | Sadaaki Takagi | Device for continuously making cushion material |
| JPS54138669A (en) * | 1978-04-19 | 1979-10-27 | Sadaaki Takagi | Cushion material and production |
| US5008141A (en) * | 1988-05-27 | 1991-04-16 | Paramount Bed Co., Ltd. | Cushioning material for mattresses |
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