JPH0521710A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an MIM capacitor with a large capacity value and high withstand voltage for a high frequency IC by a method wherein the lowermost dielectric layer is a silicon oxide film by plasma VD method and the uppermost dielectric layer is a silicon oxide film by low temperature CVD method in an MIM capacitor on a GaAs substrate. CONSTITUTION:An insulation film 2, a lower conductive layer 3, a dielectric layer 4 and an upper conductive layer 5 are formed on a GaAs single crystal substrate 1. The lowermost dielectric layer 4a of these comprises a silicon oxide film by plasma CVD method, in intermediate dielectric layer 4b comprises a silicon nitride film by plasma CVD method, and the uppermost dielectric layer 4c comprises a silicon oxide film by low temperature CVD method at a temperature of approximately 400 deg.C. Thus peeling between a metallic film and the dielectric layer constituting the lower conductive layer can be prevented and also an MIM capacitor with high withstand voltage can be obtained. In addition since the intermediate dielectric layer is the silicon nitride film by plasma CVD method, a capacity value can be increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor technology, and more particularly to a technology which is particularly effective when applied to the structure of a capacitor in a compound semiconductor device, for example, a technology which is effectively applied to a bypass capacitor for a high frequency IC.

[0002]

2. Description of the Related Art Conventionally, in a high frequency IC, a capacitor having a relatively large capacity called a bypass capacitor is connected between power supply voltage terminals (between Vcc and ground) for the purpose of reducing power supply noise. By the way, in recent years, G has been used as a device that can operate at higher speed than silicon devices.
A super high frequency GaAs IC using an aAs substrate has been put into practical use. In this type of ultra-high frequency IC, conventionally, a discrete capacitor is used as the bypass capacitor and is connected to the outside of the package.

[0003]

In the ultra high frequency IC, when the bypass capacitor is connected to the outside of the package, noise is also generated on the wire connecting the IC chip and the package, and this slight noise is generated. Is IC
It has been clarified that there is a problem of degrading the characteristics of. Therefore, the inventors of the present invention have considered and considered a method of incorporating a bypass capacitor in the package to absorb the power source noise nearer the chip.

As a result, it has been found that in an ultra high frequency IC, the device characteristics can be improved by using a capacitor having a MIM (metal insulator metal) structure using a GaAs substrate to remove high frequency noise. However, when the GaAs substrate is heated to 400 ° C. or higher, As is liberated, so that a stable dielectric film cannot be formed by an insulating film formed by a CVD method or an oxidation method at a high temperature. Therefore, conventionally, M on the GaAs substrate
In the IM capacitor, a silicon nitride film formed by the plasma CVD method was used as a dielectric.

However, the plasma CV is used as the dielectric.
The MIM capacitor using the silicon nitride film formed by the D method has a problem that it is easily broken when a voltage higher than the withstand voltage is applied, or even if the voltage is lower than the withstand voltage, if the voltage is continuously applied for a long time, the life is short. I understood.
In particular, when the chip size of the capacitor is reduced and the thickness of the dielectric film is reduced to increase the capacitance value in order to miniaturize the package, there is a problem that the withstand voltage is further reduced.

Regarding the MIM capacitor, "Design of integrated circuit", published by Modern Science Co., Ltd., March 1, 1970.
Pp. 39-42. An object of the present invention is a MIM suitable for a bypass capacitor of a high frequency IC, which has a small chip size, a large capacitance value, and a high breakdown voltage.
To provide capacitors. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, in an MIM capacitor in which an upper conductive layer is formed on a lower conductive layer formed on a compound semiconductor substrate such as GaAs via a plurality of dielectric layers,
The lowermost dielectric layer is a silicon oxide film (SiO) formed by the plasma CVD method, and the uppermost dielectric layer is 400 ° C.
Silicon oxide film (SiO ₂ ) by the following low temperature CVD method
It is what Further, if the thickness is the same as a whole, it is preferable to use a silicon nitride film by the plasma CVD method as the intermediate dielectric layer.

[0008]

When the surface of the metal film is oxidized, the insulating film on the surface of the metal film easily peels off. Therefore, in the MIM capacitor, if the lowermost dielectric layer is a silicon oxide film formed by the low temperature CVD method, a metal forming the conductive layer is formed. Although the film and the dielectric layer may be separated from each other, according to the above-mentioned means, since the lowermost dielectric layer is the silicon oxide film formed by the plasma CVD method, the metal film and the dielectric layer forming the conductive layer are formed. The silicon oxide film (SiO ₂ ) formed by the low-temperature CVD method, which can prevent the peeling of the silicon oxide film and the uppermost dielectric layer, has a higher breakdown voltage than the silicon nitride film formed by the plasma CVD method.
Therefore, a high withstand voltage MIM capacitor can be obtained. Moreover, since the silicon nitride film formed by the plasma CVD method is used as the intermediate dielectric layer, it is possible to increase the capacitance value. As a result, the bypass capacitor for a high frequency IC, which has a large capacitance value and a high breakdown voltage in a small chip size, is used. The above object of obtaining a MIM capacitor suitable for the above can be achieved. Although the uppermost dielectric layer is a silicon oxide film formed by the low temperature CVD method, since the metal film as the upper conductive layer is formed on this silicon oxide film, the surface of the metal film is oxidized and the dielectric layer is removed. It does not easily come off.

[0009]

FIG. 1 shows an embodiment of the MIM capacitor according to the present invention. In FIG. 1, 1 is GaAs
Single crystal substrate, 2 is an insulating film formed on the GaAs single crystal substrate 1, 3 is a metal film (for example, Mo / Au layer) as a lower conductive layer formed on the insulating film 2, and 4 is a metal film. Dielectric layers 5 formed on 3 are metal films (for example, Al layers) as upper conductive layers formed on the dielectric layer 4. In this embodiment, the dielectric layer 4 has a three-layer structure. Of these, the lowermost dielectric layer 4a is the plasma CV.
The silicon oxide film formed by the D method, the intermediate dielectric layer 4b formed by the silicon nitride film formed by the plasma CVD method, and the uppermost dielectric layer 4c formed by the low temperature CVD method at a temperature of about 400 ° C. Silicon oxide film (Si
O ₂ ).

Further, 6 is an interlayer insulating film for insulating between the lower conductive layer 3 and the upper conductive layer 5, and 7 is a passivation film for protection formed so as to cover the upper conductive layer 5. The lower conductive layer 3 and the upper conductive layer 5 are respectively extended to one side to form pad portions (not shown), and the passivation film 7 has an opening (corresponding to each pad portion). (Not shown) is formed.

2 and 3 show an example of the structure of an electronic device using the MIM capacitor 10 as a bypass capacitor. In the figure, reference numeral 21 is a ceramic chip carrier constituting the package 20, reference numeral 30 is an ultra high frequency IC chip such as high frequency power amplification GaAs FET, and the ultra high frequency IC chip 30 and the MIM capacitor 10 having the above-mentioned structure are connected to the ceramic chip carrier 21. Is brazed to the bottom of the storage recess 22. A signal line 41 and power lines 42 and 43 made of a tungsten layer or the like are provided in the ceramic chip carrier 21, and the power pad (Vcc pad) 32 on the super high frequency IC chip 30 and the MIM capacitor 10 are arranged. The pad 11 and the other pad 12 on the MIM capacitor 10 and the power supply line (ground line) 43 in the ceramic chip carrier 21 are connected by bonding wires 51 and 52, respectively.

Further, between the power supply pad (Vcc pad) 32 on the super high frequency IC chip 30 and the power supply line (Vcc line) 42 in the ceramic chip carrier 21, and the power supply pad (ground) on the super high frequency IC chip 30. (Pad) 33 and the power supply line (ground line) 43 in the ceramic chip carrier 21, and the input / output pad 31 on the super high frequency IC chip 30 and the signal line 41 in the ceramic chip carrier 21 are also bonded. It is connected by wires 53, 54 and 55. After the wire bonding is completed, Fe is placed on the storage recess 22 of the ceramic chip carrier 21.
The package 20 is completed by covering and sealing with a cap 23 made of an alloy of Ni and Ni.

FIG. 4 shows an upper embodiment of the invention. In this embodiment, an active element 60 such as a high frequency power amplification GaAs FET and the MI are provided on a GaAs single crystal substrate 1.
It is formed integrally with the M capacitor 10. MI
The M capacitor 10 has the same structure as that of the embodiment of FIG. 1, and the dielectric layer 4 has a three-layer structure. 61 is GaA
s Source and drain active regions formed on the surface of the single crystal substrate 1, 62a and 62b are ohmic electrodes formed on the surface of the source and drain regions 61, 63a,
63b is a source / drain electrode, and 64 is a Schottky gate electrode.

In this embodiment, the source / drain electrodes 63a and 63b of the FET (60) and the lower conductive layer 3 of the MIM capacitor 10 are formed in the same step and connected to the source / drain electrodes 63a and 63b. The signal line (not shown) and the upper conductive layer 5 of the MIM capacitor 10 are formed in the same process. This simplifies the process compared to the lower embodiment. In addition, since they are formed on the same substrate, the entire device can be downsized.
Although the dielectric layer 4 has a three-layer structure in the above embodiment, the silicon nitride film 4 formed by the intermediate plasma CVD method is used.
b may be omitted. However, if the entire dielectric layer 4 has the same thickness, a three-layer structure having a silicon nitride film 4b formed by the plasma CVD method in the middle has a larger capacitance value than two layers, which is desirable.

As described above, in the above embodiment, Ga
An upper conductive layer is formed on a lower conductive layer formed on a compound semiconductor substrate such as As via a plurality of dielectric layers M
In the IM capacitor, the lowermost dielectric layer is the silicon oxide film (SiO) formed by the plasma CVD method, and the uppermost dielectric layer is the silicon oxide film (SiO ₂ ) formed by the low temperature CVD method at 400 ° C. or less. The metal film forming the lower conductive layer can be prevented from peeling off from the dielectric layer, and the uppermost dielectric layer has a silicon oxide film formed by the low temperature CVD method, so that a high withstand voltage MIM capacitor can be obtained. There is an effect.

Plasma CVD as an intermediate dielectric layer
Since the silicon nitride film formed by the method is used, the capacitance value can be increased as compared with the case where other materials are used if the entire dielectric layer has the same thickness.
There is an effect that it is possible to manufacture an MIM capacitor suitable for a bypass capacitor of a high frequency IC, which has a small chip size, a large capacitance value, and a high breakdown voltage.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the number of dielectric layers 4 may be four or more. Further, although the MIM capacitor on the GaAs substrate has been described in the above embodiment, the present invention can be applied to the case where the capacitor is formed on a compound semiconductor single crystal substrate or a silicon substrate other than the GaAs substrate. In the above description, the case where the invention made by the present inventor is mainly applied to a bypass capacitor for a high-frequency IC which is a field of use as the background has been described, but the present invention is not limited thereto and a capacitor is used. It can be generally used for semiconductor devices provided with.

[0018]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, it is possible to obtain an MIM capacitor having a small chip size, a large capacitance value, and a high breakdown voltage, which is suitable for a bypass capacitor of a high frequency IC.

[Brief description of drawings]

FIG. 1 is a sectional front view showing an embodiment of an MIM capacitor according to the present invention.

2 is a sectional front view showing an embodiment of a semiconductor device incorporating the MIM capacitor of FIG.

3 is a plan view of the semiconductor device of FIG. 2 with a cap removed.

FIG. 4 is a sectional front view showing another embodiment of the MIM capacitor according to the present invention.

[Explanation of symbols]

1 GaAs substrate 3 Lower conductive layer (metal film) 4 Dielectric layer 4a Silicon oxide by plasma CVD method 4b Silicon nitride film formed by plasma CVD method 4c Silicon oxide film by low temperature CVD method 5 Upper conductive layer (metal film)

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Norio Nakazato             2326 Imai, Ome-shi, Tokyo Hitachi, Ltd.             In Manufacturing Device Development Center (72) Inventor Katsushi Oshika             2326 Imai, Ome-shi, Tokyo Hitachi, Ltd.             In Manufacturing Device Development Center

Claims (3)

[Claims] 1. A semiconductor device in which an upper conductive layer is formed on a lower conductive layer formed on a compound semiconductor substrate via a plurality of dielectric layers, the lowermost dielectric layer having the above-mentioned multilayer structure. A semiconductor device, wherein the side dielectric layer is a silicon oxide film formed by a plasma CVD method, and the uppermost dielectric layer is a silicon oxide film formed by a low temperature CVD method. 2. The semiconductor device according to claim 1, wherein when the dielectric layer has a three-layer structure, a silicon nitride film formed by a plasma CVD method is used as the intermediate dielectric layer. 3. A capacitive element having an upper conductive layer formed on a lower conductive layer formed on a compound semiconductor substrate via a plurality of dielectric layers, and an active element on the same compound semiconductor substrate. The semiconductor device according to claim 1, wherein the semiconductor device is formed.