JP2001102529A - Capacity element of mim structure and semiconductor integrated circuit device having the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To raise a capacity value (capacitance density) of the capacitive element of MIM structure which is provided per a unit area, when it is formed on a semiconductor substrate, and to reduce the size of a semiconductor integrated circuit device comprising the capacitive element of MIM structure. SOLUTION: On a semiconductor substrate, a first metal film, first insulating film, second metal film, second insulating film, and third metal film are laminated sequentially, with the first and third metal films electrically connected together. A first capacitor comprising the first metal film, first insulating film, and second metal film, and a second capacitor comprising the second metal film, second insulating film, and third metal film are connected in parallel. A capacitor intrinsic part which functions as a capacitance of the second capacitor is provided inside the capacitor intrinsic part which functions as capacitance of the first capacitor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an M layer formed by sequentially laminating a metal film, an insulating film and a metal film on a semiconductor substrate.
The present invention relates to a semiconductor integrated circuit device having a capacitance element having an IM (Metal-Insulator-Metal) structure, and more particularly to a technique which is effective when applied to miniaturization of the semiconductor integrated circuit device.

[0002]

2. Description of the Related Art Conventionally, in order to reduce the size and cost of portable terminals represented by portable telephones, transistors, inductors,
Capacitive elements, resistive elements, etc. are replaced by one gallium arsenide (GaAs).
s) A monolithic microwave integrated circuit (Monolithic Microwave IC, hereinafter referred to as MMIC) formed on a chip is used.

The capacitive elements formed in the MMIC include:
For example, a lower electrode is formed of an aluminum (Al) film or the like on a semiconductor substrate such as GaAs, and a capacitive insulating film such as a silicon nitride film or a silicon oxide film formed by a CVD (Chemical Vapor Deposition) method on the lower electrode. A so-called MIM structure in which a film and a metal film upper electrode are stacked. Hereinafter, the capacitance element having the MIM structure is referred to as an MIM capacitance.

The MIM capacitor is used, for example, as a bypass capacitor for smoothing a power supply voltage and preventing deterioration of a noise figure in a receiving circuit of a mobile phone (Tadayoshi Nakatsuka, “Low-noise GaAs IC for mobile phone”, application). Physics, Vol. 67, No. 4, 462-466, 1998
reference).

The relative dielectric constant of the capacitor insulating film used in the MIM capacitor is about 4.5 for a silicon oxide film, about 7 to 8 for a silicon nitride film, and about 500 to 2,000 angstroms. The capacitance value per unit area when formed on the GaAs substrate (hereinafter referred to as capacitance density) is 100 pF /
mm ^{2 to} about 400 pF / mm ² . Since the capacity density of the MIM capacitor is low, the area occupied by the MIM capacitor on a chip such as the MMIC is large. For example, in an MMIC used for a reception system circuit of a mobile phone, the area occupied by the MIM capacitor occupies 30% to 50% of the area of the circuit forming surface of the chip.

[0006] Therefore, in order to reduce the size of the MMIC, the capacity density of the MIM capacitor is increased to increase the MIM capacity.
It is most efficient to reduce the area for forming the capacitor.

[0007]

However, in the prior art, since the capacitance density of the MIM capacitor is low, the area for forming the MIM capacitor on a chip such as the MMIC must be increased. Therefore, there has been a problem that the chip size itself becomes large and the manufacturing cost (chip cost) increases.

[0008] In order to increase the capacitance density of the MIM capacitor, the thickness of the capacitor insulating film has been reduced. However, if the capacitor insulating film is too thin, dielectric breakdown occurs.
There is a problem that it is difficult to increase the capacity density of the capacity. Therefore, it is difficult to increase the capacitance density of the MIM capacitor to reduce the formation area of the MIM capacitor on a chip such as the MMIC, and it is difficult to reduce the chip size of the MMIC having the MIM capacitor. there were.

An object of the present invention is to provide a technique capable of reducing the size of a semiconductor device having a MIM structure capacitive element.

Another object of the present invention is to provide a technique capable of improving a capacitance value (capacity density) per unit area of a MIM-structured capacitor when formed on a semiconductor substrate. is there.

Another object of the present invention is to provide a technique capable of reducing the size of a semiconductor device having a MIM-structured capacitive element and reducing the manufacturing cost of the semiconductor device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A first metal film and a first metal film are formed on a semiconductor substrate.
An insulating film, a second metal film, a second insulating film, and a third metal film are sequentially laminated, and the first metal film and the third metal film are electrically connected to each other, and the first metal film, the first insulating film, A first capacitor formed of a film and a second metal film and a second capacitor formed of the second metal film, the second insulating film, and the third metal film are connected in parallel. The functioning capacity intrinsic part is
This is a capacitive element having an MIM structure provided inside a capacitive intrinsic portion functioning as the first capacitive capacitor.

(2) On the semiconductor substrate, n layers (n is an integer of 3 or more) of a first metal film to an n-th metal film are provided between the respective metal films. The first metal film to the n-th metal film are stacked with an n-1 insulating film interposed therebetween, and a second m-1 metal film (m is 1 to (n + 1) / 2
Are electrically connected to each other, the second m-th metal films are electrically connected to each other, and the k-th metal film (k is 2
To an integer from n to 1), and the capacitance intrinsic portion functioning as the capacitance of the k-th capacitor formed by the k-th insulating film and the (k + 1) -th metal film on the k-th metal film is the k-th metal film. A (k-1) th metal film, a k-1st insulating film provided below
This is a capacitive element having an MIM structure provided inside a capacitive intrinsic portion functioning as a (k-1) -th capacitor configured by a k-th metal film.

(3) A semiconductor integrated circuit device having a MIM structure capacitor, wherein the MIM structure capacitor is formed on a semiconductor substrate by a first metal film, a first insulating film, a second metal film, and a second metal film. The first metal film and the third metal film are electrically connected to each other, and are formed by the first metal film, the first insulating film, and the second metal film. And a second capacitor formed of the second metal film, the second insulating film, and the third metal film is connected in parallel.

(4) A semiconductor integrated circuit device having a MIM structure capacitor, wherein the MIM structure capacitor is formed on a semiconductor substrate by a first metal film, a first insulating film, a second metal film, A second insulating film and a third metal film, which are sequentially stacked, and a capacitance intrinsic portion functioning as a second capacitance of the second metal film, the second insulating film, and the third metal film is provided in the first insulating film. The capacitor is provided inside a capacitance intrinsic portion that functions as a capacitance of a first capacitor composed of a metal film, a first insulating film, and a second metal film.

(5) A semiconductor integrated circuit device having a MIM structure capacitive element, wherein the MIM structure capacitive element is formed on a semiconductor substrate by a first metal film, a first insulating film, a second metal film, and a second metal film. The first metal film and the third metal film are electrically connected to each other, and are formed by the first metal film, the first insulating film, and the second metal film. A first capacitor and a second capacitor formed of the second metal film, the second insulating film, and the third metal film are connected in parallel, and the capacitor intrinsic portion functioning as a capacitor of the second capacitor is formed by the second capacitor. It is provided inside the intrinsic capacitance part that functions as a capacitance of one capacitance.

(6) In the semiconductor integrated circuit device having the capacitance element having the MIM structure according to any one of the means (3) to (5), the first metal film and the third metal film are electrically connected to each other through a through hole. The electrical connection via the through hole is made by a metal attached to the through hole when the second metal film is formed.

(7) In a semiconductor integrated circuit device having a MIM-structured capacitor, the MIM-structured capacitor has an n-layer (n is an integer of 3 or more) first to n-th metal film. Are stacked between the respective metal films with n-1 layers of first to n-1th insulating films interposed therebetween.
Among the metal films to the n-th metal films, 2m-1 metal films (m is an integer from 1 to (n + 1) / 2) are electrically connected to each other, and 2m metal films are electrically connected to each other. And the k-th metal film (k is an integer from 2 to n−1), the k-th capacitance insulating film on the k-th metal film, and the k-th capacitance formed by the (k + 1) -th metal film. A functioning capacitive intrinsic portion is a k-th metal layer provided below the k-th metal film.
The first metal film, the (k-1) th capacitance insulating film, and the k-1th metal film are provided inside a capacitance intrinsic portion functioning as a capacitance of the (k-1) th capacitance.

(8) In the semiconductor integrated circuit device having the MIM structure of the means (7), the second m
-1 metal films and the 2m-th metal film are electrically connected to each other through through holes.
The electrical connection between the metal films is made by a metal attached to the through hole when the second m-th metal film is formed,
The electrical connection between the second metal films is made by a metal attached to the through hole when the 2m-1 metal film is formed.

(9) In the semiconductor integrated circuit device having the MIM structure capacitive element according to any one of the means (3) to (8), at least one of the odd-numbered and even-numbered metal films of the MIM structure capacitive element In addition, the metal wiring connecting the electrodes of other elements formed on the semiconductor substrate has a part of the metal film extended.

(10) In the semiconductor integrated circuit device according to the means (9), the metal wiring is formed by electrically connecting the other one of the odd-numbered or even-numbered metal films to the one to which the metal wiring belongs. Exists in the through hole that connects to the

(11) In the semiconductor integrated circuit device having the capacitance element having the MIM structure according to any one of the means (3) to (8), a metal film provided on an uppermost layer of the capacitance element having the MIM structure; A metal wiring provided on the film with a protective insulating film interposed is connected through an opening formed in the protective insulating film on the metal film.

(12) In the semiconductor integrated circuit device having the MIM structure capacitive element according to any one of the means (3) to (11), the metal film provided on the uppermost layer of the MIM structure capacitive element is gold ( Au) film.

(13) The means (11) or (12)
In the semiconductor integrated circuit device having the MIM structure capacitive element, the protective insulating film includes a silicon nitride film.

(14) In the semiconductor integrated circuit device having the MIM structure capacitive element according to any one of the means (3) to (13), at least one of the metal films stacked with the insulating film interposed therebetween. The outer periphery of the metal film of one layer does not intersect in plan with the outer periphery of the metal film via the insulating film below the metal film.

(15) In the semiconductor integrated circuit device having the capacitance element having the MIM structure according to any one of the means (3) to (14), the first metal film is a stack including a metal film containing gold (Au). A first film on the first metal film;
The interface with the insulating film is a metal film containing titanium (Ti).

(16) In the semiconductor integrated circuit device having the capacitance element having the MIM structure according to the means (15), the metal film containing titanium (Ti) is a titanium (Ti) film, a titanium nitride (TiN) film, or One of the compound films of titanium and tungsten (W).

(17) In the semiconductor integrated circuit device having the capacitance element having the MIM structure of the means (15), the first metal film containing the gold (Au) and the metal film containing the titanium (Ti) A molybdenum (Mo) film or a platinum (Pt) film is interposed therebetween.

Hereinafter, the present invention will be described in detail along with embodiments (examples) with reference to the drawings.

In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and their repeated explanation is omitted.

[0033]

(Embodiment 1) FIGS. 1 and 2 are a plan view and a schematic cross-sectional view, respectively, showing a schematic configuration of a semiconductor device having a MIM structure capacitive element according to Embodiment 1 of the present invention. 1 is a plan view of a capacitance element having an MIM structure mounted on a semiconductor device, and FIG. 2 is a cross-sectional view taken along line AA 'of FIG. Note that, in the plan view of FIG.
A schematic configuration of a portion (referred to as an MIM capacitor) is omitted from illustration of a surface protection film formed on the surface of the semiconductor device.

1 and 2, reference numeral 1 denotes a GaAs substrate, 2 denotes an insulating film, 3 denotes a first electrode of a MIM capacitor, 3A denotes a wiring connection portion of the first electrode 3, 4 denotes a first interlayer insulating film, and 5 denotes a first interlayer insulating film. First
A capacitance insulating film, 6 is a second electrode of a MIM capacitor, 7 is a lead, 8 is a second interlayer insulating film, 9 is a second capacitor insulating film, 10 is a third electrode of a MIM capacitor, 11 is a first protective film, 12 is the first
Metal wiring, 13 a second metal wiring, 14 a surface protective film, C
O1 is the first capacitor opening, CO2 is the second capacitor opening, TH
1 is a first through hole, TH2 is a second through hole, T
H3 is a third through hole, and TH4 is a fourth through hole. In FIG. 1, the first through hole TH1 and the third through hole TH3 overlap, and the outer periphery of the first metal wiring 12 and a part of the outer periphery of the first electrode 3 overlap.

The MIM capacity of the first embodiment is shown in FIGS.
As shown in FIG. 1, on a GaAs substrate 1 on which transistors and inductors (not shown) are formed, a first electrode 3 made of a metal film, a first capacitance insulating film 5 made of an insulating film, and a second electrode 6 made of a metal film , A second capacitor insulating film 9 made of an insulating film, and a third electrode 10 made of a metal film are laminated, and a first capacitor formed by the first electrode 3, the first capacitor insulating film 5, and the second electrode is formed. , The second capacitance constituted by the second electrode 6, the second capacitance insulating film 9, and the third electrode 10 is the Ga
It has a two-stage configuration laminated on an As substrate. In the first embodiment, for example, a stacked film of a molybdenum (Mo) film and an aluminum (Al) film is used as the first electrode 3, and molybdenum (Mo) is used as the second electrode 6 and the third electrode 10.
A stacked film of a film, a gold (Au) film, and a molybdenum (Mo) film, and a stacked film of a silicon oxide film and a silicon nitride film are used as the first capacitance insulating film 5 and the second capacitance insulating film 9. The first
The capacitor insulating film 5 and the second capacitor insulating film 9 may be a silicon oxide film, a silicon nitride film, a stacked film of a silicon oxide film, or the like.

The first capacitor of the MIM capacitor is the GaAs capacitor.
a first electrode 3 formed on an s substrate 1 and the first electrode 3
The first capacitor opening CO of the first interlayer insulating film 4 formed thereon
1 and the first capacitor insulating film 5 formed around
It is composed of electrodes 6. The second capacitor includes the second electrode 6, the second capacitor opening CO2 of the second interlayer insulating film 8 formed on the second electrode 6, and the second capacitor insulating film 9 formed around the second capacitor opening CO2. It is constituted by the third electrode 10. In the first capacitance and the second capacitance, a region that actually functions as a capacitance (hereinafter, referred to as a capacitance intrinsic portion) is:
This is only inside the capacitor opening of each interlayer insulating film.

The second capacitor opening C of the second interlayer insulating film 8
As shown in FIG. 1, O2 is smaller than the first capacitor opening CO1 of the first interlayer insulating film 4 and is formed inside the first capacitor opening CO1. That is, the second
The capacitance intrinsic part of the capacitor is smaller than the capacitance intrinsic part of the first capacitance and is formed inside the capacitance intrinsic part of the first capacitance.

A second through hole TH2 is opened in the first protective film 11 formed on the third electrode 10.
A first metal wiring 12 for connecting the third electrode 10 to elements such as transistors and inductors formed on the GaAs substrate 1 is formed. As shown in FIG. 1, the second through hole TH2 is formed in the second capacitor opening C.
It is smaller than O2 and formed inside the second capacitor opening CO2.

The first electrode 3 has a wiring connection portion 3A drawn out at a position not overlapping with the second electrode 6 and the third electrode 10, and the wiring connection portion 3A of the first electrode 3 First through hole TH1 opening first interlayer insulating film 4
Are drawn out onto the first interlayer insulating film 4 by the lead lines 7 formed in the first step. The lead line 7 is connected to the first metal wiring 12 via a third through hole TH3 opening the second interlayer insulating film 8 and the first protective film 11 on the lead line 7.

On the other hand, the second electrode 6 is connected to the first electrode 3
The wiring connection portion 3A and the wiring connection portion 6A drawn out at a position not overlapping with the third electrode 10, the second interlayer insulating film 8 and the first protection film 11 on the wiring connection portion 6A of the second electrode.
Through the fourth through hole TH4 opening the first through hole.
It is connected to the second metal wiring 13 formed on the protective film.
The second metal wiring 13 is a transistor, an inductor, or the like formed on the GaAs substrate 1, and when connected by the first metal wiring 12, an element is connected to a different element. That is, the first capacitance and the second capacitance stacked on the GaAs substrate 1 are connected in parallel between the first metal wiring 12 and the second metal wiring 13.

A second protective film (surface protective film) 14 is formed on the surface of the GaAs substrate 1 on which the MIM capacitor is formed, to protect other elements including the MIM capacitor and metal wiring.

FIGS. 3 to 5 are plan views showing the steps of manufacturing the capacitance element having the MIM structure according to the first embodiment.

Hereinafter, a method of manufacturing the MIM capacitor according to the first embodiment will be briefly described with reference to FIGS. Although elements such as transistors and resistors are also formed in the semiconductor device having the MIM capacitor according to the first embodiment, a method for manufacturing them is omitted. The configuration of the cross section of FIGS. 3 to 5 is referred to the schematic cross-sectional view of FIG.

First, an insulating film 2 is formed on a GaAs substrate 1 on which elements such as transistors and resistors are formed, and then, as shown in FIG.
A first electrode 3 provided with A is formed. The first electrode 3
In order to improve the adhesiveness with the GaAs substrate 1,
A molybdenum (Mo) film and an aluminum (Al) film are sequentially laminated. The insulating film 2 is made of, for example, a silicon oxide film having a thickness of about 0.5 μm by CVD (Chemical
It is formed by a vapor deposition method. The insulating film 2 is made of a PSG (Phospho Silicon) containing phosphorus (P).
e Grass) It may be a film.

Next, as shown in FIG. 4, a first interlayer insulating film 4 is formed, and the first interlayer insulating film 4 is formed by etching.
A first capacitor opening CO1 on the first electrode 3 and a first through hole TH1 on the wiring connection portion 3A of the first electrode 3.
Is formed, a first capacitance insulating film 5 made of a silicon nitride film and a silicon oxide film is formed around the first capacitance opening CO1 and the periphery thereof, and then the second electrode 6 having a wiring connection portion 6A and the first through hole are formed. A lead line 7 in the hole TH1 is formed. At this time, the wiring connection portion 6A of the second electrode 6 is formed at a position that does not overlap with the wiring connection portion 3A of the first electrode 3, as shown in FIG.

As the first interlayer insulating film 4, for example, a PSG film having a thickness of about 0.8 μm is formed by a CVD method.
Further, the first interlayer insulating film 4 may be a silicon oxide film. The first capacitor insulating film 5 is formed by sequentially stacking a silicon oxide film and a silicon nitride film by a PCVD (Plasma CVD) method, and then etching. The second electrode 6 and the lead wire 7 are made of, for example, a Mo film, an Au film, a Mo film.
After sequentially stacking the films, they are simultaneously etched to form a desired pattern.

Next, as shown in FIG. 5, a second interlayer insulating film 8 is formed on the entire surface, and a second capacitor opening CO2 on the second electrode 6 is formed in the second interlayer insulating film 8 by etching. After the opening, the second capacitor insulating film 9 is formed on the second capacitor opening CO2 and the periphery thereof, and then the third electrode 10 is formed. The second capacitor opening CO2 is smaller than the first capacitor opening CO1 formed in the first interlayer insulating film 4, and
It is formed inside the capacitor opening CO1. That is, the second electrode 6, the second capacitor insulating film in the second capacitor opening CO2,
The capacitance intrinsic portion of the second capacitance constituted by the third electrode is the capacitance of the first capacitance constituted by the first electrode 3, the first capacitance insulating film 5, and the second electrode 6 in the first capacitance opening CO1. It is formed inside the intrinsic portion.

As the second interlayer insulating film 8, for example, a PSG film having a thickness of about 0.5 μm is formed by a CVD method.
Further, the second interlayer insulating film 8 may be a silicon oxide film. The second capacitor insulating film 9 is a stacked film of a silicon oxide film and a silicon nitride film, and is formed by sequentially stacking by PCVD and then etching. The third electrode 10 includes:
For example, a Mo film, an Au film, and a Mo film are sequentially stacked and then formed by etching.

At this time, the outer periphery of the third electrode 10
The second electrode 6 is formed such that it does not intersect with the outer peripheral portion of the second electrode 6, particularly the outer peripheral portion of the wiring connection portion 6 </ b> A of the second electrode 6.

Next, after forming the first protective film 11 on the entire surface, the second through hole TH2 for wiring connection on the third electrode 10 and the third
Through hole TH3, wiring connection portion 6A of second electrode 6
After forming the upper fourth through hole TH4, the first metal connecting the third electrode 10 and the lead 7 drawn from the first electrode 3 to another element formed on the GaAs substrate 1 The wiring 12, the second electrode 6, and the G
a second element for connecting another element formed on the aAs substrate 1
The metal wiring 13 is formed. The first protective film 11 is formed of a silicon nitride film having high moisture resistance. The first metal wiring 12 and the second metal wiring 13 are made of, for example, a Mo film, Au
After the films are sequentially stacked, they are formed by etching.

FIG. 6 is a diagram for explaining the function and effect of the capacitance element having the MIM structure of the first embodiment, where X is the intersection between the outer periphery of the third electrode 10 and the second electrode 6.

As shown in FIG. 6, when the third electrode 10 is formed, a planar intersection X is formed between the outer periphery of the third electrode 10 and the outer periphery near the wiring connection portion 6A of the second electrode 6. If possible, there is a possibility that short-circuit failure between the second electrode 6 and the third electrode 10 may occur due to the remaining etch that occurs at the step on the side surface of the second electrode 6. That is, the fourth electrode formed on the wiring connection portion 6A of the second electrode 6 in a later step.
When the through hole TH4 is displaced from the wiring connection portion 6A due to misalignment as shown in FIG.
The metal wiring 13 and the third electrode 10 are short-circuited. As a result, the second electrode 6 and the third electrode 10 are short-circuited.
Therefore, as shown in FIG. 5, the outer peripheral portion of the third electrode 10 does not cross the outer peripheral portion of the second electrode 6.

Finally, a surface protection film 14 having a thickness of about 2 μm is formed of a polyimide resin or the like.

In accordance with the above procedure, the first capacitor composed of the first electrode 3, the first capacitor insulating film 5, and the second electrode 6, and the second capacitor
The second capacitor including the electrode 6, the second capacitor insulating film 9, and the third electrode 10 is laminated on the GaAs substrate 1, and the first electrode 3 and the third electrode 10 are connected to the first through hole TH1 and the third
Electrically connected through a through hole TH3,
The electrode 3 and the third electrode 10 are connected to another element formed on the GaAs substrate 1 by a first metal wiring 12, and the second electrode 6 is connected to the first metal wiring 12 by a second metal wiring 13. By connecting to a different element, the first capacitance and the second capacitance are connected in parallel. At this time, the first capacitance and the second capacitance correspond to the GaAs substrate 1.
The GaAs of the MIM capacity
The capacitance value (capacity density) obtained per unit area when formed on the s substrate 1 can be increased.

In the MIM capacitor of the first embodiment, for example, the capacitance density of the first capacitor is 200 pF / mm ² , the capacitance density of the second capacitor is 350 pF / mm ² , and the first capacitor and the second capacitor are GaAs. By laminating on the substrate 1, it can be used as an MIM capacitor having a capacitance density of 550 pF / mm ² .

Here, the reason why the capacitance density of the first capacitance is lower than the capacitance density of the second capacitance is that an Al film is used for the first electrode 3 of the first capacitance. This is because the first capacitor insulating film 5 must have a thickness of 200 nm or more in order to prevent a reduction in the breakdown voltage of the capacitor due to a projection (hillock) generated in the step.

The second capacitor opening CO2 of the second interlayer insulating film 8 is smaller than the first capacitor opening CO1 of the first interlayer insulating film 4 and is located inside the first capacitor opening CO1. By forming the capacitor, the capacitance intrinsic portion of the second capacitor formed in the upper layer can be formed flat. Therefore, the quality and thickness of the second capacitor insulating film 9 can be made uniform, and the breakdown voltage and reliability of the MIM capacitor can be improved.

Further, the third electrode 10 is formed of a laminated film including an Au film having high corrosion resistance, and the second electrode 10 formed on the first protection film 11 having high moisture resistance on the third electrode 10 is formed. Since the third electrode 10 and the first metal wiring 12 are connected through the through hole TH2, the progress of corrosion from the first metal wiring 12 due to intrusion of moisture from the outside, etc.
The MIM can be blocked on the third electrode 10.
It is possible to prevent a decrease in the reliability of the capacity. The third electrode 10 may be a laminated film including a corrosion-resistant metal film other than the Au film.

FIG. 7 is a schematic cross-sectional view showing a modification of the MIM structure capacitive element according to the first embodiment, and corresponds to the cross-sectional view shown in FIG.

In the MIM capacitor according to the first embodiment, as shown in FIG.
2, the third electrode 10 is extended to a position above the third through hole TH3, as shown in FIG.
Instead of the first metal wiring 12, the third electrode 10 can be connected to the lead 7 from the first electrode 3.

In this case, since it is not necessary to provide the second through hole TH2 on the third electrode 10, the first protective film 11 formed on the third electrode 10 is not opened. The first protective film 11 is formed of a laminated film including a silicon nitride film, and covers the entire surface of the large-area third electrode 10. Therefore, unless the stress of the silicon nitride film is suppressed, the first protective film 11 is formed. 11 becomes easy to peel off from the third electrode 10. When the upper layer of the third electrode 10 is a Mo film as in the first embodiment, the adhesion with the first protective film 11 is not always good due to oxidation or the like in the manufacturing process of the Mo film.

Since the stress of the silicon nitride film formed by the plasma CVD method is relatively higher than that of a silicon oxide film or the like, the silicon nitride film, that is, the first protective film 11 is formed above the third electrode 10. For example, a method of suppressing the thickness of the silicon nitride film is required because the film is easily peeled.

On the other hand, the MI having the configuration as shown in FIG.
In the case of M capacitance, the first protective film 11 on the third electrode 10 is removed by opening the second through hole TH2, so that the first protective film 11 is easily peeled off from the third electrode 10. The problem has also been solved.

Further, the MI having the configuration as shown in FIG.
In the case of the M capacitor, a first metal wiring 12 connected to the third electrode 10 is provided, and the first electrode 3 is connected to a third through hole TH3.
After being connected to the lead line 7 from the other, it is connected to another element. As a wiring method for other elements, the third electrode 10 may be extended and connected instead of the first metal wiring 12, or a lead formed simultaneously with the second electrode 6 as shown in FIG. The connection may be made using a wiring portion 7A extended from the wire 7. Also, as shown in FIG. 7, when the third electrode 10 is connected to the lead 7 from the first electrode 3 instead of the first metal wiring 12, the third electrode 10 is extended. You may connect with another element. That is, if the first electrode 3 and the third electrode 10 are electrically connected,
Wiring to other elements may be performed by extending any electrode (metal film).

Similarly, the M shown in FIG.
In the IM capacity, the second electrode 6 is connected to the fourth through hole TH.
4, the wiring is connected to the second metal wiring 13 and is connected to another element. However, the present invention is not limited to this. As shown in FIG. It may be used as wiring.

As described above, since the degree of freedom of the wiring method from the MIM capacitor to other elements is high,
The area of the semiconductor integrated circuit device can be laid out small, for example, because it is not necessary to provide a separate through hole near other elements connected to the M capacitor.

By providing the first through hole TH1 and the third through hole TH3 on the wiring connection portion 3A of the first electrode 3, it is possible to prevent each through hole from becoming too deep. That is, the first through hole TH
1 and the third through hole TH3 are formed at one time, and the lead wire 7 is formed in the first through hole rather than connecting the first metal wire 12 and the first electrode 3. Is improved, and stable electrical connection can be achieved in manufacturing. In the MIM capacitors shown in FIGS. 1 and 2, the first through hole TH1 and the third through hole TH3 have the same layout shape. However, each shape is changed according to the ease of manufacturing process. Alternatively, they may be formed at different positions.

FIG. 8 is a schematic plan view showing a schematic configuration of a semiconductor integrated circuit device having the MIM structure capacitive element according to the first embodiment.

In FIG. 8, C1 and C2 are MI
M capacity, L1, L2, L3 are inductors, F
1 and F2 are field-effect transistors (FE
T), P1, P2, P3, P4, P5, and P6 are bonding pads, respectively, and W1 is a field effect transistor F
1 and a metal wiring connecting the electrode pad W1, W2, W3,
W4 is a metal wiring connected to the MIM capacitor. In addition,
In FIG. 8, metal wirings other than the metal wirings W1, W2, W3, and W4 and resistance elements are omitted.

As shown in FIG. 8, the semiconductor integrated circuit device equipped with the MIM capacitor according to the first embodiment is used, for example, in a receiving circuit such as a portable telephone to smooth the power supply voltage and prevent the noise figure from deteriorating. And two MIM capacitors, a first MIM capacitor C1 and a second MIM capacitor C2, used as a bypass capacitor or the like. For example, the first
The capacitance value of the MIM capacitance C1 is 40 pF, and the capacitance value of the MIM capacitance C2 is 8 pF. Since the capacitance density of the MIM capacitor of the first embodiment is, for example, 550 pF / mm ² , the first MIM capacitor C1 and the second
The formation area of the two MIM capacitors of the IM capacitor C2 is 0.08
7 mm ² .

The size of the GaAs substrate 1 (semiconductor device) is 0.67 mm in length, 0.67 mm in width and 0.4 area.
Since it is 49 mm ² , the MIM on the GaAs substrate 1
The area occupied by the capacitance is about 19% of the whole.

The conventional MIM capacitor has a capacitance value (capacity density) per unit area of about 200 pF / mm ² when formed on the GaAs substrate 1.
To form an MIM capacitor of 8 pF, 0.24 mm
^In the case where a semiconductor integrated circuit device having the same function as the semiconductor integrated circuit device equipped with the MIM capacitor of the first embodiment as shown in FIG. ^Two GaAs substrates 1 were required.
That is, by stacking the MIM capacitors connected in parallel on the GaAs substrate 1, the capacitance value (capacity density) obtained per unit area when formed on the GaAs substrate 1 is increased. Of the MIM capacitor can be reduced. Therefore, the GaAs substrate 1
(Semiconductor device) can be reduced in size.

In the case of a metal wiring layout along the outer periphery of the first MIM capacitor C1 as in the case of the metal wiring W1 shown in FIG. 8, the formation of the first MIM capacitor C1 on the GaAs substrate 1 is performed. By reducing the area, the wiring length of the metal wiring W1 can also be reduced. That is, by reducing the formation area of the MIM capacitor on the GaAs substrate, the metal wiring can be shortened, and the layout design of the metal wiring can be made more flexible.
It is easy to miniaturize semiconductor integrated circuit devices such as MIC,
In particular, this is effective in the case of a thick wiring having a thickness of 30 to 50 microns.

Further, in the semiconductor integrated circuit device shown in FIG. 8, the metal wiring W connected to the first MIM capacitor C1 is formed.
2, W3, and W4, the metal wiring W2 is formed of the same metal as the first electrode 3 of the first MIM capacitor C1.
A part of the IM capacitor C1 is extended and used as a metal wiring, and the metal wiring W1 is formed of the same metal as the first electrode 3. Thus, the metal wiring can be provided without separately providing a wiring bypassing the first MIM capacitor C1. The wiring W1 and the metal wiring W2 can be connected.

The metal wiring W4 is connected to the first metal wiring 12 of the MIM capacitor shown in FIG. The first metal wiring is a third electrode 1 of the first MIM capacitor C1.
0 and the first electrode 3 through the third through hole TH3 and the first through hole TH1 of the first MIM capacitor C1.
Is electrically connected to Therefore, the metal wiring W
4 is a metal wiring W without a separate through hole.
1, W2.

In FIG. 8, the reason why the first MIM capacitor C1 has a polygonal shape is actually a structure in which three small capacitors are connected in parallel. This is because the one-capacity opening CO1 is also a polygon having six or more corners. The third MIM capacitor C1 has a third
The first through-hole TH1 and the third through-hole TH3, which are the electrical connection between the electrode 10 and the first electrode 3, are provided only at one place. Each small-capacity second capacitor opening C
Three O2s are provided around the inside of the first capacitance opening CO1. That is, M shown in FIG. 1 and FIG.
In the case of the IM capacitor, the first capacitor opening C provided on the first electrode 3
O1 is one, but not limited to this, and the opening is the first
As long as it is inside the electrode 3, a plurality of electrodes may be provided.

Further, in addition to the layout design of the metal wiring, the degree of freedom in the layout design of elements such as the inductors L1, L2, L3 and the field effect transistors F1, F2 is increased. The degree of freedom is further improved, and an efficient wiring with a reduced wiring length of the metal wiring can be performed.

As described above, according to the first embodiment, by stacking two MIM capacitors connected in parallel on a semiconductor substrate, the capacitance obtained per unit area when formed on the semiconductor substrate is obtained. Value (capacity density) can be increased. Therefore, the M
The area for forming the IM capacitor can be reduced, and the size of the semiconductor integrated circuit device can be reduced.

The second capacitor opening CO of the MIM capacitor
2 is formed inside the first capacitance opening CO1 and a portion (capacitance communication portion) functioning as a capacitance of the second capacitance in the second capacitance opening CO2 becomes flat, The film quality and thickness of the second capacitance insulating film 9 in the intrinsic portion of the capacitance can be uniform, and the breakdown voltage and reliability of the MIM capacitor can be improved.

The third electrode 10 and the first metal wiring 1
2 are separately formed, and the first metal wiring 12 is
An o film and an Au film are sequentially laminated to form a two-layer film,
By forming the electrode 10 as a laminated film including an Au film, progress of the first metal wiring 12 from corrosion due to invasion of moisture or the like from the outside can be prevented on the third electrode 10. It is possible to prevent a decrease in the reliability of the capacity.

As described above, the area for forming the MIM capacitor on the semiconductor substrate is reduced to reduce the size of the semiconductor integrated circuit device, to prevent the reliability of the MIM capacitor from decreasing, and to improve the manufacturing yield. Therefore, the manufacturing cost of the semiconductor integrated circuit device can be reduced.

In the MIM capacitor according to the first embodiment, since the Al film is used for the first electrode 3, a decrease in the breakdown voltage of the first capacitor due to a projection (hillock) generated on the Al film is prevented. To prevent this, the thickness of the first capacitance insulating film 5 is increased. Therefore, the capacity density of the first capacity is lower than the capacity density of the second capacity. Instead of the Al film, a stacked film including an Au film and having a metal film including titanium (Ti) on the interface side with the first capacitance insulating film 5 may be used as the first electrode 3. By forming the first electrode 3 as a laminated film including the Au film, the generation of protrusions (hillocks) such as the Al film is eliminated, and the first capacitance insulating film 5 is thinned to reduce the capacitance of the first capacitance. Density can be increased. Further, by using a metal film containing Ti on the interface side of the first electrode 3 with the first capacitance insulating film 5, the adhesiveness between the first electrode 3 and the first capacitance insulating film 5 is improved, The production yield is improved. Titanium (T) formed at the interface with the first capacitance insulating film 5
Examples of the metal film containing i) include a simple Ti film, a titanium nitride (TiN) film, and a compound film of Ti and tungsten (W). At this time, the metal film containing Ti and A
A Mo film or a Pt film may be inserted between the u film and the u film.

In the MIM capacitor of the first embodiment, a laminated film of a silicon nitride film and a silicon oxide film is used as the first capacitance insulating film 5 and the second capacitance insulating film 9, but the present invention is not limited to this. The first capacitance insulating film 5 and the second capacitance insulating film 9
As strontium titanate (SrTiO ₂ ; ST
O) A film may be used. Further, as the first electrode 3 and the intermediate wiring 15, a four-layer film in which a titanium film, a gold film, a titanium film, and a platinum film are sequentially laminated, the second electrode 6 and the third electrode 10 are used.
By using a four-layer film in which a platinum film, a titanium film, a gold film, and a titanium film are sequentially laminated, it is possible to further increase the capacity density.

In the first embodiment, the first capacitor insulating film 5 or the second capacitor insulating film 9 is formed after the capacitor opening is formed in the first interlayer insulating film 4 or the second interlayer insulating film 8. However, the present invention is not limited to this, and the first capacitance insulating film 5 may be formed directly on the first electrode 3.

FIGS. 9 and 10 are diagrams showing a schematic configuration of a modification of the first embodiment. FIG. 9 is a plan view of a capacitance element having an MIM structure, and FIG. 10 is a view taken along a line BB 'in FIG. It is a schematic cross section.

9 and 10, 1 is a GaAs substrate, 2 is an insulating film, 3 is a first electrode, 3A is a wiring connection portion of the first electrode 3, 4 is a first interlayer insulating film, and 5 is a first capacitor. Insulating film,
6 is a second electrode, 7 is a lead wire, 9 is a second capacitance insulating film,
Reference numeral 10 denotes a third electrode, 11 denotes a first protective film, 12 denotes a first metal wiring, 13 denotes a second metal wiring, 14 denotes a second protective film (surface protective film), 15 denotes an intermediate wiring, and 15A denotes an intermediate wiring. The connection portion, TH1 is a first through hole, TH2 is a second through hole, TH3 is a third through hole, TH4 is a fourth through hole, and TH5 is a fifth through hole. Note that FIG.
In this case, the first through hole TH1 and the third through hole TH3 are overlapped, and the outer periphery of the first metal wiring 12 and the first through hole TH3 are overlapped.
It is assumed that the outer periphery of the electrode 3 also overlaps.

The MIM capacitor shown in FIGS. 9 and 10 has a first electrode 3 made of a metal film and a first capacitor made of an insulating film on a GaAs substrate 1 on which a transistor, an inductor and the like (not shown) are formed. An insulating film 5, a second electrode 6 made of a metal film, an intermediate wiring 15 made of a metal film, a second capacitance insulating film 9 made of an insulating film, and a third electrode 10 made of a metal film are stacked. A first capacitor composed of a one-capacitance insulating film 5 and a second electrode 6;
The intermediate wiring 15 connected through the fifth through hole TH5 formed in the interlayer insulating film 4, the second capacitance insulating film 9, the third
It has a two-stage configuration in which the second capacitors constituted by the electrodes 10 are stacked. In the second embodiment, the first electrode 3
Titanium (Ti) film, platinum (Pt) film, gold (Au) film, P
a five-layer film in which a t film and a Ti film are sequentially laminated,
The metal wiring is a molybdenum (Mo) film, an Au film, a Mo film,
It is assumed that the film is formed of a four-layer film in which TiW films are sequentially laminated. Further, the first capacitance insulating film 5 and the second capacitance insulating film 9 are made of a laminated film of a silicon nitride film and an acid or silicon film.

As in the first embodiment, the third electrode 10 of the second capacitor is connected to the first metal wiring 1 via the second through hole TH2 formed in the first protective film 11 on the third electrode.
2 is connected. Further, the first metal wiring 12 is
The first electrode 3 is also electrically connected to the first electrode 3 via a first through hole TH1 and a third through hole TH3 formed on the wiring connection portion 3A of the first electrode 3. Further, the intermediate wiring 15 connected to the second electrode 6 is provided with a wiring connection portion 15A drawn out to a position different from the wiring connection portion 3A of the first electrode 3; Is connected to the second metal wiring 13 via a fourth through hole TH4 formed on the wiring connection part 15A.

In the MIM capacitors shown in FIGS. 9 and 10,
A first capacitor insulating film 5 and a second electrode 6 are formed directly on the first electrode 3 without providing a capacitor opening in the interlayer insulating film, and a flat surface on an intermediate wiring 15 connected to the second electrode 6 is formed. The second capacitor insulating film 9 and the third electrode 10 are formed in a region where the first capacitor insulating film 5 and the second electrode 6 are formed as shown in FIG.
The whole becomes a portion (capacitance intrinsic portion) that functions as a capacitance of the first capacitance, and the entirety of the second capacitance insulating film 9 and the third electrode 10 functions as a capacitance of the second capacitance (capacitance intrinsic portion).
Becomes Also in this case, the capacitance intrinsic part of the second capacitance is smaller than the capacitance intrinsic part of the first capacitance, and
The capacitor is formed inside the intrinsic portion of the capacitor.

Hereinafter, a method of manufacturing the MIM capacitor shown in FIGS. 9 and 10 will be briefly described.

First, after an insulating film 2 is formed on a GaAs substrate 1 on which a transistor, an inductor, etc. are formed, a Ti film, a Pt film, and a Pt film are formed on the insulating film 2 by an ion milling method.
A first electrode 3 having a wiring connection portion 3A is formed by sequentially laminating a film, an Au film, a Pt film, and a Ti film. The first electrode 3 may be formed by a lift-off method instead of the ion milling method.

Next, a silicon nitride film is formed by the PCVD method,
After laminating a silicon oxide film and subsequently laminating a WSi film, patterning is performed to form a first capacitance insulating film 5 composed of the silicon oxide film and the silicon nitride film and a second electrode 6 composed of the WSi film.

Next, a first interlayer insulating film 4 is formed on the entire surface,
A fifth through hole TH5 on the second electrode 6 and a first through hole TH1 on the wiring connection portion 3A of the first electrode 3
Are formed, and a Mo film, an Au film, a Mo film, and a TiW film are sequentially laminated, and then patterned to form the intermediate wiring 15 having the wiring connection portion 15A and the lead line 7 of the first electrode 3. At this time, the wiring connection portion 15A of the intermediate wiring 15
Is drawn out to a position where it does not overlap with the wiring connection portion 3A of the first electrode 3.

Next, a silicon nitride film is formed by the PCVD method,
A silicon oxide film is laminated, followed by a Mo film, an Au film, and a Mo film.
After sequentially stacking the films, patterning is performed, and the second capacitor insulating film 9 and the second capacitor insulating film 9 each including the silicon oxide film and the silicon nitride film
A third electrode 10 made of an o film, an Au film, and a Mo film is formed. At this time, the second capacitance insulating film 9 and the third electrode 10
Is patterned inside the second electrode 6 and on the flat portion of the intermediate wiring 15.

Next, a first protective film 11 is formed on the entire surface, and the second through hole TH2 on the third electrode 10, the third through hole TH3 on the lead wire 7, and the wiring connection of the intermediate wiring 15 are formed. Fourth through hole TH4 on part 15A
Is formed, and a Mo film and an Au film are sequentially laminated and then patterned to form a first metal wiring 12 and a second metal wiring 13. The first metal wiring 12 is connected to the third electrode 10 via the second through hole TH2, and the lead wire 7 drawn from the first electrode 3 via the third through hole TH3. Connected to Also,
The second metal wiring 13 is connected to the fourth through hole TH4.
Is connected to the intermediate wiring 15. Therefore, the first and second capacitors connected in parallel between the first metal wiring 12 and the second metal wiring 13 are connected to the GaAs substrate 1.
And the MIM capacitor is connected to the Ga
The capacitance value (capacity density) obtained per unit area when formed on the As substrate 1 can be increased. Therefore, the area for forming the MIM capacitor can be reduced, and the size of the semiconductor integrated circuit device can be reduced.

Further, the first electrode 3 and the intermediate wiring 15
Does not include an aluminum (Al) film, no projections (hillocks) are generated on the respective surfaces, and both the first capacitance insulating film 5 and the second capacitance insulating film 9 can be reduced in thickness. Density can be increased. For example, it is possible to each of capacity density of the first capacitor and the second capacitor from about 300 pF / mm ² and 500 pF / mm ^2, obtained per unit area at the time of forming on the GaAs substrate 1 volume Value (capacity density) is about 60
An MIM capacity of 0 pF / mm ² to 1000 pF / mm ² can be obtained. Therefore, the formation area of the MIM capacitor can be further reduced, and the size of the semiconductor integrated circuit device can be reduced.

The first capacitance insulating film 5 of the first electrode 3
Since the metal film containing titanium (Ti) is formed at the interface between the first electrode 3 and the first capacitor insulating film 5 at the interface between the first electrode 3 and the first capacitor insulating film 5, respectively.
And the adhesiveness between the intermediate wiring 15 and the second capacitor insulating film 9 are improved, and the production yield is improved.

In the case of the first embodiment, the first interlayer insulating film 4 is formed first, a first capacitor opening CO1 is provided in the first interlayer insulating film 4, and the first capacitor insulating film is formed therein. 5, the first capacitance insulating film 5 runs over the first interlayer insulating film 4 at the outer peripheral portion of the first capacitance opening CO1, so that the capacitance intrinsic portion of the first capacitance is formed. There is a possibility that the film thickness becomes non-uniform near the outer periphery of the MIM and the reliability of the MIM capacitor is reduced. Therefore, as in the case of the MIM capacitor shown in FIGS. 9 and 10, by forming the first capacitance insulating film 5 and the second electrode 6 on the first electrode 3 first,
The film thickness can be made uniform even at the outer peripheral portion of the first capacitance insulating film 5, and the reliability of the MIM capacitor can be prevented from lowering.

(Embodiment 2) FIGS. 11 and 12 are a plan view and a schematic cross-sectional view, respectively, showing a schematic configuration of a semiconductor device having a MIM structure capacitive element according to Embodiment 2 of the present invention.
1 is a plan view, and FIG. 12 is a sectional view taken along line CC 'of FIG. Note that, in the plan view of FIG. 11, the insulating film laminated on the semiconductor substrate is omitted, and the configuration of the metal film serving as the electrode of the MIM capacitor and the configuration of the metal wiring are shown.

In FIGS. 11 and 12, CO1 is the first
A capacitor opening, CO2 is a second capacitor opening, CO3 is a third capacitor opening, TH1 is a first through hole, TH2 is a second through hole, TH6 is a sixth through hole, and TH7 is a seventh.
Through hole, TH8 is an eighth through hole, TH9 is a ninth through hole, 1 is a GaAs substrate, 2 is an insulating film, 3 is a first electrode, 3A is a wiring connection portion of the first electrode 3, 4 is a first interlayer insulation. A film, 5 is a first capacitance insulating film, 6 is a second electrode, 6A is a wiring connection portion of the second electrode 6, 7 is a first lead wire, 8 is a second interlayer insulating film, 9 is a second capacitance insulating film, 10 is a third electrode,
10A is a wiring connection portion of the third electrode 10, 11 is a first protective film, 12 is a first metal wiring, 13 is a second metal wiring, 14 is a second protective film (surface protective film), and 16 is a second lead wire. , 1
7 is a third interlayer insulating film, 18 is a third capacitance insulating film, and 19 is a fourth electrode. In FIG. 11, the first through hole TH
1, sixth through hole TH6, eighth through hole TH8
Are formed in the same position and are shown in an overlapping manner, and the seventh through-hole TH7 and the ninth through-hole TH9 are also shown in an overlapping manner.

As shown in FIGS. 11 and 12, the MIM capacitor according to the second embodiment has the first MIM capacitor formed on the GaAs substrate 1.
On the electrode 3, a first capacitance insulating film 5, a second electrode 6, a second capacitance insulating film 9, a third electrode 10, a third capacitance insulating film 18, and a fourth electrode 19 are sequentially laminated. Each of the first electrode 3, the second electrode 6, the third electrode 10, and the fourth electrode 19 is made of a metal film, and the first capacitance insulating film 5, the second capacitance insulating film 9,
Each of the third capacitance insulating films 18 is formed of an insulating film,
A first capacitor including the electrode 3, the first capacitor insulating film 5, and the second electrode 6, a second capacitor including the second electrode 6, the second capacitor insulating film 9, and the third electrode 10, a third capacitor 10, 3 capacitance insulating film 1
The third capacitance composed of the eighth and fourth electrodes 19 is a three-stage MIM capacitance laminated on the GaAs substrate 1. Example 2
Is basically the same as the two-stage MIM capacitor of the first embodiment, and a detailed description thereof will be omitted.

In the MIM capacitor according to the second embodiment, as shown in FIG. 11, the third capacitor opening CO3 is connected to the second capacitor opening CO3.
2 and the second capacitor opening CO2 is formed in the first
It is formed inside the capacitor opening CO1.

As shown in FIG. 12, the fourth electrode 19 is formed on the first protective film 1 formed on the fourth electrode 19.
The second electrode 6 is connected to the first metal wiring 12 through the second through hole TH2 opened to the first through hole 1, and the second lead 6 is drawn out by the seventh through hole TH7 formed on the wiring connection portion 6A. The line 16 is the second lead line 16
It is connected to the first metal wiring 12 via a ninth through hole TH9 formed above.

On the other hand, the first lead-out line 7 drawn out through the first through-hole TH1 on the wiring connection portion 3A of the first electrode 3 passes through the third through-hole TH6.
The third electrode 10 is connected to the second metal wiring 13 via an eighth through-hole TH8 formed on the wiring connection part 10A, while being connected to the wiring connection part 10A of the electrode 10. That is, the first capacitance, the second capacitance, and the third capacitance are connected in parallel, and are stacked on the GaAs substrate 1.

Like the MIM capacitor of the second embodiment, the first, second and third capacitors connected in parallel
By laminating on the As substrate 1, the capacitance value (capacity density) obtained per unit area when formed on the GaAs substrate 1 can be increased. Therefore, the area for forming the MIM capacitor can be reduced, and the semiconductor device can be downsized.

The capacitance intrinsic portion of the second capacitance is smaller than the capacitance intrinsic portion of the first capacitance and is formed inside the capacitance intrinsic portion of the first capacitance. The intrinsic portion is smaller than the capacitive intrinsic portion of the second capacitor,
And it is formed inside the capacitance intrinsic portion of the second capacitance. As a result, the capacitance intrinsic portion of each capacitor becomes flat, and the quality and thickness of the capacitance insulating film of each capacitor can be made uniform, so that the breakdown voltage and reliability of the capacitor are improved.

The first electrode 3 is a laminated film including an Au film, and a Ti film,
By forming a metal film containing titanium (Ti) such as a TiW film or a TiN film, a projection (hillock) like a conventional aluminum (Al) electrode is prevented from being generated, and the thickness of the first capacitance insulating film 5 is reduced. Can be reduced, so that the capacity density of the MIM capacitor can be increased. Therefore, the MIM
The formation area of the capacitor can be reduced, and the size of the semiconductor device can be reduced. At this time, a Mo film or a Pt film may be inserted between the metal film containing titanium (Ti) and the Au film.

Further, similarly to the first embodiment, the fourth electrode 19 formed on the uppermost layer and the first metal wiring 12 are separately formed, and the first metal wiring 12 is formed of a Mo film, Au.
The second electrode 19 is formed of a two-layer film in which films are sequentially stacked, and the fourth electrode 19 is a stacked film including an Au film. Blocking on the fourth electrode 19, the M
It is possible to prevent a decrease in the reliability of the IM capacity.

In the second embodiment, a three-stage MIM capacitor in which four metal films are stacked has been described.
However, the present invention is not limited to this. In general, in an MIM capacitor in which n layers of electrodes from the first electrode to the n-th electrode, where n is an integer of 3 or more, the second electrode among the first to n-th electrodes is
The m-1 electrodes (m is an integer from 1 to (n + 1) / 2) may be electrically connected to each other, and the second m may be electrically connected to each other. Here, when n is 3, the MIM capacitor has the configuration as described in the first embodiment, and the only electrode corresponding to the second m electrode is the second electrode. The electrical connection between the second m electrodes is satisfied.

In the case of the MIM capacitor in which the n layers of electrodes are stacked, the wiring connection portion of each electrode from the first electrode to the nth electrode sequentially stacked on the semiconductor substrate is connected to each of the 2m-1 electrodes. The 2m-
One electrode is electrically connected to each other through a through hole formed in an interlayer insulating film between the electrodes, and each electrode of the second m electrode is placed at a position not overlapping with a wiring connection portion of each electrode of the second m-1 electrode. So that the wiring connection portions of
The m-electrodes are electrically connected to each other through through holes formed in the interlayer insulating film between the electrodes, and the n-th electrode in the uppermost layer is connected to the through-hole provided in the first protective insulating film on the n-th electrode. The first metal wiring connected via the hole allows the n-th metal wiring
-2 electrode, and the n-1th electrode with the second metal wiring, thereby forming an MIM capacitor in which n-1 capacitors connected in parallel are stacked on the semiconductor substrate. The capacitance value (capacity density) obtained per unit area when formed can be increased. Therefore, the formation area of the MIM capacitor can be reduced, and the semiconductor device can be downsized.

The k-th electrode, the k-th capacitance insulating film, and the k +
The capacitance intrinsic portion of the k-th capacitor composed of one capacitor (k is an integer from 2 to n-1) is the k-1st electrode and k-1
By forming the capacitor insulating film and the capacitance intrinsic portion of the (k-1) th capacitance composed of the kth electrode and inside the capacitance intrinsic portion of the (k-1) th capacitance, the capacitance intrinsic portion of each capacitance becomes flat. Since the film quality and thickness of the capacitance insulating film can be made uniform in the capacitance intrinsic portion of each capacitance, the MIM
The breakdown voltage and reliability of the capacitor are improved.

The first electrode 3 is a laminated film including an Au film, and a Ti film,
By forming a metal film containing titanium (Ti) such as a TiW film or a TiN film, a projection (hillock) like a conventional aluminum (Al) electrode is prevented from being generated, and the thickness of the first capacitance insulating film 5 is reduced. Can be reduced, so that the capacity density of the MIM capacitor can be increased. Therefore, the MIM
The formation area of the capacitor can be reduced, and the size of the semiconductor device can be reduced. At this time, a Mo film or a Pt film may be inserted between the metal film containing titanium (Ti) and the Au film.

The uppermost n-th electrode and the first metal wiring are separately formed, the first metal wiring is formed of a two-layer film in which a Mo film and an Au film are sequentially laminated, and the n-th electrode is formed of Au. By forming a laminated film including a film, the progress of corrosion from the first metal wiring due to intrusion of moisture or the like from the outside can be prevented on the n-th electrode, and the reliability of the MIM capacitor decreases. Can be prevented.

(Embodiment 3) FIGS. 13 and 14 are diagrams showing a schematic configuration of a semiconductor device having a MIM-structured capacitive element according to Embodiment 3 of the present invention. FIG. 13 is a plan view, and FIG. FIG. 4 is a schematic sectional view taken along line DD ′ of FIG. FIG.
The plan view of No. 3 shows the capacitive element portion having the MIM structure of the third embodiment, omitting the surface protection film.

In FIGS. 13 and 14, 1 is GaAs.
Substrate, 2 is an insulating film, 20 is a lower electrode (first electrode), 21
Is an interlayer insulating film, 22 is a capacitive insulating film, 23 is an upper electrode (second electrode), 11 is a first protective film, 12 is a first metal wiring,
3 is a second metal wiring, 14 is a second protective film (surface protective film),
TH2 is a second through hole, TH10 is a tenth through hole, and TH11 is an eleventh through hole.

As shown in FIGS. 13 and 14, the MIM capacitor of the third embodiment has a lower electrode (first electrode) 20, a capacitor insulating film 22, and an upper electrode (second electrode) on a GaAs substrate 1.
23, which is the same as the conventional one-stage configuration in which
The upper electrode 23 is connected to another element on the GaAs substrate 1 by a first metal wiring 12 connected via a second through hole TH2 opening the first protective film 11 on the upper electrode 23, The lower electrode (first electrode) 20 is
A first opening formed in the interlayer insulating film 21 and the first protection film 11;
The second metal wiring 13 connected via one through hole TH11 connects to another element on the GaAs substrate 1.

Also in the MIM capacitor of the third embodiment, the upper electrode (second electrode) 23 and the first metal wiring 12 are separately formed, and the first metal wiring 12 is formed of a Mo film, Au.
The film is formed of a two-layer film in which films are sequentially laminated, and the upper electrode (second
By forming the electrode 23 as a laminated film including an Au film, progress of the first metal wiring 12 from corrosion due to intrusion of moisture or the like from the outside is prevented on the upper electrode (second electrode) 23. Therefore, it is possible to prevent the reliability of the MIM capacitor from decreasing.

The lower electrode (first electrode) 20 is
By forming a metal film containing titanium (Ti) such as a Ti film, a TiW film, and a TiN film at an interface with the capacitance insulating film 22 as a laminated film including an Au film, a conventional aluminum (Al) electrode is formed. Preventing the occurrence of such hillocks,
Since the thickness of the capacitor insulating film 22 can be reduced, the MI
When the M capacitor is formed on the GaAs substrate 1, a capacitance value (capacity density) obtained per unit area can be increased. Therefore, the formation area of the MIM capacitor can be reduced, and the semiconductor device can be downsized. At this time,
Between the metal film containing titanium (Ti) and the Au film,
A Mo film or a Pt film may be inserted.

Although the present invention has been described in detail with reference to the above embodiments, the present invention is not limited to the above embodiments, but may be variously modified without departing from the scope of the invention. Of course.

For example, an HBT formed on a GaAs substrate
(Hetero Bipolar Transistor) and a capacitance element, even in a circuit device in which a resistance element is integrated, by using the capacitance element having the MIM structure of the present invention for the capacitance element, the circuit device can be reduced in size and the manufacturing cost can be reduced. It is possible.
The semiconductor integrated circuit device according to the present invention is not limited to a so-called large-scale integrated circuit having a large number of elements, but includes a case where two or more elements are formed on the same semiconductor substrate.

[0121]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) The size of a semiconductor integrated circuit device having a MIM structure capacitive element can be reduced.

(2) It is possible to improve the capacitance value (capacity density) obtained per unit area when a capacitor having the MIM structure is formed on a semiconductor substrate.

(3) The size of the semiconductor integrated circuit device having the MIM structure capacitive element can be reduced, and the manufacturing cost of the semiconductor integrated circuit device can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view illustrating a schematic configuration of a semiconductor integrated circuit device having a MIM structure capacitive element according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view taken along line AA ′ of FIG.

FIG. 3 is a plan view in each manufacturing step of the capacitive element having the MIM structure according to the first embodiment.

FIG. 4 is a plan view in each manufacturing step of the capacitive element having the MIM structure according to the first embodiment.

FIG. 5 is a plan view in each manufacturing step of the capacitive element having the MIM structure according to the first embodiment.

FIG. 6 is a plan view for explaining the function and effect of the MIM structure capacitive element according to the first embodiment.

FIG. 7 is a schematic cross-sectional view showing a modification example of the MIM structure capacitive element according to the first embodiment.

FIG. 8 is a diagram showing a schematic configuration of a semiconductor integrated circuit device equipped with a MIM structure capacitive element according to the first embodiment.

FIG. 9 is a plan view illustrating a schematic configuration of a modified example of the MIM structure capacitive element according to the first embodiment.

FIG. 10 is a schematic cross-sectional view taken along line BB ′ of FIG.

FIG. 11 is a plan view illustrating a schematic configuration of a semiconductor integrated circuit device having a MIM structure capacitive element according to a second embodiment of the present invention.

FIG. 12 is a schematic cross-sectional view taken along line CC ′ of FIG. 11;

FIG. 13 is a plan view illustrating a schematic configuration of a semiconductor integrated circuit device having a MIM structure capacitive element according to a third embodiment of the present invention.

FIG. 14 is a schematic sectional view taken along line DD ′ of FIG. 13;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... GaAs substrate, 2 ... insulating film, 3 ... 1st electrode, 3A ...
Wiring connection part of first electrode 3, 4 ... first interlayer insulating film, 5 ... first capacitance insulating film, 6 ... second electrode, 6A ... wiring connection part of second electrode 6, 7 ... lead wire (first lead wire) , 7A: wiring portion of lead wire 7, 8: second interlayer insulating film, 9: second capacitance insulating film, 10: third electrode, 10A: wiring connecting portion of third electrode 10, 11: first protection Film, 12 first metal wiring, 1
3 ... second metal wiring, 14 ... second protective film (surface protective film),
15: Intermediate wiring, 15A: Wiring connection part of intermediate wiring 15,
16 second lead, 17 third interlayer insulating film, 18
Third capacitance insulating film, 19: fourth electrode, 20: lower electrode (first electrode), 21: interlayer insulating film, 22: capacitive insulating film, 23
... upper electrode (second electrode), CO1 ... first capacitor opening, C
O2: second capacitance opening, CO3: third capacitance opening, TH
1: first through hole, TH2: second through hole, T
H3: third through hole, TH4: fourth through hole,
TH5: fifth through hole, TH6: sixth through hole, TH7: seventh through hole, TH8: eighth through hole, TH9: ninth through hole, TH10: tenth through hole, TH11: eleventh through hole, C1 ... First MIM capacitance, C2 ... Second MIM capacitance, F1, F2 ... Field effect transistors, L1, L2, L3 ... Inductors, P1, P2, P3, P4, P5, P6 ... Bonding pads, W1, W2, W3, W4 ... metal wiring.

Claims (17)

[Claims] A first metal film, a first insulating film, a second metal film, a second insulating film, and a third metal film sequentially laminated on a semiconductor substrate, wherein the first metal film and the third metal film are stacked; The films are electrically connected to each other, and a first capacitor including the first metal film, the first insulating film, and the second metal film, and a first capacitor including the second metal film, the second insulating film, and the third metal film. An MIM structure, wherein two capacitances are connected in parallel, and a capacitance intrinsic portion functioning as the capacitance of the second capacitance is provided inside the capacitance intrinsic portion functioning as the capacitance of the first capacitance. Capacitive element. 2. An n-layer (n is an integer of 3 or more) first to n-th metal film on a semiconductor substrate, and n-1 first to n-th insulating films between each metal film. -1 insulating film, and the second metal film (m is an integer from 1 to (n + 1) / 2) among the first metal film to the n-th metal film is electrically connected to each other. And the second m-th metal film is electrically connected to each other, and a k-th metal film (k is any integer from 2 to n-1), and a k-th insulating film on the k-th metal film And a capacitance intrinsic portion functioning as a capacitance of a k-th capacitor constituted by the k-th metal film, a k-th metal film, a k-th insulating film, and a k-th metal film provided below the k-th metal film. Characterized by being provided inside a capacitance intrinsic portion functioning as a capacitance of the (k-1) th capacitance constituted by Element. 3. A semiconductor integrated circuit device having a MIM-structured capacitor, wherein the MIM-structured capacitor is formed on a semiconductor substrate by a first metal film, a first insulating film, a second metal film, and a second metal film. An insulating film and a third metal film are sequentially stacked, and the first metal film and the third metal film are electrically connected to each other, and are configured by the first metal film, the first insulating film, and the second metal film. A semiconductor integrated circuit device, wherein a first capacitor and a second capacitor formed of the second metal film, the second insulating film, and the third metal film are connected in parallel. 4. A semiconductor integrated circuit device having a MIM-structured capacitor, wherein the MIM-structured capacitor is formed on a semiconductor substrate by a first metal film, a first insulating film, a second metal film, and a second metal film. An insulating film and a third metal film are sequentially laminated, and a capacitance intrinsic part functioning as a second capacitance of the second metal film, the second insulating film, and the third metal film is formed of the first metal. A semiconductor integrated circuit device provided inside a capacitance intrinsic portion functioning as a capacitance of a first capacitance constituted by a film, a first insulating film, and a second metal film. 5. A semiconductor integrated circuit device having a MIM structure capacitor, wherein the MIM structure capacitor is formed on a semiconductor substrate by a first metal film, a first insulating film, a second metal film, and a second metal film. An insulating film and a third metal film are sequentially stacked, and the first metal film and the third metal film are electrically connected to each other, and are configured by the first metal film, the first insulating film, and the second metal film. A first capacitor and a second capacitor formed of the second metal film, the second insulating film, and the third metal film are connected in parallel, and the capacitor intrinsic portion functioning as a capacitor of the second capacitor is formed by the first capacitor. A semiconductor integrated circuit device provided inside a capacitance intrinsic portion functioning as a capacitance of a capacitance. 6. The semiconductor integrated circuit device having the MIM structure capacitive element according to claim 3, wherein the first metal film and the third metal film are electrically connected to each other through a through hole. A semiconductor integrated circuit device, wherein the electrical connection via the through-hole is made by a metal attached to the through-hole when the second metal film is formed. 7. A semiconductor integrated circuit device having a capacitance element having an MIM structure, wherein the capacitance element having the MIM structure has n layers (n is an integer of 3 or more) of a first metal film to an n-th metal film. The first to n-th metal films are stacked between the respective metal films with the first to n-th insulating films interposed therebetween, and the second to m-th metal films among the first to n-th metal films are stacked. (Where m is an integer from 1 to (n + 1) / 2) are electrically connected to each other, and the second m-th metal films are electrically connected to each other, and the k-th metal film (k is 2 to n-1) An intrinsic part of the k-th metal film, which functions as a capacitance of the k-th capacitor formed by the k-th capacitance insulating film and the (k + 1) -th metal film, is provided below the k-th metal film. The k-th
A semiconductor integrated circuit device provided inside a capacitive intrinsic portion functioning as a capacitance of a (k-1) th capacitance constituted by a first metal film, a (k-1) th capacitance insulating film, and a kth metal film. 8. The semiconductor integrated circuit device having an MIM structure capacitor according to claim 7, wherein the 2m-1 metal films and the 2m metal films are electrically connected to each other via a through hole. The electrical connection between the 2m-1 metal films is made by a metal attached to the through hole when the 2m metal film is formed, and the electrical connection between the 2m-1 metal films is 2. A semiconductor integrated circuit device comprising a metal adhered to the through hole when a 2m-1 metal film is formed. 9. The semiconductor integrated circuit device having the MIM-structured capacitance element according to claim 3, wherein at least one of an odd-numbered and an even-numbered metal film of the MIM-structured capacitance element. And a metal wiring for connecting an electrode of another element formed on the semiconductor substrate, wherein a part of the metal film is extended. 10. The semiconductor integrated circuit device according to claim 9, wherein the metal wiring electrically connects the other one of the odd-numbered or even-numbered metal films to the one to which the metal wiring belongs. A semiconductor integrated circuit device present in a through hole connected to the semiconductor integrated circuit device. 11. The semiconductor integrated circuit device having the MIM structure capacitive element according to claim 3, wherein a metal film provided on an uppermost layer of the MIM structure capacitive element and the metal film A semiconductor integrated circuit device, wherein a metal wiring provided on a film with a protective insulating film interposed is connected through an opening formed in the protective insulating film on the metal film. 12. The semiconductor integrated circuit device having the MIM-structured capacitance element according to claim 3, wherein the metal film provided on the uppermost layer of the MIM-structured capacitance element is made of gold ( Au) A semiconductor integrated circuit device comprising a film. 13. An M according to claim 11 or claim 12.
In a semiconductor integrated circuit device having a capacitor having an IM structure, the protective insulating film includes a silicon nitride film. 14. The semiconductor integrated circuit device having the MIM structure capacitive element according to claim 3, wherein at least one of the metal films stacked with the insulating film interposed therebetween. Wherein the outer periphery of the metal film does not intersect planarly with the outer periphery of the metal film via the insulating film below the metal film. 15. The semiconductor integrated circuit device having the MIM structure capacitive element according to claim 3, wherein the first metal film includes a metal film containing gold (Au). A first film on the first metal film;
A semiconductor integrated circuit device, wherein an interface side with an insulating film is a metal film containing titanium (Ti). 16. The semiconductor integrated circuit device having the MIM-structured capacitance element according to claim 15, wherein the metal film containing titanium (Ti) is a titanium (Ti) film, a titanium nitride (TiN) film, or A semiconductor integrated circuit device, which is one of a compound film of titanium and tungsten (W). 17. The semiconductor integrated circuit device having the MIM structure capacitive element according to claim 15, wherein the first metal film includes the gold (Au) -containing metal film and the titanium (Ti) -containing metal film. A semiconductor integrated circuit device having a molybdenum (Mo) film or a platinum (Pt) film interposed therebetween.