JPS6135167A - Controller for inverter - Google Patents

Abstract

PURPOSE:To efficiently utilize a memory cell by separately storing the ON-OFF combination state of a switching element and the maintaining time, and obtaining the output of the combination switching elements. CONSTITUTION:When a setter 8 sets an output frequency F and a set value F/V to F''=10, V/F=0.5'', a controller 15 reads out the maintaining time ''t=28'' from the second memory 11 on the basis of the value of ''C=0'' to set in a timer 14. Then, it converts the combination state P of ON-OFF of transistors 2-7 with the value of the third memory 12 on the basis of ''theta=0'' and C=0'' to obtain from the first memory and to output it. Then, the timer 14 starts step backward to maintain this state until the remaining time of the timer 14 become t1<tp. Then, a variable theta, C are altered, this operation is repeated to obtain ON-OFF signals of the transistors 2-7 for one period.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to an inverter control device that can obtain three-phase AC output through ON-OFF control of a plurality of switching elements constituting a three-phase bridge. .

(b) Conventional technology In general, conventional inverter devices configure multiple switching elements (for example, transistors, thyristors, etc.) in a bridge shape, and control the ON/OFF states of these switching elements to convert DC into single-phase or three-phase was converting to the output of

ON-OFF signals for one period of the switching element are stored in a storage element, and these signals are sequentially read out to control ON-OFF of the switching element. That is, if this is explained based on FIGS. 15 and 16,
The figure shows six switching transistors (2) to (7) connected to a DC power supply (1) in a bridge configuration.
, (G), is a diagram of an inverter circuit in which a three-phase output can be obtained from W.

Transistors (2) to (7) are connected between base terminals, (
16th
The figure is an address map showing the state of the H level signal given to terminals (3), (g), (2)), ■, (to), and ■.As an example, the state of the H level signal given to terminal Only this is determined and described based on the PWM method, but the H level signals given to other terminals are the same and are therefore omitted. Signals used for 1 to 10 Hz are stored between Abiref 0 and 5110, and signals for 11 to 20 Hz are stored in addresses 512 to 1023.
The signals used for are stored. Similarly, signals used for each frequency band are stored. This is a terminal (goods), ■
, W. If the drive characteristics of the load are constant, it is sufficient to store only the signal for one of the frequency bands.

For example, if an output of 1 to 10 Hz is required from the terminals, leap, and W, specify addresses sequentially from O to 511 to connect terminals (X), (Y) of transistors (2) to (7).
, (force, flash, (2), had obtained the control signal to (2).

In this case, since addresses 0 to 511 constitute one cycle, it is necessary to appropriately set the cycle of the clock that specifies the address.

In this way, the switching signals for transistors (2) to (7) were stored in the memory element for one cycle. For this reason, a large amount of storage element capacity was required to store one cycle's worth of signals for each frequency, and in order to further increase the resolution of the output signal, it was necessary to further increase the storage element capacity. .

In order to solve the above problems, Japanese Unexamined Patent Publication No. 57-46
A method such as that described in Publication No. 677 was considered.

According to this method, if the negative part of the three-phase AC shown in FIG. 17(a) is inverted using a phase inverter or the like, the
Only positive waveforms as shown in Figure fb) will be generated. This figure 17 (
The waveform of b) is divided by 60" electrical angle, and
..., the waveforms are exactly the same, although there are differences in the U, ■, and W phases. These waveforms are also symmetrical in the middle of each section, ie, at the position shown by the dashed line.

When these waveforms are shifted by 306 and superimposed, Figure 17 (C
6 characteristics like 1. , D7, D2, D3, D is required. In other words, an ideal AC waveform can be obtained by appropriately combining the characteristics shown in FIG. 17(C). That is, to obtain the U phase, the angle is 0° to 30°. % characteristics, 30'' to 60'', characteristics, 606 to 90e, D2 characteristics, 906 to 120'', characteristics, 120
If the D4 characteristic is selected from 0 to 150 degrees and the D4 characteristic is selected from 150' to 180 degrees, positive half-wave sine waves can be continuously extracted by sequentially selecting the characteristics. Next, to obtain a negative waveform ranging from 180° to 360°, the phase of the waveform selected by the above method can be shifted to obtain a perfect sine wave. This sine wave can be returned to an ideal three-phase alternating current by shifting the phase by 120@, that is, by arbitrarily selecting the above characteristics.

(c) Problems to be Solved by the Invention In the conventional inverter control device configured as described above, the three-phase sine wave is controlled by six characteristics selected within the angle range of 0'' to 306 as described above. This means that if these characteristics are memorized, they can be used as three-phase control signals, but when such a method is used, the utilization rate of the memory element is Although it can be improved to some extent, it is still not sufficient.In other words, since part of the three-phase sine wave is stored, there is a limit to reducing the capacity of the storage element due to resolution considerations. is.

In view of such problems, an object of the present invention is to provide an inverter control device in which the capacity of a memory element is greatly suppressed.

B) Means for Solving the Problem The inverter control device according to the present invention includes a three-phase 71779 section configured using a plurality of switching elements, a first storage section that stores the ON-0FF combination state of the switching elements, The initial value of the maintenance time to maintain this ON-OFF combination state is set for each (output voltage)/(output frequency).
a second storage unit that stores the data for each time; a calculation unit that calculates a maintenance time for maintaining the ON-OFF combination state based on this initial value; and a control section that outputs a PWM output to the switching element.

(e) Effect If the in-control device is configured using such a means, the capacity of the second storage section can be suppressed to a minimum, and the capacity of the second storage section can be reduced to a minimum compared to the conventional in-control device. This allows for miniaturization.Also, since the maintenance time is determined by calculation, the frequency resolution of the inverter device can be improved based on the accuracy of this calculation.

(F) Embodiment Below, embodiments of the present invention will be explained based on FIGS. 1 to 14. First, in FIG. 1, a PWM control signal to be applied to the same inverter circuit as shown in FIG. 15 is obtained. (C) in the figure is a carrier wave, (Ml), (M
2) and (M3) are modulated waves whose phases are shifted by 120 degrees, and there is a relationship of (frequency of carrier wave)/(frequency of modulated wave)=(odd multiple of 3). <XO) is the switching signal of the transistor (2) obtained by comparing the carrier wave (C) and the modulated wave (M, ), and (Yo) is the carrier wave (Q
and the modulated wave (M, ), and (Zo) is the switching signal of the transistor (4) obtained by comparing the carrier wave (C) and the modulated wave (M3). Switching signal, transistor (5), (6), (power switching signal (
Xo), (Yo), (Zo) are switching signals (X;
), (Yo), and (Zo) are obtained by inverting them, so their explanation will be omitted.

Here, the three-phase alternating current in FIG. 1 is from 0° to "a" in FIG. 1, as can be seen from the explanation of FIG. 17 and this figure.

A three-phase alternating current for 0° to 360° is formed by appropriately combining the components of the section (parts of the modulated waves (M, (M2), (M3)). Therefore, the carrier wave (C) and modulated wave (Ml
The same holds true for the switching signals (Xo), (Yo), and (Zo) obtained by comparison with ), (M2), and (Ms). The signal waveforms of the switching signals (Xo), (Yo), and (Zo) in the 0° to 3-ge interval are respectively (Xl), (Yl), (z, ) Torsult, 30
Signal waveforms (X, ), (Y,), (Z2
) correspond to the waveform obtained by reading the signal waveform (2,) backwards, the waveform reading the signal waveform (Y, ) backwards, and the waveform reading the signal waveform (Xl) backwards, respectively. Hereinafter, by converting the signal waveforms (XI), (Yl), and (Zl) by reading them backwards, inverting them to 0, etc., one period (0° to 360＠) of switching signals ( Xo)
, ('Yo), and (Zo) can be obtained.

Next, Figure 2 shows (frequency of carrier wave)/(frequency of modulated wave)
It is an enlarged view of the 0° to 30° section when =27.

Components in the figure that are the same as those in FIG. As shown in Figure 2, the signal waveforms (X,), (Y,)
, (Zl) are respectively (To) to (T 1□), the transistors (2) to (7
) is shown in FIG. 3. Furthermore, the second
The section (Ts) in the figure always takes only a small amount of time even when the voltage ratio between the carrier wave and the modulated wave is changed. Therefore, since this interval from 0° to 30° takes a minute time, omitting it will not cause any problem in the operation of the inverter, and therefore, in the following explanation, this interval (T6) will be omitted. In these sections ('ro), (T2), (T6), and (T8), the combination states of ON and OFF of the transistors (2) to (power) are the same, and in the sections (T1), (T7), (
TI2) is also the ON-OF of transistors (2) to (7).
The combination of F is also the same, and similarly the sections (T3) and (T5
), (T, ), (T11), interval (T4), (T+.)
are also the same. Therefore, it is configured in four types of combinations as described above.

In this way, the ON-O of transistors (2) to (7)
The number of combinations of F is limited to a predetermined number.

Therefore, from transistor (2) to (ON-
OFFCON is 1 and OFF is 0), the combination state is shown in FIG. In this figure, state (0)
The states (7) to (7) are the basic combination states of the transistors (2) to (7). In addition, transistors (5), (6),
The ON-OFF state of (7) is the transistor (2), (3
), (4) are assumed to be in an inverted state of the ON-OFF state. Further, states (8) to (c) indicate get time states. For example, the section (To) → (T
, ), the combination state of the transistors changes from state (0) to state (6) in FIG. Specifically, a change occurs in that the transistor (4) becomes ON40'FF and the transistor (7) becomes 0FF-)ON. If there is no put-time state at this time, transistors (4) and (7) will be turned on at the same time during this switching, causing a short circuit in the inverter circuit and transistors (4) and (7).
) may be damaged. This is a transistor (4),
(7), and is mainly based on O
This is due to a time delay in the operation when transitioning from N to OFF state. Therefore, when switching from state (0) to state (6), if put-time state (8) is used to change state [0) → put-time state (8) → state (6), transistor (4),
(7) There is no short circuit and this problem is solved. (5th
Sections θ''~60''~60'' in the figure refer to jisters (2) to (
If the switching characteristics in 7) are improved by adding a discharge circuit or the like, such a get time condition will become unnecessary.

If such states (0) to (7) and get time states (8) to (c) are combined, ON-OF for one cycle can be obtained.
F combination states can be obtained. ON- of transistors (2) to (7) for one period obtained in this way
FIG. 5 shows the OFF combination state. This figure shows a 60" section divided into 13 sections of 30" each as shown in Figure 3.
The section, that is, the 60° section is divided into 25 sections. Note that the section (wing is in a dead time state).

FIG. 8 shows the maintenance time (including the get time state (approximately several tens of microns)) of each section (0) to (goods) shown in FIG. (However, when V/F (output voltage/output frequency) is set to 0.5.) Also, as can be seen from Figures 1 and 2 above, the output waveform for one cycle is 0°
It can be represented by a waveform in the ~30° interval, and in the 0°~60'' interval, which is doubled, the maintenance time of each interval is symmetrical with respect to 30''.

That is, by arranging the sections (0) to (1) in reverse and arranging them with the section (121 to (0)), the sections (12) to (goods) can be obtained. If the time is determined, the maintenance time of each section for one cycle is also determined.In addition, in Fig. 8, the output frequency is separately shown from 10Hz to 60Hz every 10Hz.This is because the maintenance time Since the time of one cycle, that is, the frequency, is determined by the sum of , it is necessary to set the maintenance time for each frequency.

Note that the arrow in the table indicates that the maintenance time value is the same as the value of the frame on the left.

Therefore, transistors (2) to (2) as shown in FIG.
If the ON-OFF combination state of 7) is stored in the first storage section and the maintenance time shown in FIG. 8 can be calculated based on the initial value of the second storage section, this ON-OFF
ON-O of transistors (2) to (7) is determined by reading the combination state of F and calculating this maintenance time.
It is possible to control the F state.

For example, when the frequency is 10 Hz and an output of 0.5 in V/F is obtained, the section (, To
), the ON-OFF combination states of transistors (2) to (7) are determined from section (0) of the first storage section based on FIG. 6, and the maintenance time of section (0) is calculated based on FIG.
μ [sec]” and set it in a separately provided timer. Therefore, this state will be maintained until this timer times up. Furthermore, the predetermined time at the end of this section (0) will be in the get time state. This prevents damage to the transistors (2) to (7) when the ON/OFF states of the transistors (2) to (7) are switched to the next section (1).Next, when the timer times up, Section (1)
Transistors (2) to (power ON/OFF states and sustaining times are read from the first and second storage sections (here, the sustaining times when the frequency is 10 Hz are stored as initial values). , to control the ON-OFF state of transistors (2) to (7).The ON-OFF state of transistors (2) to (7) is controlled every time the following sections are switched.
A continuous switching signal can be obtained by sequentially reading out the state and maintenance time.

Next, the maintenance time of each section at each frequency is determined by the predetermined sections (0), (2), (3), (5), (6).
, (8), (9), (11), <13), (15),
a6), 0飄α9, (21), (24, (24+te&')
;When IV/F is constant, the maintenance time is constant regardless of the frequency. Therefore, in such a section, the initial value maintenance time corresponding to V/F stored in the second storage unit may be used as is. Other sections (1), (4), (7),
(10), Mackerel, 1. In αη, (a), and (c), the value obtained by subtracting a constant value from the initial value stored in the second storage section corresponds to the maintenance time of this section. For example, if the frequency is 20 Hz, the required maintenance time can be obtained by subtracting 926'' from the initial value, and by subtracting 1235'' from the initial value if the frequency is 30 Hz. The constant value (f3(F)) for each frequency is shown in FIG.

The above explanation is based on (output voltage M)/
(Output frequency CF')) is a certain constant value, but when this value V/F is changed, the maintenance time is, for example, V/F + 0. s, V/F-: 1.0°V/F
Middle school 1. ．． 5, V/F=2. OK, Figures 8 to 11
As shown in the figure. These diagrams also show that when the V/F value changes,
It is shown that by using the constant value (fs[F]) shown in FIG. 8, each maintenance time can be determined by calculation.

Therefore, if you memorize the constant value (old) as shown in Figure 7 and the initial value for the V/F value as shown in Figure 12, the data in Figures 8 to 11 will be saved. (Even various V
The output of the maintenance time for the value of /F can be obtained.

The flowchart shown in FIG. 13 shows the operation of the control unit, the calculation unit, the first storage unit, the second storage unit, and the constant value that executes the above operations, and the operation of the control unit and calculation unit when the constant value is stored inside the microprocessor. ) K, first, in this flowchart IC, F) and (V/F) are the set frequency and output waveform (output voltage)/(output frequency) set value given from the outside, and (1) is The remaining time of the built-in timer, (Q is the set value of the interval, (θ) is the electrical angle interval indicating θ'≦θ<θ'+60', θ=0 is 0°≦θ≦60°, θ=60
is 60″≦θ×120°,...θ=300 is 300'
≦θ≦360''. Also, the remaining time (t)
(maintenance time) is from Figure 12. t=f, (V/F, C
)" to find the initial value, 'C' is C=1.4.7.10,
From Figure 7 only at the time of 12.14.17.20.23 "f
3(117-) and further perform subtraction to determine the value of t''.

Also, transistors (2) to (7) are ON -OF.
F state P is “P=f, (θ, C)” from Figures 4 and 5.
It is determined by When starting operation by turning on the power, etc., after initializing and initializing variables,
Set frequency and set value (V/
F) is read, and then the maintenance time, that is, the timer setting time (1) is found and set in the timer. Next, the transistor (
The ON-OFF states (P) of 2) to (7) are determined and output to transistors (2) to (7).
) to (determine the ON-OFF state of the force. At this time, find the output surface of the put-time state required when changing to the next section, that is, when section (0 becomes section (C+1)).

After that, the timer starts decrementing. After this, the remaining time of the timer is “t<to” (put time is t,
Let it be p (sec). ), the output becomes P decotime state. After changing the descendant variables (0, (θ)), the set frequency (2) and the set value (V
/F) and repeat the same operation. Therefore, when the set frequency (F'') is switched, the output frequency is switched from the time the set frequency port is read.

FIG. 14 shows a block configuration diagram of the device according to the present invention, in which (8) is a frequency (5) and setting value (V/F) setting section, and (9) is a microprocessor that stores the information shown in FIG. The first storage unit a [, setting value (V/F) in Fig. 12
A second storage unit α stores the initial value (value at 10Hz) of
D. A third storage section (1) that stores the information in FIG. 5, a fourth storage section that stores the information in FIG. Q5) (including the calculation section). In addition, the edge
+(3), jump, (Z), ■, bacteria, (2) are connected to the pace terminals of each transistor (2) to (7) of the three-phase inverter circuit shown in Figure 15. .

The operation of the inverter control device configured as described above will be explained in detail again using FIG. 6. First, the setting section (8)
When the output frequency port is set as F=10 and V/F=0.5'', the control unit (19) sets the sustain time ``t:28'' based on the value of ``c=o'' in the second storage unit ( 11) and set it to the timer (141), then "θ20pa" c=o
” transistors (2) to (7) are turned on based on the value of
-OFF combination state cod is converted by the value of the third storage section α2, obtained from the first storage section aω, and output. This output is sequentially turned OFF, as shown in the state of electrical angle 0° in Figure 6.
The state is OFF, ON, ON, ON, OFF. Thereafter, the timer 04) starts decrementing, and this state is maintained until the remaining time of this timer becomes t<t,''.

That is, section T in FIG. It is. Furthermore, this section T.

During the latter half of the period tDμ (sec), there is a put-time state, and the ON-OFF state of the transistor (2) or (power) becomes OFF%OFF, OFF, ON, ON, OFF.

Next, when this timer (14) times up (t<O), after changing the variables θ and C, the 13th
The section T shown in FIG. 6 is obtained by repeating the operations based on the diagram.

Thereafter, the sections T2 to T24 are sequentially determined in the same manner, and the ON-OFF signals of the transistors (2) to (7) for one cycle can be obtained.

Next, for example, when the set frequency is changed to "F=20"', the control unit (151) reads the maintenance time "t=28" from the second storage unit (11) based on the value of "CCO2" and sets the timer. (14). Next, based on the values of 70=O, C=O", transistors (2) to (power ON-OF) are set.
The combination state (P) of F is stored in the first storage section α in the same manner as above.
Find it from Q. Thereafter, when "C=1", the maintenance time "t=872" is first read out from the second storage section (11).

At this time, since "C=1", the predetermined value of the sword is obtained from the fourth storage unit 09, and the calculation of 1798f3(F)'' is performed by the control unit (151
Do it. This result “t=1798-926=872
" is set in the timer (14). Next, "θ=0, C21
” transistors (2) to (7) are turned on based on the value of
-OFl17) M matching state (P) All obtained from the first storage section α0 in the same manner as above. Below, based on the flowchart in FIG. 13, the sustaining time (1) and the transistor (2) are
) to (7), ON-0'FF signals of transistors (2) to (7) for one period at F=20'' can be obtained.

Similarly, the maintenance time (1) at the set frequency (2)
If the transistors (2) to (power ON-OFF combination states P) are sequentially determined based on the flowchart in FIG. 13, transistors (2) to (7 ) can obtain ON-OFF signals.

In addition, when the set value (V/F) is changed, the initial value based on this set value (V/F) is obtained from Fig. 12, and continuous PW
It is possible to obtain M output.

In this way, the inverter control device of the present invention can obtain the necessary control output by calculation based on the initial value that is different for each setting value (V/F) stored in the second storage section.

(g) Effects of the Invention The inverter control device of the present invention includes a three-phase bridge section configured using a plurality of switching elements, a first storage section that stores the ON-OFF combination state of the switching elements, and a first storage section that stores the ON-OFF combination state of the switching elements. a second storage section that stores an initial value of the maintenance time for maintaining the OFF combination state for each ■/F; a calculation section that calculates the maintenance time for maintaining the ON-OFF combination state based on this initial value; and a control unit that outputs a continuous PWM output to the switching element by combining the ON-OFF combination state and the maintenance time,
The ON-OFF combination state of the switching element and its maintenance time can be stored separately, and the output of the switching element can be obtained by combining these. Therefore, the PWM output for one cycle can be obtained with a small storage capacity, and the storage element can be used efficiently. Furthermore, since the resolution of the obtained PWM output can be determined by the value of the sustain time stored in the second storage section, there is no need to increase the capacity of the storage element in order to increase the resolution as in the past. In other words, a high-resolution inverter can be easily configured with a small storage capacity.

In addition, the (output voltage)/(output frequency) values of the inverter control device can be set arbitrarily, and the output can be obtained according to the characteristics of the driven load, increasing the versatility of the inverter control device. It is.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram showing the waveform obtained by the present invention, Fig. 2 is the same as Fig. 1 (frequency of carrier wave)/(frequency of modulated wave) = 2
7 is a partially enlarged view, and Figure 3 shows the ON-O of the transistors that constitute the inverter in order to obtain the waveform shown in Figure 2.
An explanatory diagram showing the FF state, Fig. 4 is an explanatory diagram showing the ON-OFF combination state of the transistors making up the inverter, and Fig. 5 is a maintenance state of the ON-OFF combination of the transistors making up the inverter for one period. FIG. 6 is an explanatory diagram showing the actual ON-OFF state of the transistors forming the inverter when the embodiment of the present invention is used, and FIG. 7 is an explanatory diagram showing an example of the subtraction time value used for calculation. Explanatory diagram, Fig. 8 is an explanatory diagram showing the maintenance time when V/F is 0.5, Fig. 9 is an explanatory diagram showing the maintenance time when 1,0 is in /F, and Fig. 10 is an explanatory diagram showing the maintenance time when V/F is 0.5. An explanatory diagram showing the maintenance time when /F is 1.5, Fig. 11 is an explanatory diagram showing the maintenance time when V/F is 2.0, and Fig. 12 is an explanatory diagram showing the initial value of the maintenance time. , FIG. 13 is a flowchart showing the operation of an embodiment of the present invention, FIG. 14 is a block diagram of a device showing an embodiment of the present invention, FIG. 15 is an electric circuit diagram of a three-phase inverter, and FIG. FIG. 17 fa), (b), and (C) are waveforms representing three-phase alternating current, respectively, and a waveform obtained by inverting the negative portion of the waveform in (a). and f
It is a waveform explanatory diagram which shows the waveform shown in b) divided into 6 parts and superimposed on each other from 0° to 180°. <10)...First storage unit, ←D...Second storage unit,
(151...control unit. Applicant: Sanyo Electric Co., Ltd. and one other attorney: Shizuka Sano, Tomomi Fu, N') -? No. 21!1 Figure 3 Figure 4 Figure 5517 44 To 8 5 Kinini, Figure 9 'yF41・0 101! I outside 41゛5 Figure 16 117 Flash (b) Figure 17 (C) D. Electric nine angle −

Claims (1)

[Claims] (1) A three-phase bridge section configured using a plurality of switching elements, a first storage section that stores the ON-OFF combination state of this switching element, and a maintenance time for maintaining this ON-OFF combination state. a second storage unit that stores an initial value for each (output voltage)/(output frequency); a calculation unit that calculates a maintenance time for maintaining the ON-OFF combination state based on the initial value; An inverter control device comprising: a control section that outputs continuous PWM output to the switching element by combining combination states and maintenance times.