JPS60261368A - Controller for inverter - Google Patents

Abstract

PURPOSE:To obtain a controller which suppresses a memory capacity by storing the ON-OFF combination state of a switching element of an inverter in a memory, and obtaining the PWM output by using the combined state and the counting operation of a timer. CONSTITUTION:A plurality of switching elements (transistors 2-7) are formed in a bridge state to construct an inverter, and the ON/OFF state of the elements are controlled to convert a DC power source 1 to an AC of 3-phase and the like. The combined state of the ON/OFF state is stored in advance in a memory, the combined state is read out from the memory, an initial value set in a calculator is set to a timer, and the ON/OFF state is maintained during the timer time. When this time is elapsed, the state of the next zone is read out from the memory, and the ON/OFF state of the switching element is controlled similarly.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to ON-OFF control of a plurality of switching elements constituting a three-phase bridge. It is designed so that it can be performed based on the state and the maintenance time.

(B) Prior art In general, conventional inverter devices configure multiple switching elements (for example, transistors, thyristors, etc.) in a bridge shape, and control the ON-OFF states of these switching elements to convert direct current into single-phase or three-phase was converting to the output of

For example, 0N-OF for one period of this switching element
An example of storing the F signal in a storage element and sequentially reading out this signal to control ON-OFF of a switching element will be explained based on FIGS. 9 and 10. FIG. 9 shows a DC power supply (
1) This is an inverter circuit diagram in which six switching transistors (2) and (2) are connected in a bridge configuration so that a three-phase output can be obtained from the terminals, jumps, and W.

Transistors (2) to (power is connected to the pace terminal (3), respectively)
It has (g), , , , , , and becomes ON (energized state) when an H level voltage is applied. FIG. 10 is an address correspondence diagram showing the states of H level voltages applied to terminals (3), (g), (Z),
-For example, only the state of the H level signal given to the terminal is P.
Although this is described based on the WM method, the H level signals applied to other terminals are the same and will therefore be omitted. Address 0~
Between addresses 5110 and 1023, 1 to 10 Hz IC signals are stored, and between addresses 512 to 1023, 11 to 20 Hz IC signals are stored.
C The signal used is stored. Below, signals used for each frequency range are similarly stored. This is a terminal (goods),
This is matched to the driving characteristics of the load connected to the leap and W, and if the driving characteristics of the load are constant, it is sufficient to store only the signal for one of the frequency ranges. In other words, when an output of 1 to 10 Hz is required from terminals, concave, W, address O to 511 are sequentially specified and transistors (2) to (power terminal diagram, (to), (
Obtain control signals for Z), ■, ■, and (. In this case, addresses O to 511 constitute one cycle, so the cycle of the clock that specifies the address must be set appropriately.

In this way, the switching signals for transistors (2) to (7) are stored in the storage element for one period, and therefore, one period of signals for each frequency is stored in the storage elements 1 to 6.
A lot.ゎMemory element □ 4 quantities 81, yes.

In order to improve the resolution of the output signal, it was necessary to further increase the capacity of the storage element.

In order to solve the above problems, Japanese Unexamined Patent Publication No. 57-46
A method such as that described in Publication No. 677 was considered.

According to this method, if the negative part of the three-phase alternating current as shown in FIG.
Only the positive waveform shown in Figure (b) is K. This figure 11 (
The waveform of b) is divided by 60 electrical degrees and divided into 1st, 2nd, 2nd
, . . ., the waveforms are exactly the same, although there are differences in the UlV and W phases. These waveforms are in the middle of each section, i.e. 1
The position shown by the dotted chain line is also symmetrical.

When these waveforms are superimposed with a shift of 30 degrees, Figure 11 (C
) such as Do, D+, Dt, Da,
D4 becomes Ds. Conversely, this means Figure 11<C)
Combining the characteristics of traps means that a more ideal AC waveform can be obtained. That is, to obtain the U phase, O~
30 is the D0 characteristic, 30 to 60 is the characteristic,
60-90.

characteristics, 90-120, D5 characteristics, 120-15
0, D4tVj characteristics Y'150 ~ 180'''C- can be successively extracted by selecting D3% characteristics sequentially. Negative waveforms from next K]80' to 360 The obtained K can be made into a perfect sine wave by changing the phase of the waveform selected by the above method.This sine wave can be made into an ideal sine wave by shifting the phase by 1200, that is, by arbitrarily selecting the above characteristics. It can be converted back to phase current.

Therefore, the three-phase sine wave can be represented by six characteristics selected within the angle of 5VCO0 to 3o0 as described above. This means that if these characteristics are memorized, they can be used as three-phase control signals.

Since the inverter device described above stores a portion of the three-phase sine wave, there is a limit to reducing the capacity of the storage element due to resolution considerations.

←j Purpose of the Invention In view of the above problems, the present invention is as described in 1. The present invention provides an inverter control device that minimizes the capacity of the cable.

B) Structure of the Invention The inverter control device of the present invention includes a three-phase bridge section configured using a plurality of switching elements, a storage section that stores the ON-OFF combination state of the switching elements,
a calculation unit that determines the maintenance time for maintaining this ON-OFF combination state; a timer unit that measures this maintenance time;
The inverter device is miniaturized by outputting a continuous 1-PWM output to the switching element using the ON-0FF combination state and the timing operation of the timer section.

(E) Embodiment Below, the embodiment of the present invention will be explained based on FIGS. 1 to 8. First, FIG. 1 shows a PWM control signal to be applied to the same inverter circuit as shown in FIG. 9. (C) in the figure is a carrier wave, (M,), (M2), (
M, ) are modulated waves whose phases are shifted by 120, and the relationship is (frequency of carrier wave)/(frequency of modulated wave)=(odd multiple of 3).

(Xo) is the switching signal of the transistor (2) obtained by comparing the carrier wave (c) and the modulated wave (Ml), and (yo) is the comparison of the carrier wave (cl) and the modulated wave (M, ). The switching signal of the transistor (3) obtained by (20) is the carrier wave (C) and the modulation wave (M
3) obtained by comparing the transistor (
4) switching signal, transistors (5) and (6)
), (7) switching signals (also.), (YO), (
zo) are switching signals (Xo), (yo), (20
) can be obtained by inverting each of them, so the explanation will be omitted.

Here, the three-phase AC in Figure 1 is obtained by appropriately combining the components in the O~300 section (parts of the modulated waves (M, ), (M, ), and (M3)) in the O~360 interval. A three-phase alternating current can be formed. Also, carrier wave (c) and modulated wave (M, ), (
The same holds true for the switching signals (Xo), (Yo), and (Zo) obtained by comparison with M, ), and (M3). If the signal waveforms of the switching signals (XO), (Yo,
The signal waveforms (X,), (Y,), and (Z,) in the sections are the waveforms obtained by reading the signal waveform (zl) from the opposite direction, and the signal waveforms (X,), respectively.
, ) corresponds to the waveform read from the reverse. Below, convert the signal waveforms (XI), (YI), (Z,) by reading them from the reverse direction or inverting them by 6.
The switching signal (X
o), (Yo), and (Zo) can be obtained.

Figure 2 shows (frequency of carrier wave)/(frequency of modulating wave) = 2
7 is an enlarged view of the section 0 to 30 in FIG. 1; Components in the figure that are the same as those in FIG. As shown in Fig. 2, the signal waveform (Xl), (
yl) and (Zl), respectively (To
) to (Tit), the ON-OFF state of the transistors (2) to (7) becomes K as shown in FIG. still,
The interval ('rat) in FIG. 2 always takes a small amount of time even when the voltage ratio between the carrier wave and the modulated wave is changed. Therefore, since this interval from 0 to 30 is a minute time, omitting it will not cause any problem in the operation of the inverter, so this interval (Tit) will be omitted in the following explanation. This interval CTo), (T,), (Ta), (T
In a), transistor (2) to (power 0N-OF
The combination states of F are the same, and the interval ('rl),
(T?) and ('rat) are also transistors (2) to (7).
) are also the same combination of 0N-OFF, and similarly the interval (
'rs), ('re), (T,), ('r++), interval (T4), and (T+o) are also the same. Therefore, the 0N-OFF states of transistors (2) to (7) are 5 to 4.
It can be configured in a combination of types.

In this way, from transistor (2) to (power 0N-OFF)
Since the combination of states is limited to a predetermined number, the possible states of transistors (2) to (7) are 0N-OFF (ON is 1).
．． When the combination states of (assumed to be OFF (O)) are summarized, they become as shown in FIG. In this figure, states (0) to (force are the basic combination states of operation of transistors (2) to (force). In addition, transistors (5), (6), (ON-OFF states of force are transistors (2) to (force). 2), (3), (4
) is assumed to be the inverted state of the 0N-OFF state. In addition, the state (8) to (2) indicates the time state.For example, when switching from the interval (To) to (T,) in Fig. 3, the combination state of the transistors changes from the state (0) in Fig. 4 to the state ( 6).Specifically, the transistor (4)
) turns from ON to OFF, and transistor (7) turns OFF.
-A change occurs at the point where it becomes +ON. If there is no dead time condition at this time, the transistor (
4) (If the power is turned ON at the same time, a short circuit may occur in the inverter circuit, causing damage to transistors (4) and (7). This is based on the switching characteristics of transistors (4) and (7). This is mainly due to the time delay when transitioning to the 0N-OFF state.Therefore, when switching from state (0) to state (6), the put-time state (
8) to change state (0) -> put-time state (8) -> state (6), the short circuit between transistors (4) and (7) will disappear and this problem will be solved. (Section O~6 in Figure 5
Also, if the switching characteristics of the transistors (2) and (2) are improved by adding a discharge circuit or the like, such a put-time state will become unnecessary.

Such a state (0) to (force and put-time state (
By combining 8) to (c), it is possible to obtain an ON-OFF combination state for one cycle. Figure 5 shows an example of the combination state of 0N-OFF of the transistor (2) for one cycle of pressure applied in this way. The figure shows 60 sections, that is, 60 sections divided into 24 sections. Note that the section (*) is a put-time state.

FIG. 6 shows the maintenance time of each section (0) to (goods) shown in FIG. 5 [including the get time state (approximately several tens of microseconds)]. In addition, as mentioned earlier, the output waveform for one period can be expressed as a waveform in the 0 to 30 interval, and furthermore, the 0 to 60 interval, which is doubled, is the maintenance time of each interval after 30. It is symmetrical. That is, the interval (
0) to 0 can be reversely arranged with the interval (13 to (0)) to obtain the interval a3 to Q4.

Therefore, if the maintenance time of each section from 0 to 30 is determined, the maintenance time of each section for one cycle is also determined. In addition, in FIG. 6, the output frequency is shown separately for every 4 Hz from 20 to 120 Hz. This is because the total time for one cycle, that is, the frequency, is determined by the total maintenance time, so it is necessary to set the trap maintenance time for each frequency.

Therefore, transistors (2) to (2) as shown in FIG.
If the combination state of 0N-OFF of the force is stored in the storage section and the maintenance time as shown in Fig. 6 is calculated by the calculation section, this combination state of 0N-OFF is read out
By calculating the sustain time, it is possible to control the ON-OFF state of the transistor (2).

For example, when obtaining an output with a frequency of 20 Hz, the explanation will be based on FIG. 7. First, in the section T0, based on FIG. 4, FIG. The combination state of 0N-OFF is read and the initial value (130) set in the arithmetic unit is set in the timer. Therefore, this state is maintained until the timer times out. ) becomes a dead time state, and when the 0N-OFF state of transistors (2) to (7) is switched to the next section (11), transistors (2) to (2) to (2) are prevented from being damaged. .Next, when the timer times up, section (1) VC
The 0N-OFF state of the transistors (2) to (7) is read from the memory section, and the initial value (668) set in the calculation section is used for the maintenance time. Next, when obtaining an output with a frequency of 24 Hz, in interval (0), transistor (2) to (power The combination state of 0N-OFF is read out and the initial value (13
0) to the timer. Therefore, this state is maintained until the timer completes the time amplification. Next, when the timer times up, the 0N-OFF state of the transistor (21 to
668), perform the calculation "668-154 (predetermined number) = 514", set the maintenance time (514) of this result in the timer, and set the 0N-O of the ℃ transistors (2) to (7).
Controls the FF state. Below, sections (4), (7), (l
The maintenance time is calculated by subtracting a predetermined number (154) from the initial value only when I, round, a selections (17), (2), and (c) are selected. Next, when obtaining an output with a frequency of 28 Hz, the predetermined number of calculation units is set to ``264'', and the maintenance time is determined by subtracting it from the initial value to control the ON-OFF state of transistors (2) to (7). A different predetermined number is determined for each frequency, and the maintenance time of a specific section is calculated.In this way, transistors (2) to (7)
), a continuous switching signal can be obtained by sequentially switching the combinations of ON-OFF states and sustaining times.

When the control unit, storage unit, and calculation unit that executes the above operations are housed and controlled within a microprocessor, the operation of the control unit will be explained based on the flowchart shown in FIG. 8. [F] is the set frequency given externally, (11 is the remaining time of the built-in timer, (c) is the set value for the interval, (θ) is “θ≦ψ≦θ+
It is an electrical angle section indicating 60″, and θ=0 is O≦ψ≦60
, θ=60 is 60≦ψ≦】20...θ=300 is 3
00≦ψ≦360, respectively. Also, the remaining time (
The initial value of 1) is set in the arithmetic unit and is ``c-setting value (
1,4,7, ]0, ]2.14.17.20.23)”
Otherwise, this initial value (f, (cl) is output to the timer, and if “C=setting value”, “t”, “f1(cl)
,! i'(F)" is output to the timer. Note that F(
Fl is a predetermined number determined for each set frequency month. (For example, it is 154 for F-224, and 264 for F-28.

) 0N-OFF state P of transistors (2) to (7)
is determined by p"f*cθ, C) from FIGS. 4 and 5.

When operation is started by turning on the power, etc., after initializing and initializing variables, read the set frequency set in the external setting section, and then set the sustain time, that is, the timer setting time (after 11, set the timer to Next, the transistors (2) to (ON-OFF state CP of power) are outputted to the transistors (2) to (7), and the transistors (
2) to (7) ON-OFF states are determined. At this time,
When changing to the next section, that is, section 0) becomes section (c+1)
Determine the output ψ of the get '1 tie state required when . After that, the timer starts decrementing. After this, the remaining time of the timer becomes "t <ttl" (put time t. μ is turned on. After changing the descendant variables (c) and (), read the set frequency (F) again. The same operation is repeated. Therefore, when the set frequency ■ is switched, the output frequency is switched from the time when this set frequency ■ is read.

The operation of the inverter control device as described above will be explained in detail again using FIG. 7. First, when the output frequency (2) is set to F=20 in the frequency setting section, the control section
0" and "c==o", the maintenance time "t=
130" in the timer in the calculation section. Next K"θ=θ
Transistors (2) to (
The combination state CP) of force ON-OFF is output. This output is 5KI as shown in the electrical angle 0(1) state KAVC in Figure 7.
[The state is OFF, OFF, ON, ON, ON, OFF. After this, the timer starts decrementing, and this state is maintained until the remaining time of this timer reaches "t(t,"), that is, section T in FIG. 7. Note that during this section T0, During the latter half tD [μsec], the get time state is reached, and the transistor (2) (force 0N-
OFF status is OFF, OFF, OFF, ON, ON, O
Becomes FF. Next, this timer times up (t<O)
Then, after changing the variable C5θ, the eighth
The section T1 in FIG. 7 is obtained by repeating the operations based on the flowchart shown in the figure. Thereafter, in the same way, one cycle of the transistor (2) to (0N-O
FF (i) can be obtained. Even when the frequency setting value changes, the sustain time is calculated based on the flowchart in Fig. 8, and the 0N-OF of transistors (2) to (7)
If the combination of F is determined, an output for one continuous period can be obtained.

In the case of such an inverter device, the output resolution is determined by the time accuracy of the maintenance time. In other words, the unit of maintenance time is, for example, 0 several tens μ [Sec"1" → "μ [s+=c
]”, you can further increase your spirit.

(f) Effects of brackets The inverter control device of the present invention includes a three-phase bridge section configured using a plurality of switching elements, a storage section that stores the ON-OFF combination state of the switching elements,
a calculation unit that determines the maintenance time for maintaining this ON-OFF combination state; a timer unit that measures this maintenance time;
Since continuous PWM output was output to the switching element using the 0N-OFF combination state and the time measurement of this timer section, the ON-OFF combination state of the switching element and this maintenance time are separately stored, Moreover, the output of the switching element can be obtained by a combination of these.

Therefore, PWM output for one cycle can be obtained with a small storage capacity, and the storage element can be used efficiently.

Furthermore, since the resolution of the obtained PWM output can be determined by the entire maintenance time in the arithmetic unit, there is no need to increase the capacity of the storage element to increase the resolution, as in the case of conventional inverters. However, it can be easily configured with a small storage capacity.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram showing the three-phase waveform obtained by the present invention, Figure 2
The figure is a partially enlarged view of Figure 1, and Figure 3 is an 0N-OF diagram of the transistors constituting the inverter to obtain the waveforms in Figure 2.
An explanatory diagram showing an F-shaped track. Fig. 4 is an explanatory diagram showing a basic pattern of 0N-OFF combinations of transistors constituting an inverter. Fig. 5 is a 0N-OFF combination for one period of transistors constituting an inverter. An explanatory diagram showing the state,
Figure 6 shows the 0N-O transistors that make up the inverter.
FIG. 7 is an explanatory diagram showing the maintenance time of the combination state of FFs; FIG.
9 is a flowchart showing an embodiment of the operation of the device of the present invention, FIG. 9 is an electric circuit diagram of a three-phase inverter, FIG. 10 is an address correspondence diagram of the contents of a memory element showing a conventional embodiment, and FIG. a) is a waveform diagram showing three-phase AC, Figure 11 (
b) is a waveform diagram in which the negative part of the waveform in Fig. 11 (a) is inverted, and Fig. 11 (cl is any single waveform shown in Fig. 11 (bl) divided into 6 parts and These are superimposed waveform diagrams. (2) to (power...transistor. Applicant: Sanyo Electric Co., Ltd. and one other representative, patent attorney: Yasuo Sano, Figure 2, Figure 31, Figure 4 + r', Inco, Separate, and Other Patent Attorneys) Figure 11 (1)) Figure 11 (C) D Yoden 9-

Claims (1)

[Claims] (1) A three-phase bridge section configured using a plurality of switching elements, a storage section that stores the ON-OFF combination state of this switching element, and an operation that determines the maintenance time to maintain this ON-OFF combination state. , a timer section that measures this maintenance time, and a continuous PW using the 0N-OFF combination state and the time measurement of this timer section.
An inverter control device characterized in that it outputs M outputs to the switching element.