JPS61185076A - Inverter controller - Google Patents

Abstract

PURPOSE:To reduce the memory capacity of a memory cell and to simultaneously simplify a control by obtaining the combined state of ON/OFF for preventing a switching element from shortcircuiting from the combined state of ON and OFF before and after switching. CONSTITUTION:A ROM11 stores the combined state of ON and OFF of a switching element, and a ROM12 stores a maintaining time for maintaining the combined state of ON and OFF. A timer 14 counts the maintaining time, sequentially switch the output of the combined state during the maintaining time counted by the timer 14 to output a continuous switching signal. A CPU10 obtains the output of the combined state used for switching the output of the combined state and the output of next combined state by the logic product of the output of the combined and the output of the next combined state.

Description

[Detailed Description of the Invention] G) Industrial Application Field The present invention relates to an inverter control device that can obtain three-phase AC output through ON-OFF control of a plurality of switching elements constituting a three-phase bridge. .

(b) Conventional technology In general, conventional inverter devices connect multiple switching elements (for example, transistors, thyristors, etc.) in the form of a bridge, and control the ON-OFF states of these switching elements to convert direct current into single-phase or three-phase was converting to the output of

ON-OFF signals for one period of the switching element are stored in a storage element, and these signals are sequentially read out to control ON-OFF of the switching element. That is, if this is explained based on FIGS. 14 and 15,
The figure shows an Imper 2 circuit in which six switching transistors (2) to (7) are connected to a DC power supply (1) in a bridge configuration so that three-phase output can be obtained from terminals υ, leap, and W. be.

The transistors (2) to (7) each have a pace terminal, and are turned ON (energized state) when an H level voltage is applied. Figure 15 shows the terminal■
, (To), Prison, ■, This is an address map showing the state of the H level voltage given to ml (2). As an example, only the state of the H level signal given to terminal (X)K is determined based on the PWM method. However, since the H level signals applied to other terminals are the same, they will be omitted. Abilev 0~5110
In between, signals used for 1 to 1011 Hz are stored, and in addresses 512 to 1023, signals used for 11 to 20 Hz are stored. Similarly, signals used for each frequency band are stored. This is tailored to the drive characteristics of the load connected to the terminal surface, ■, and W. If the drive characteristics of the load are constant, it is sufficient to store only the signal for one of the frequency bands. be.

For example, if an output of 1 to 10 Hz is required from terminals 0, leap, and W, specify addresses sequentially up to ON511 and connect terminals (3), (2),
■, control signals to the bacteria and surface were obtained. In this case, addresses O to 511 constitute one cycle, so it is necessary to appropriately set the cycle of the clock that specifies the address.

The switching signals for the busy transistors (2) to (7) are stored in the memory element for one period. For this reason, a large amount of storage element capacity is required to store one period's worth of signals for each frequency, and in order to further increase the resolution of the output signal, it is necessary to further increase the capacity of the storage element. Ta.

In order to solve the above problems, Japanese Unexamined Patent Publication No. 57-46
A method such as that described in Publication No. 677 was considered.

According to this method, if the negative part of the three-phase alternating current as shown in Fig. 16 (at) is inverted using a phase inverter etc.
Only positive waveforms like bl are shown in Figure 16 (
The waveform of bl is divided into electrical angles of 60° and divided into 1st, 2nd, 2nd
..., the waveforms are exactly the same, although there are differences in the U, V%W phases. These waveforms are also symmetrical in the middle of each section, ie, at the position shown by the dashed line.

When these waveforms are shifted by 30' and superimposed, Figure 16 (
6 properties like cl D0, D, , D, , D8, D4
, becomes Ds. In other words, an ideal AC waveform can be obtained by appropriately combining the characteristics of Figure 16 (cl). In other words, to obtain the U phase, use the Do characteristic for 00 to 300 degrees, and use the Do characteristic for 300 to 60 degrees. D1 characteristics from 60°
At 90°, the beam characteristics, from 90° to 120°, the Ds characteristics, from 1200 to 1500, the D4 characteristics, from 150° to 1
At 80°, positive half-wave sine waves can be continuously extracted by sequentially selecting the D3% property. Next 1800-360
K, which obtains a negative waveform up to 0, can be made into a perfect sine wave by phase-shifting the waveform selected by the above method. This sine wave can be returned to an ideal three-phase alternating current by shifting the phase by 120 degrees, that is, by arbitrarily selecting the above characteristics.

(c) Problems to be solved by the invention In the conventional inverter control device configured as described above,
The three-phase sine wave can be represented by six characteristics selected within the angle of 00 to 30 degrees as described above. This means that if these characteristics are memorized, they can be used as three-phase control signals, but if such a method is used, it is possible to increase the utilization rate of the memory element to some extent. was still not sufficient. That is, since a part of the three-phase sine wave is stored, there is a limit to reducing the capacity of the storage element due to resolution issues.

In view of such problems, the present invention greatly increases the capacity of the memory element by 5.
The purpose of the present invention is to provide an inverter control device that is compatible with the IF).

B) Means for Solving the Problems The inverter control device of the present invention comprises: a plurality of switching elements for converting DC voltage into AC voltage; a first storage unit storing ON-OFF combination states of the switching elements; It has a second storage unit that stores the maintenance time for maintaining the ON-OFF combination state, and a timer that measures this maintenance time, and this timer holds the output of the combination state, and the output of the combination state is maintained. In a device that obtains a continuous switching signal by sequentially switching outputs, the output of the previous combination state and the output of the next combination state are calculated by logically calculating the output of the combination state and the next combination state for a predetermined time. The control unit is provided between the output of the combination state and the output of the combination state.

(E) Function When the inverter control device is configured as described above, the ON-OFF switch for preventing short circuits of the switching elements is required when switching the ON-OFF combination state of the switching elements.
The OFF combination state can be calculated from the ON-OFF combination state before and after switching, and the storage capacity of the storage element can be reduced accordingly, and at the same time, control can be simplified.

(F) Embodiments Hereinafter, embodiments of the present invention will be explained based on the drawings. First, FIG. 1 is an explanatory diagram for determining a PWM control signal to be applied to the same inverter circuit as shown in FIG. 14. , in the figure (0 is the carrier wave, (Ml), (M, ), (M,) are modulated waves whose phases are shifted by 1200, respectively, (frequency of carrier wave) / (frequency of modulated wave) = (odd number of 3) (Xo) is the switching signal of the transistor (2) obtained by comparing the carrier wave (0 and the modulated wave (M, ), and (Yo) is the carrier wave (0) and the modulated wave (M, ). , ), the switching signal (Z6) of the transistor (3) obtained by comparing the carrier wave (0 and the modulating wave (M
, ) obtained by comparing the transistor (
4) switching No. a, transistor (5), (
6), (sword switching signal (Xo), (Yo), (
Zo) is the switching signal (Xo), (Yo), (Z
Since o) must be obtained by inverting each of them, the explanation will be omitted.

As can be seen from the explanation of FIG. 16 and this figure, the three-phase alternating current shown in FIG. A three-phase alternating current for 0° to 360° is formed by appropriately synthesizing a part of M, )). Therefore, carrier wave (0 and modulating wave (M, ), (M
The same holds true for the switching signals (Xo), (Yo), (Z, )K obtained by comparison with l), (M,). Switching signal in the 09~30° interval (
The signal waveforms of (Xo), (Yo), and (zo) are respectively expressed as (Xt
), (Yl), (zl) Tosult, 30° to 60' ISM signal waveform (Xt), (Yt), (Zt)
The waveform obtained by reading the signal waveform (Xl) from the opposite direction corresponds to the waveform obtained by reading the signal waveform (Xl) from the reverse direction. Below, the signal waveform (
X, ), (Y, ), (2)) can be converted by reading backwards or inverting them.
0° to 360°) switching signals (Xo), (Y,
), (zo) can be obtained.

Next, Figure 2 shows (frequency of carrier wave)/(frequency of modulated wave)
It is an enlarged view of the 00-30 degree section when =27.

Components in the figure that are the same as those in FIG. Signal waveforms (X, ), (y+) as shown in the second figure
, (Zl) are respectively (To) to ('rat), the transistors (2) to (7
) is shown in FIG. 3. Furthermore, the second
In the section (T,) in the figure, even when the voltage ratio between the carrier wave and the modulated wave is changed, only a small amount of time is required at normal pressure. Therefore, even the interval from 00° to 30° takes a very small amount of time, so omitting it will not cause any problem in the operation of the inno(-ta), so in the following explanation, this interval (T,) will be omitted. In these intervals (To), (T2), (T6), (T,), the ON-OFF combination states of transistors (2) to (7) are the same, and in the intervals (T,), ( T, ),
('rat) is also a transistor (2) or (power ON-O
The combination of FFs is also the same, and similarly the intervals (T, ), (
T, ), (To), (T+υ, interval (T4), (T,.

) are also the same. Therefore, it is configured in four types of combinations as described above.

In this way, the ON-O of transistors (2) to (7)
The number of combinations of F is limited to a predetermined number. Therefore, the possible ON-
The woven state of 0FF (ON is 1 and OFF is O) is shown in FIG. In this figure, state (0
) to (7) are the basic combination states of transistors (2) to (7). In addition, transistors (5) and (6
), (7) ON-OFF state is transistor (2),
It is assumed that the ON-OFF states of (3) and (4) are inverted. Further, states (8) to (c) indicate put-time states. For example, the section (To) in Figure 3 →
When switching to (TI), the combination state of the transistors is the fourth
The state (01 in the figure) switches to state (6). Specifically, the transistor (4) changes from ON to 0FFK, and the transistor (7) changes from OFF to ON.

If there is no put-time state at this time, transistors (4) and (7) will be in the ON state at the same time during this switching, causing a short circuit in the inverter circuit, and transistors (4) and (7) will be in the ON state at the same time.
(7) may be damaged. This is a transistor (4
), (7), and is mainly based on the time delay K when transitioning from ON to OFF state.
evening. Therefore, when switching from state (0) to state (6), if get time state (8) is used to change state (01 → put time state (8) → state (6)), transistor (4
), (7) are no longer short-circuited, and this problem is solved.

If such states (0) to (7) and put-time states (8) to (c) are combined, ON-OF for one cycle can be obtained.
F combination states can be obtained. ON of transistors (2) to (7) for one period obtained in this way
-OFF combination state is shown in FIG. This figure is the third
As shown in the figure, 6 is divided into 13 sections of 30° each.
The 0' section, that is, the 60' section is divided into 25 sections. Note that the section (*) is the get time state.

Here, the put-time state can be determined from the previous and subsequent combination states. For example, when changing from the interval (To) shown in FIG. 3 to the interval (TI), the ON-OFF state of the transistors (2) to (7) changes from the state (0) shown in FIG. 4 to
The state changes from put-time state (8) to state (6).

This put-time state (8) (000110) put-time state +
01 (OO1110) and state (6) (000111
), the following logical formula holds true.

[State (01(OO1110')) X C state (6
) (O00111)] = [state +81 (OOO11
0) ) That is, transistor (2) to (power ON-
If the OFF state is regarded as a logical value of 1.0, the put-time state (8) can be determined by the AND of the state (01 and the state (6). This logical operation is performed by the state (at(al, a2
, a3, a4, a5, a6), state (bl(bl, b2
, b3, b4, b5, b6), then it is calculated as follows.

[state(al(al, a2, a3, a4, a5, a6)
)X [state (bl (b 1, b2, b3, b4, b5
, b6)) = [: state (cl(alXbl, a2Xb2
, a3Xb3, a4Xb4, a5Xb5, a6Xb6
)] Therefore, once the states of transistors (2) to (7) are determined, the put-time states can be determined by calculation.

Note that if the above logical formula is transformed, it becomes the following logical formula.

[state fol) + (state (61) = C state (
8)] That is, transistors (2) to (7) are turned on.
- If the OFF state is expressed as a 1's complement number, it can be determined by logical sum.

Figure 7 shows the maintenance time of each section (0) to (goods) shown in Figure 5 (including the get time state (approximately several tens of μ (8W)))
It represents.

However, V/F (output voltage/output frequency)'=-0,5
If .

Furthermore, as can be seen from Figures 1 and 2 above, the output waveform for one cycle can be expressed as a waveform in the 00 to 30' interval, and the 00 to 60' interval, which is doubled, is 30.
The maintenance time of each section is symmetrical with respect to '. In other words, interval CI? J to r24) can be obtained. Therefore, if the maintenance time of each interval from θ° to 30° is determined, the maintenance time of each interval for one cycle is also determined. In addition, in FIG. 7, the output frequency is stored separately from 10 Hz to 60 Hz in increments of 10 Hz. This is because the time of one cycle, that is, the frequency, is determined by the sum of the sustaining times, so it is necessary to set the sustaining time for each frequency.

Note that the arrow in the table indicates that the maintenance time value is the same as the value of the frame on the left.

Figures 8, 9, and 10 show V/F values of ■, 0.
It is a figure which shows the maintenance time of each area when it is set to 1.5.2.0.

Figure 11 is a block configuration diagram of a device showing an embodiment of the present invention, and in the figure (8) is a frequency setter, which can be set manually or by inputting digital signals from other equipment. It may be any one that operates. (9)
is the control unit, which is composed of a microprocessor and the like. This microprocessor (9) has an internal arithmetic unit Q.
l, a first storage section (11) that stores the contents of FIG. 13, a third storage section 0 that stores the contents of the basic output state of FIG. 4, and stores the contents of the maintenance time shown in FIGS. 7 to 10. It consists of a second storage section α.

FIG. 12 is a flowchart showing the operation of the control section (9) shown in FIG. 11, and the operation is as follows. First, when operation is started by turning on the power, etc., each variable t, C1
Let θ be '0''. Next, trunk x ri(2) to !?+
(7) ON-OFF state CP+wo” P = f(θ,
C)". This conversion formula is the 13th
The range of angles in the figure (if q is set, then K is the state) is determined to be constant.Next, the state CP+ determined using this conversion formula is output and the transistor (
2) Switch the ON-OFF states of (7). Next, read the set frequency [F]. Next, the maintenance time (tl) of this state [F] is determined by the conversion formula t=g(F,C)'', and the timer (14) K is set. This conversion formula is shown in FIG.
/F! =;0.5) frequency [F] and interval (
By setting K to 0, the maintenance time (tl) is determined to be constant.Next, the timer starts decrementing (subtraction counting).Next, the remaining time of the timer is determined as l1lt≦
Until the 20μ formula is reached, the section is moved to the next section as K"C:C+1", and at the same time, the value of 1θ" is changed as necessary, and the newly determined section (based on the value of 0, The state (Q is determined by 'Q=f(θ, C)'', the logical product of the previously determined state CPI and the logical value of this state (Q) is determined, and this value is stored as state (2). Next, the value of state CP+ is changed to the value of state (Q). Then, when the remaining time (tl of timer (141) becomes "t≦20 μsec", the value of state (■) is outputted and transistors (2) to (7 ). After this, the remaining time of timer I (tl is "t≦00").
Then, after reading the setting frequency port again, the state [
F] is output to switch the values of transistors (2) to (7). Thereafter, the above-mentioned operations are sequentially repeated.

When operating the inverter control device configured as described above, turn on the power and set the frequency [F] to, for example, "F=1"
0'', first the state (Pl is P=f(0,0)
Therefore, p=o is set, and the states of transistors (2) to (7) become (001110). Next, the maintenance time (tl is found as t=28 from t=g (10,0), this value is set in timer I, and at the same time the timer decrement is started. Next, the next interval "C=1" The state Q of is defined as Q=f(0
, 1) and store it. Next, the logical product of the state (0) and the state (1) is calculated, and the ON-OFF states of the transistors (2) to (7) based on this value are stored as a state entry. This state port is output when the remaining time of timer I becomes t≦20 μSec", and the ON/OFF states of transistors (2) to (swords) are switched. Also, the state (0) stored in state CPl is changed to state ( Change to the state il+ stored in Q. After this, if the remaining time of timer I becomes "1603 formula", this newly stored state (1
Outputs 1 and turns transistors (2) to (7) ON-O.
Switch the FF state. After this, the maintenance time of section (1) (
Find tl as "t=g(0,1)" and set it in the timer (141).

Thereafter, by repeating the same operation as above, state (Pl), state (Q, state ■) are obtained, and transistors (2) to (7) are sequentially
The ON/OFF state of the switch is switched.

(G) Effects of the Invention The inverter control device of the present invention includes a plurality of switching elements that convert DC voltage into AC voltage, a first storage unit that stores ON-OFF combination states of the switching elements,
It has a second storage unit that stores a maintenance time for maintaining this ON-OFF combination state, and a timer that measures this maintenance time, and during the maintenance time measured by this timer, the combination state is maintained. In a device that obtains a continuous switching signal by sequentially switching the outputs, the output of the combination state used when switching between the output of the combination state and the output of the next combination state is switched between the output of the combination state and the next combination. Since this is determined by a logical operation with the output of the state, the capacity of the storage element that stores the combination states can be reduced by the number of combination states determined by this logical operation.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram showing the waveform obtained by the present invention, Fig. 2 is the same as Fig. 1 (frequency of carrier wave)/(frequency of modulated wave) = 2
7 is a partially enlarged view, and Figure 3 shows the ON-O of the transistors that constitute the inverter in order to obtain the waveform shown in Figure 2.
An explanatory diagram showing the FF state, Fig. 4 is an explanatory diagram showing the ON-OFF combination state of the transistors constituting the inverter, and Fig. 5 is an explanatory diagram showing the ON-OFF combination of the transistors constituting the inverter for one cycle. An explanatory diagram showing the maintenance state, FIG. 6 is an explanatory diagram showing the actual ON-OFF state of the transistors constituting the inverter when the embodiment of the present invention is used, and FIG. Fig. 8 is an explanatory diagram showing the maintenance time when V/F is -1, 0. Fig. 9 is an explanatory diagram showing the maintenance time when V/F = ts. , FIG. 10 is an explanatory diagram showing the maintenance time when V/Fζ2.0, FIG. 11 is a block diagram of a device showing an embodiment of the present invention, and FIG. 12 shows the operation of the embodiment of the present invention. Flowchart diagram, FIG. 13 is an explanatory diagram showing the contents of the first storage section used in the embodiment of the present invention, FIG. 14 is an electric circuit diagram of a three-phase inverter, and FIG. 15 is an illustration of a memory element showing a conventional embodiment. Content address correspondence diagram, Figure 16 (al, (bl)
, (cl is a waveform indicating three-phase alternating current, (a waveform that is the inversion of the negative part of the waveform of al, and (00 to 0 of the waveform shown in bl)
It is a waveform explanatory diagram which shows 180 degrees divided into 6 parts and superimposed. (2) to (power...transistor, +81...frequency setter, (9)...control unit, αα...calculation unit, α]) to α3...first, second, second 3 storage section,
α4)...Timer. Applicant Sanyo Electric Co., Ltd. and 1 other agent Patent attorney Shizuo Sano Figure 2 Figure 3 Figure 4 151! ! ! 1 No. 61'2) Fig. 7 V/F book 0.5 Fig. 8 A. 1. . Fig. 9 Y-1.5 Fig. 10 VF: 2.0 Fig. 13 Fig. 15

Claims (3)

[Claims] (1) A first storage unit that stores a plurality of switching elements that convert DC voltage to AC voltage, the ON-OFF combination state of the switching elements, and a maintenance time for maintaining this ON-OFF combination state. The device has a second storage unit and a timer for measuring the maintenance time, and obtains a continuous switching signal by sequentially switching the outputs of the combination states, wherein the timer outputs the outputs of the individual ON-OFF combination states. During the timed maintenance time,
The present invention is characterized by comprising a control unit that provides an output of a value obtained by logically calculating the output of the combination state and the next combination state for a predetermined time between the output of the combination state and the output of the next combination state. Inverter control device. (2) Logical operation converts the ON-OFF combination state to 1-
The inverter control device according to claim 1, characterized in that when expressed by 0, the inverter control device is performed by logical product. (3) The inverter control device according to claim 1, wherein the logical operation is performed by a logical sum when the ON-OFF combination state is expressed in one's complement.