JPS613437A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS613437A
JPS613437A JP12466084A JP12466084A JPS613437A JP S613437 A JPS613437 A JP S613437A JP 12466084 A JP12466084 A JP 12466084A JP 12466084 A JP12466084 A JP 12466084A JP S613437 A JPS613437 A JP S613437A
Authority
JP
Japan
Prior art keywords
reference potential
lead frame
terminal
center point
gnd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12466084A
Other languages
Japanese (ja)
Inventor
Michiaki Kojima
小島　道章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12466084A priority Critical patent/JPS613437A/en
Publication of JPS613437A publication Critical patent/JPS613437A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain the stable titled device of wide operating margin by reducing the amount of noise by a method wherein the inductance of a reference potential is reduced by shortening the inner lead frame of the reference potential terminal and the enlarging its area. CONSTITUTION:The inner lead frame 4 of a reference potential is set at 1:1 or less in length to the lead frame 3 on the diagonal line and at 1:1 or more in the ratio of area by moving the center point of a cavity 2 from the center point of the package toward the reference potential terminal. This construction enables the noise generating at the reference potential by the capacitance coupling of the internal operating contact with the substrate 1 during the operation of the internal circuit to be reduced by a factor of a reduction in resistance L of the reference potential according to a formula dV=L.di/dt; therefore, the device of high stability whose input level, output level, and internal circuit operating margin have been enlarged can be obtained.

Description

【発明の詳細な説明】 本発明は、基準電位（ＧＮＤ’）端子のインダクタンス
を、減少させる構成を有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a configuration for reducing inductance of a reference potential (GND') terminal.

一般に、高速の半導体装置に於いては、高速で情報を転
送する必要から、各々のインバータの電流変化（ｄｉ／
ａｔ　）が大きく、基準電位（ＧＮＤ、）のインダクタ
ンスが太き込場合、ノイズが発生し易い状態におる。又
、大容量の半導体装置でも負荷の大きい回路では、情報
が変化する数ｎｓ〜１０ｎｓ程度の間に、ピーク電流が
、数十ｍＡ〜百数十ｍＡ流れる箇所もあり内部動作接点
と、容量結合により、基準電位（ＧＮＤ）の弯化が、ｄ
■＝Ｌ。In general, in high-speed semiconductor devices, it is necessary to transfer information at high speed, so the current change (di/
When the inductance of the reference potential (GND, ) is large and the inductance of the reference potential (GND, ) is large, noise is likely to occur. In addition, even in large-capacity semiconductor devices, in circuits with large loads, peak currents of several tens of milliamps to hundreds of milliseconds flow in some places during the few nanoseconds to ten nanoseconds when information changes, and the internal operating contacts and capacitive coupling As a result, the curve of the reference potential (GND) becomes d
■=L.

ｄｉ／ａｔ分だけ変動し実質的にスレッシー−ルド電圧
ｆｆＴ）が、変動して半導体装置の入力レベルや出力レ
ベル、あるいは、内部回路の動作マージン低下が、発生
し、シ、いては誤動作の原因にもなっている。この対策
として通常は、（１ｙ−Ｌ−ｄｉ／ｄｔ　　より回路に
於いては、電流変化（”／ａｔ）　ｔ−小さくする手段
と、ノイズに鈍感なヒステリシス、Ｗ性を持つ回路を用
いており回路以外では、パッケージの基準電位（ＧＮＤ
）のインダクタンスを減小させる手段が用いられる。　
　　　　　。The threshold voltage ffT (substantially the threshold voltage ffT) fluctuates by the di/at amount, which causes the input level and output level of the semiconductor device or the operating margin of the internal circuit to decrease, which may cause malfunction. It has also become As a countermeasure against this, a method is usually used to reduce the current change (''/at) t in the circuit from (1y-L-di/dt), and a circuit with hysteresis and W characteristics that is insensitive to noise. Other than the circuit, the package reference potential (GND
) is used.
.

第１図社従来のガラス樹、脂で封入した１６端子のデュ
アルインラインパッケージのリードフレーム及びキャビ
ティ図で、アルミナ基板１と、チップ搭載部のキャビテ
ィ２、及びリードフレーム３で構成されている。この様
な構成に於いては、キャビティ２の中心点がパッケージ
の中心点と同じである為、左・右及び対角線上の端子の
リードフレーム形状が同じになり、パッケージの端にあ
る基準電位（ＧＮＤ）端子４け、細く長い為インダクタ
ンスが大きく、回路動作時ノイズが発生し易い欠点があ
った。Figure 1 is a diagram of the lead frame and cavity of a conventional 16-terminal dual in-line package sealed with glass resin or resin, which is composed of an alumina substrate 1, a cavity 2 for a chip mounting portion, and a lead frame 3. In such a configuration, since the center point of cavity 2 is the same as the center point of the package, the lead frame shapes of the left, right and diagonal terminals are the same, and the reference potential ( Since the 4 terminals (GND) are thin and long, the inductance is large, and the disadvantage is that noise is likely to occur during circuit operation.

更にデュアルインラインパッケージに於いては、端子数
が増えるに従い基準電位（ＧＮＤ）端子４の内部リード
フレームが長くなるので、多数端子の場合は、中速・中
容量の半導体装置でもノイズが発生し易く入力レベルや
出力レベル及び内部回路の動作マージンが低下し、ひい
ては誤動作を起し易くしていた。Furthermore, in a dual in-line package, as the number of terminals increases, the internal lead frame of the reference potential (GND) terminal 4 becomes longer, so in the case of multiple terminals, noise is likely to occur even in medium-speed and medium-capacity semiconductor devices. The input level, the output level, and the operating margin of the internal circuit are reduced, and malfunctions are more likely to occur.

本発明の目的は、半導体装置のパッケージ形状を変える
事で、基準電位（ＧＮＤ）端子のインダクタンスを減小
させ高速あるいは、大容量半導体装置の回路動作時の基
準電位（ＧＮＤ）のノイズ発生を極力少なくシ、入力レ
ベルや出力レベルあるいは内部回路動作マージンを広く
したところの高安定性の半導体装置を提供する事にある
。An object of the present invention is to reduce the inductance of the reference potential (GND) terminal by changing the package shape of the semiconductor device, thereby minimizing noise generation of the reference potential (GND) during circuit operation of high-speed or large-capacity semiconductor devices. The object of the present invention is to provide a highly stable semiconductor device in which the input level, output level, or internal circuit operation margin is widened.

本発明の半導体装置は、キャビティの中心点をパッケー
ジの中心点より基準電位（ＧＮＤ）端子側へ移動させ基
準電位（ＧＮＤ）の内部リードフレームは、対角線上に
ある端子のリードフレームの長さに対し、１：１以下か
つ面積比を、１：１以上にした構成とした事を、特徴と
する。In the semiconductor device of the present invention, the center point of the cavity is moved from the center point of the package to the reference potential (GND) terminal side, and the internal lead frame of the reference potential (GND) is aligned with the length of the lead frame of the terminal on the diagonal. On the other hand, it is characterized by having a structure in which the area ratio is 1:1 or less and the area ratio is 1:1 or more.

以下本発明の実施例について図面を、参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.

第２図は、本発明の一実施例の要部を示すガラス樹脂で
封入した、１６端子のデュアルインラインパッケージの
リードフレームとキャビティ図で、第１図と同じ番号を
付している。すなわち、本実施例が、第１図の従来例と
、異な五点は、チップを搭載するキャビティ２の中心点
が、パッケージの中心点より基準電位（ＧＮＤ）端子４
側へ移動している為、基準電位（ＧＮＤ）端子４の内部
リードフレームが、従来の長さより短かく、かつ面積は
広くしている点にありこれ以外は第１図と同じでおる。FIG. 2 is a diagram of a lead frame and a cavity of a 16-terminal dual in-line package sealed with glass resin, showing essential parts of an embodiment of the present invention, and the same numbers as in FIG. 1 are given. That is, there are five points in which this embodiment differs from the conventional example shown in FIG.
Since the internal lead frame of the reference potential (GND) terminal 4 has been moved to the side, the length of the internal lead frame of the reference potential (GND) terminal 4 is shorter than that of the conventional one, and the area is larger, but other than this, it is the same as in FIG.

この時注意する点は、キャビシティ−の移動距離は、内
部リードフレームが長くなった端子の入力容量が、カタ
ログ５ＰＥＣ１−満足する範囲内でなければならない。At this time, it should be noted that the moving distance of the cavity must be within a range that satisfies the input capacitance of the terminal with a longer internal lead frame.

この様な構成によれば、内部回路動作時に内部動作接点
と基板の容量結合によシ基準電位（ＧＮＤ）に発生する
ノイズは、ｄ　ｙ　＝　Ｌ　０ｄ　ｉ　／ｄｔの式より
基準電位（ＧＮＤ）の°インダクタンス■が、減小した
分だけ小さくできるので、入力レベルや出力レベル及び
内部回路動作マージンを広くした高安定の半導体装置が
得られる。以上の説明はガラス樹脂で封入した１　６　
ｐｉｎのデュアルインラインパッケージを取シ上けて行
なったけれどもモールド・セラミックのデュアルインラ
インパッケージ及びミニフラットバ、ケー゛ジを用いた
半導体装置に適“用される事は言うまでもない。According to such a configuration, the noise generated at the reference potential (GND) due to capacitive coupling between the internal operating contact and the board during internal circuit operation can be reduced to the reference potential (GND) by the formula d y = L 0d i /dt. Since the inductance (2) can be reduced by the amount that is reduced, a highly stable semiconductor device with wide input level, output level, and internal circuit operation margin can be obtained. The above explanation is 1 6 sealed with glass resin.
Although the present invention was developed based on a PIN dual-in-line package, it goes without saying that it can also be applied to semiconductor devices using molded ceramic dual-in-line packages, mini-flat bars, and cages.

以上、詳細に説明した通り本発明の半導体装置は、基準
電位（ＧＮＤ）端子の内部リードフレームを従来よシ短
かく、かつ面積を広くしているので基準電位（ＧＮＤ）
のインダクタンスを減小させる事ができその分だけノイ
ズ量を少なくできるので動作マージンの広い安定した半
導体装置を容易に得る事ができる。As described above in detail, the semiconductor device of the present invention has an internal lead frame for the reference potential (GND) terminal that is shorter and has a wider area than the conventional one.
Since the inductance can be reduced and the amount of noise can be reduced accordingly, a stable semiconductor device with a wide operating margin can be easily obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の半導体装置のガラス樹脂で封入した１６
端子のデュアルインラインパッケージのリードフレーム
及びキャーティを示す図、第２図は本発明の一実施例を
示す、ガラス樹脂で封入した１６端子のデュアルインラ
インバツケニシノリードフレーム及びキャビティを示す
図である。 １・・・・・・アルミナ基板、２・・・・・・キャビテ
ィー、３・・・・・・ＩＪ−）”７　レ−Ａ、　４・・
・・・・基準電位端子のリードフレーム、である。 −年１圀 をＺ則Figure 1 shows a conventional semiconductor device encapsulated with glass resin.
FIG. 2 is a diagram showing a lead frame and a cavity of a dual in-line terminal package, and FIG. 2 is a diagram showing a dual in-line package lead frame and cavity of 16 terminals sealed with glass resin, showing one embodiment of the present invention. 1...Alumina substrate, 2...Cavity, 3...IJ-)"7 Le-A, 4...
...This is the lead frame for the reference potential terminal. -Z rule for one area per year

Claims (1)

【特許請求の範囲】[Claims] デュアルインライン及びミニフラットパッケージのキャ
ビティーの中心点を、パッケージの中心点より基準電位
端子側へ移動させ、基準電位の内部リードフレームの長
さは対角線上にある端子のリードフレームの長さより短
かく、かつ該基準電位の内部リードの面積と該対角線上
にある端子のリードフレームの面積より大であることを
特徴とする半導体装置。The center point of the cavity of dual in-line and mini-flat packages is moved from the center point of the package to the reference potential terminal side, and the length of the internal lead frame of the reference potential is shorter than the length of the lead frame of the terminal on the diagonal. , and the area of the internal lead of the reference potential is larger than the area of the lead frame of the terminal on the diagonal line.
JP12466084A 1984-06-18 1984-06-18 Semiconductor device Pending JPS613437A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12466084A JPS613437A (en) 1984-06-18 1984-06-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12466084A JPS613437A (en) 1984-06-18 1984-06-18 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS613437A true JPS613437A (en) 1986-01-09

Family

ID=14890895

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12466084A Pending JPS613437A (en) 1984-06-18 1984-06-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS613437A (en)

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