JPS6133258B2 - - Google Patents
Info
- Publication number
- JPS6133258B2 JPS6133258B2 JP52151973A JP15197377A JPS6133258B2 JP S6133258 B2 JPS6133258 B2 JP S6133258B2 JP 52151973 A JP52151973 A JP 52151973A JP 15197377 A JP15197377 A JP 15197377A JP S6133258 B2 JPS6133258 B2 JP S6133258B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- present
- leads
- view
- sides
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 239000011347 resin Substances 0.000 claims abstract description 4
- 229920005989 resin Polymers 0.000 claims abstract description 4
- 238000007789 sealing Methods 0.000 claims description 2
- 239000004642 Polyimide Substances 0.000 abstract description 2
- 239000012212 insulator Substances 0.000 abstract description 2
- 229920001721 polyimide Polymers 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は半導体装置に関するものである。[Detailed description of the invention] The present invention relates to a semiconductor device.
最近、半導体装置は１チツプ当りの素子数（集
積度）が大きくなり、価格及び性能の面からさら
にこの要求は強くなつてきている。一方、チツプ
だけではなく完成された封止後の半導体装置の容
積も、小さくする必要が出てきた。これは大容量
のメモリー等に代表される様に、半導体装置を大
量に用いる場合実装後の容積が小さいことが望ま
しいためである。 Recently, the number of elements per chip (integration degree) of semiconductor devices has increased, and this demand has become even stronger in terms of cost and performance. On the other hand, it has become necessary to reduce not only the volume of the chip but also the volume of the completed semiconductor device after sealing. This is because when a large number of semiconductor devices are used, as typified by large-capacity memories, it is desirable that the volume after mounting be small.
本発明は上記要求に基づいて、小容量の半導体
装置を提供するものである。 The present invention provides a small capacity semiconductor device based on the above requirements.
本発明の半導体装置は、薄い絶縁性のフイルム
の両面複数個のリードを設け、該フイルムの両面
にそれぞれ半導体チツプを載置し、該半導体チツ
プのボンデイングパツドと前記リードとを電気的
機械的に接合し、封止したことを特徴とする。 In the semiconductor device of the present invention, a plurality of leads are provided on both sides of a thin insulating film, a semiconductor chip is placed on each side of the film, and bonding pads of the semiconductor chip and the leads are connected electrically and mechanically. It is characterized by being bonded to and sealed.
本発明を実施例により説明する。 The present invention will be explained by examples.
第１図は本発明に使用する半導体チツプの平面
図（ａ図）及びａ図のＡ−A′断面図ｂ図であ
る。 FIG. 1 is a plan view (a) of a semiconductor chip used in the present invention, and a sectional view taken along line A-A' in FIG.
半導体チツプ１は基板２上に絶縁膜３を設け、
その上にリードとの接続用のパツドを設け、その
上にAl−Ti−Pt−Au系等のバンブ４を設けて作
られる。 A semiconductor chip 1 includes an insulating film 3 provided on a substrate 2,
A pad for connection with a lead is provided thereon, and a bump 4 made of Al--Ti--Pt--Au is provided thereon.
第２図は本発明にかるリード付きフイルムの平
面図（ａ図）、ａ図のＢ−B′断面図（ｂ図）及び
ａ図のＣ−C′断面図（Ｃ図）である。 FIG. 2 is a plan view (figure a) of a leaded film according to the present invention, a sectional view taken along line B-B' in figure a (figure b), and a cross-sectional view taken along line C-C' in figure a (figure C).
絶縁体、例えばポリイミドのフイルム５の両面
にリード６，７を設ける。 Leads 6 and 7 are provided on both sides of a film 5 made of an insulator such as polyimide.
第３図は本発明の半導体装置の製造方法を説明
する斜視図（ａ図）及びａ図のＤ−D′断面図
（ｂ図）である。 FIG. 3 is a perspective view (figure a) and a sectional view taken along line D-D' of figure a (figure b) for explaining the method of manufacturing a semiconductor device according to the present invention.
フイルム５の両面のリード６，７に半導体チツ
プ１，１′のバンブ４，４′をそれぞれ合わせてボ
ンデイングする。このようにフイルムの両面にそ
れぞれ半導体チツプ１，１′を取付けるとフイル
ムの占有面積が半分ですみ小容積化が実現され
る。 The bumps 4, 4' of the semiconductor chips 1, 1' are aligned with the leads 6, 7 on both sides of the film 5, respectively, and bonded. By attaching the semiconductor chips 1, 1' to both sides of the film in this manner, the area occupied by the film is halved, resulting in a reduction in volume.
第４図は本発明の半導体装置の視図である。 FIG. 4 is a perspective view of the semiconductor device of the present invention.
上記第３図で説明した組立品を樹脂８で封止し
たものでこれにより小型製品が得られる。 The assembled product explained in FIG. 3 above is sealed with resin 8, and a small product can thereby be obtained.
リード付きフイルムには種々の変形が可能であ
る。 Various modifications are possible to the leaded film.
第５図は本発明に使用するリード付きフイルム
の他の例の斜視図である。 FIG. 5 is a perspective view of another example of the leaded film used in the present invention.
フイルム４の一方の表面のリード６′と他方の
面のリード７′とをスルーホール９を介して電気
的に結合することができる。例えば、一方の半導
体チツプ１の出力信号を他方の半導体チツプ１′
の入力信号とするように結合することが可能とな
る。 Leads 6' on one surface of film 4 and leads 7' on the other surface can be electrically coupled via through holes 9. For example, the output signal of one semiconductor chip 1 is transferred to the output signal of the other semiconductor chip 1'.
This makes it possible to combine the signals into an input signal.
第６図は本発明にかかるリード付フイルムの更
に他の例の斜視図である。 FIG. 6 is a perspective view of still another example of the leaded film according to the present invention.
これはフイルム５″の内部を除去したものであ
る。このようにすれば二つの向い合う半導体チツ
プ１の電極を直接に接続することも可能である。 This is obtained by removing the inside of the film 5''. In this way, it is also possible to directly connect the electrodes of two opposing semiconductor chips 1.
以上詳細に説明したように、本発明よれば半導
体チツプの占有面積を半分にすることができるの
で半導体装置の小型化が可能となる。 As described in detail above, according to the present invention, the area occupied by a semiconductor chip can be halved, thereby making it possible to downsize the semiconductor device.
第１図は本発明に使用する半導体チツプの平面
図（ａ図）及びａ図のＡ−A′断面図（ｂ図）、第
２図は本発明にかかるリード付きフイルムの平面
図（ａ図）、ａ図のＢ−B′断面図（ｂ図）及びａ
図のＣ−C′断面図（ｃ図）、第３図は本発明の半
導体装置の製造方法を説明する斜視図（ａ図）及
びａ図のＤ−D′断面図（ｂ図）、第４図は本発明
の半導体装置の斜視図、第５図は本発明にかかる
リード付きフイルムの他の例の斜視図、第６図は
本発明にかかるリード付きフイルムの更に他の例
の斜視図である。
１，１′……半導体チツプ、２……半導体基
板、３，３′……絶縁膜、４，４′……バンブ、
５，５′，５″……フイルム、６，６′，６″……第
１面のリード、７，７′，７″……第二の面のリー
ド、８……樹脂、９……スルーホール。
Fig. 1 is a plan view (Fig. a) of a semiconductor chip used in the present invention and a sectional view taken along line A-A' in Fig. A (Fig. b), and Fig. 2 is a plan view of a leaded film according to the present invention (Fig. A). ), B-B' sectional view of figure a (figure b), and a
3 is a perspective view (a) illustrating the method of manufacturing a semiconductor device of the present invention, a sectional view taken along D-D' (b) of FIG. 4 is a perspective view of a semiconductor device according to the present invention, FIG. 5 is a perspective view of another example of the leaded film according to the present invention, and FIG. 6 is a perspective view of still another example of the leaded film according to the present invention. It is. 1, 1'... Semiconductor chip, 2... Semiconductor substrate, 3, 3'... Insulating film, 4, 4'... Bump,
5, 5', 5''...Film, 6, 6', 6''...Lead on the first side, 7, 7', 7''...Lead on the second side, 8...Resin, 9... Through hole.
Claims (1)
イルムを介して積層され、前記各リードの一端に
はそれぞれ異なるチツプのボンデイングパツドが
接合され、前記各リードの他端は封止樹脂の外部
に突出していることを特徴とする半導体装置。1 A pair of leads of almost the same shape are laminated with a thin insulating film interposed therebetween, one end of each lead is bonded to a bonding pad of a different chip, and the other end of each lead is connected to the outside of the sealing resin. A semiconductor device characterized by a protruding feature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15197377A JPS5483768A (en) | 1977-12-16 | 1977-12-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15197377A JPS5483768A (en) | 1977-12-16 | 1977-12-16 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5483768A JPS5483768A (en) | 1979-07-04 |
| JPS6133258B2 true JPS6133258B2 (en) | 1986-08-01 |
Family
ID=15530260
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15197377A Granted JPS5483768A (en) | 1977-12-16 | 1977-12-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5483768A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4862322A (en) * | 1988-05-02 | 1989-08-29 | Bickford Harry R | Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projecting outwardly from therebetween |
| KR920702024A (en) * | 1990-03-15 | 1992-08-12 | 세끼사와 요시 | Semiconductor device with multiple chips |
| US5530292A (en) * | 1990-03-15 | 1996-06-25 | Fujitsu Limited | Semiconductor device having a plurality of chips |
| JPH061762U (en) * | 1992-06-08 | 1994-01-14 | 日野自動車工業株式会社 | Exhaust gas recirculation system for diesel engines |
-
1977
- 1977-12-16 JP JP15197377A patent/JPS5483768A/en active Granted
Non-Patent Citations (1)
| Title |
|---|
| IBM TECHNICAL DISCLOSURE BULLETIN * |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5483768A (en) | 1979-07-04 |
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