JPH04206654A - Lead frame and semiconductor device - Google Patents

Lead frame and semiconductor device

Info

Publication number
JPH04206654A
JPH04206654A JP33048290A JP33048290A JPH04206654A JP H04206654 A JPH04206654 A JP H04206654A JP 33048290 A JP33048290 A JP 33048290A JP 33048290 A JP33048290 A JP 33048290A JP H04206654 A JPH04206654 A JP H04206654A
Authority
JP
Japan
Prior art keywords
plate
power supply
lead
ground
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP33048290A
Other languages
Japanese (ja)
Other versions
JP2569217B2 (en
Inventor
Kiyoaki Tsumura
清昭 津村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2330482A priority Critical patent/JP2569217B2/en
Publication of JPH04206654A publication Critical patent/JPH04206654A/en
Application granted granted Critical
Publication of JP2569217B2 publication Critical patent/JP2569217B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Abstract

PURPOSE:To achieve low inductance by providing a power source plate and a ground plate by extending to a separate layer from a lead frame made of a nonmagnetic substance. CONSTITUTION:A body of a lead frame is formed of a die pad 1 of a predetermined pattern from one plate of Cu alloy, hanging leads 7, inner leads 2, and a frame. A power source plate 31 and a ground plate 32 are adhered by one pair for one piece of a frame through an insulator layer 41 having an adhesive layer from the lower surface of the leads 2. Then, conductive plates 61, 62 are simultaneously adhered from above the leads 2 to a position opposed to the previous plate 31 and the plate 32 through an insulating layer 51 to form a conductive layer of a multilayer structure. The nonmagnetic material has low inductance even in several 100MHz band. Thus, the frame having excellent electric characteristics can be obtained.

Description

【発明の詳細な説明】 ［産業上の利用分野コ この発明は、リードフレームおよび半導体装置に関し、
さらに詳しくいうと、高出力、高周波の半導体素子の組
立のためのリードフレームおよびこれを適用した半導体
装置に関するものである。[Detailed Description of the Invention] [Industrial Application Field] This invention relates to lead frames and semiconductor devices,
More specifically, the present invention relates to a lead frame for assembling high-output, high-frequency semiconductor elements, and a semiconductor device using the lead frame.

［従来の技術］ 第５図は、１９８９ジヤパンエしクトロニックマニファ
クチュアリングテクノロシイ　シンポジラム（１９８９
Ｊａｏａｎ　Ｅｌｅｃｔｒｏｎｉｃ　Ｍａｎｕｆａｃｔ
ｕｎｉｇ　Ｔｅ−ｃｈｎｏｌｏｇｙ　Ｓｙｎｐｏｓｉｕ
ｍ）、講演番号Ｂ４−２．＾ｐｒ　、１９８９”マルチ
−レイヤモルデッドプラスチ・ンクノ＜ラゲージ゛’　
（Ｍｕｌｔｉ−Ｌａｙｅｒ　Ｍｏ１ｄｅｃｌ　Ｐｌａｓ
ｔｉｃ　Ｐａｃｋａｇｅ）に開示された従来のリードフ
レームを示し、図において、（２）はインナーリード、
（３１）は電源プレート、＜３２）はグランドプレート
である。（４）はポリイミドフィルムで、電源プレート
（３１）をインナーリード（２）に、またグランドプレ
ー）　（３２）を電源プレート（３１）に接着させる。[Prior art] Figure 5 shows the 1989 Japan Electronic Manufacturing Technology Symposium (1989
Jaoan Electronic Manufacturer
unig Te-chnology Synposiu
m), lecture number B4-2. ^pr, 1989 “Multi-layer molded plastic baggage”
(Multi-Layer Mo1decl Plus
tic package), and in the figure, (2) is an inner lead,
(31) is a power supply plate, and <32) is a ground plate. (4) is a polyimide film that adheres the power supply plate (31) to the inner lead (2) and the ground play (32) to the power supply plate (31).

第６図は、同じく上記リードフレームで組立てた半導体
装置であり、図において、（８）は半導体素子、（８１
）は電源電位をもつ電源パッド、（８２）はグランド電
位をもつグランドバッド、（８３）は信号系の電極パッ
ドである。FIG. 6 shows a semiconductor device similarly assembled using the above lead frame, and in the figure, (8) is a semiconductor element, (81
) is a power pad with a power supply potential, (82) is a ground pad with a ground potential, and (83) is a signal system electrode pad.

電源バッド（８１）は電源プレート（３１）に＾Ｕワイ
ヤ（９）で結線されている。グランドパッド（８２）は
グランドプレート（３２）に＾Ｕワイヤ（９）で結線さ
れている。The power supply pad (81) is connected to the power supply plate (31) with a ^U wire (9). The ground pad (82) is connected to the ground plate (32) with a U wire (9).

信号系の電極バッド（８３）はインナーリード（２）に
＾Ｕワイヤ（９）で結線されている。The signal system electrode pad (83) is connected to the inner lead (2) with a U wire (9).

次に、製造方法について説明する。まず、リードフレー
ムの本体は、Ｃｕ合金１枚板から、金型ノくンチらしく
は、化学薬品による工・・ノチンクにより要求するパタ
ーンを形成する。とりわけ、イシ＋−リー１〜（２）の
先端は、フし−ム中心に向か−〉て細・くなり、近年ピ
ン数の増加に伴い、加工限界に来ている。その後、イン
ナーリード（２）の下面から接着剤層を有するポリイミ
ドフィルムを介して、Ｃｕ合金で製造された電源プレー
トとり°ランドプレートを接着させ、電源プレー＋１３
１）の端子（３１ａ）とインナーリード（２）出端子（
２ｂ）を電気溶接し、また、グランドプレート（３２）
の端子（３２ａ）とインナーリード（２）の端子（２ａ
）を電気溶接することで、電位を取出せる構造にしてい
る。次に半導体素子（８）をグランドプレート（３１）
上に半日または樹脂などのダイボンド材を介して接合し
、ワイヤボンドにより結線を行う。通常、リードフレー
ム全体が３００℃程度に加熱された状態で＾Ｕワイヤの
先端を溶融してＡｕボールを形成し、これを電極パッド
（８３）に加圧するとともに、超音波振動を印加するこ
とにより、Ａｕボールと電極パソＦ（８３）の＾１合金
を生成して接合を完了する。その後、＾Ｕワイヤを繰り
出し、ワイヤ自体をインナーリーＦ（２）上に同じく、
加圧するとともに、超音波振動を印加する二とにより、
＾ＵワイヤとインナーリーＦ（２）上のメツキ（ΔＵ、
八ＢへＣｕ）との合金を生成して接合を完了する。これ
を超音波熱圧着によるワイヤホントと呼んている。この
方法で、電源バ／トと電源プレート、グランドパッドと
グランドプレー１・、そして信号系の電極パッドとイン
ナーリードをワイヤボンドする。その後、全体をエポキ
シ系樹脂で封止し、外形リードのフォーミンク加工を施
して、半導体装置として完成する。Next, the manufacturing method will be explained. First, the main body of the lead frame is made from a single Cu alloy plate, and the required pattern is formed by a process using chemicals, similar to a die process. In particular, the tips of the anchors 1 to (2) become thinner toward the center of the frame, and as the number of pins has increased in recent years, they have reached their processing limit. After that, a power plate and a land plate made of Cu alloy are adhered to the lower surface of the inner lead (2) via a polyimide film having an adhesive layer, and the power plate +13
1) terminal (31a) and inner lead (2) output terminal (
2b) and also the ground plate (32)
The terminal (32a) of the inner lead (2) and the terminal (2a) of the inner lead (2)
) is electrically welded to create a structure that allows the potential to be extracted. Next, place the semiconductor element (8) on the ground plate (31).
It is bonded to the top using a die-bonding material such as resin or resin, and connections are made by wire bonding. Usually, with the entire lead frame heated to about 300°C, the tip of the U wire is melted to form an Au ball, which is then pressed against the electrode pad (83) and ultrasonic vibration is applied. , a ^1 alloy of the Au ball and the electrode Paso F (83) is produced to complete the bonding. After that, let out the ^U wire and place the wire itself on the inner Lee F (2) in the same way.
By applying pressure and ultrasonic vibration,
^U wire and plating on inner Lee F (2) (ΔU,
8B to form an alloy with Cu) to complete the bonding. This is called wire bonding using ultrasonic thermocompression bonding. Using this method, the power supply board and power supply plate, the ground pad and ground plate 1, and the signal system electrode pad and inner lead are wire-bonded. Thereafter, the entire device is sealed with epoxy resin, and the external leads are formed to form a semiconductor device.

［発明が解決しようとする課題］ 従来のリードフレームおよび半導体装置は以上のように
構成されているので、電源プレートとインナーリードま
たはグランドプレートとインナーリードを電気溶接する
ため、リードフレーム自体の反りが発生した安定した品
質を確保てきす、高い製造コストが必要であった。また
、通常のり−トフレームの下に電源プレートとグランド
プレートを接着するため、モールド樹脂との密着力を低
下させてパラゲージクラ・・／りなとを生し、信頼性を
低下させるなどの問題点かあった。[Problems to be Solved by the Invention] Conventional lead frames and semiconductor devices are configured as described above, and since the power supply plate and the inner lead or the ground plate and the inner lead are electrically welded, warping of the lead frame itself is avoided. In order to ensure stable quality, high manufacturing costs were required. In addition, because the power supply plate and ground plate are glued under the normal glue frame, the adhesion with the molding resin is reduced, resulting in paragauge cracks and other problems, such as reduced reliability. there were.

この発明は上記のような問題点を解消するためになされ
たちのて、第一の発明は、信号系と電源をクランドのイ
ンダクタンスを低下させたままで、安定ヒな品質と安価
な製造コストのり−トフレームを得ることを目的とする
。This invention was made to solve the above-mentioned problems, and the first invention is to provide stable quality and low manufacturing cost by keeping the inductance of the signal system and power source low. The purpose is to obtain a frame.

さらに第二の発明は、パッケージクラックと防止すると
ともに電源系の雑音を小さくシ、信号系に対してはクロ
ストークを押えた半導体装置を得ることを目的とする。A further object of the second invention is to obtain a semiconductor device that prevents package cracks, reduces noise in the power supply system, and suppresses crosstalk in the signal system.

［課題を解決するための手段］ この発明の第一の発明に係るリードフレームは、材質を
Ｃｕ合金にして電源プレートとグランドプレートをリー
ドフレームとは別層に広げて設けたものである。[Means for Solving the Problems] A lead frame according to a first aspect of the present invention is made of a Cu alloy and has a power supply plate and a ground plate spread out in separate layers from the lead frame.

第二の発明に係る半導体装置は、信号系のインナーリー
ドを絶縁体層を介して電源プレートとグランドプレート
て侠んた多層構造にしたちのてある。In the semiconductor device according to the second invention, the inner lead of the signal system has a multilayer structure including a power supply plate and a ground plate with an insulating layer interposed therebetween.

！作　用二 この発明の第一の発明においては、１，１−１〜フし一
ムの材質であるＣｕ合金は、熱伝導率か高く、非磁性体
であるため、数１００　Ｍ　Ｉｔ　ｚ帯でも低インダク
タンスとなり、放熱性を向上するとともに雑音を低下さ
せる。! Effect 2 In the first aspect of the present invention, the Cu alloy, which is the material of the frame 1,1-1, has a high thermal conductivity and is a non-magnetic material, so it However, the inductance is low, improving heat dissipation and reducing noise.

また、第二の発明においては、絶縁体層は、信号系に対
してストリップラインとなる。Further, in the second invention, the insulating layer serves as a strip line for the signal system.

そして電源電位とグランド電位をイン＋−り一トに伝達
するためにワイヤボンドを行い、信号系インナーリード
を挟んで電源プレートとゲランドブし一トが対面した構
造により、製造も容易で、モールド樹脂の中で応力を発
生することが少なくなる。Wire bonding is then performed to transmit the power supply potential and ground potential to the input terminals, and the structure in which the power supply plate and the Gerando board face each other with the signal system inner lead in between makes manufacturing easy and molded resin. This will reduce the stress that will be generated inside.

［実施例］ 以下、この発明の一実施例を図について説明する。第１
図において、（１）はダイスパッド、（７）はこのダイ
スパッドをフレームに吊るための吊リード、（２）はイ
ンナーリードで（２１）は電源リード、（２２）はグラ
ンドリードである。（１０）は吊り−ｌ〜・（７゛とイ
ンナーリー１〜（２）を支持するフレーム、（３１）は
電源プＬ、　−１−１〈３２）はゲランドアし−１−５
＜４１１＝。[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
In the figure, (1) is a die pad, (7) is a hanging lead for hanging this die pad on a frame, (2) is an inner lead, (21) is a power supply lead, and (22) is a ground lead. (10) is the frame that supports the hanging -l ~ (7゛ and inner Lee 1~(2)), (31) is the power supply plug L, -1-1 <32) is the gelatin door -1-5
<411=.

（Ｓｌ）は絶縁体層、（４２）　、　（５２）は接着剤
層、（６１八。(Sl) is an insulator layer, (42), (52) is an adhesive layer, (618).

（６２）は導電プレートで、電源プレート（３１）とク
ラン１ヘプレート（３２）は絶縁体層（４１）を介して
イ；ナーリーＦ（２）の下に接着されている。導電プレ
ート（６）は絶縁体層（５１）を介してインナーリーＦ
（２４の上に接着されている。(62) is a conductive plate, and the power supply plate (31) and the crank 1 plate (32) are bonded to the lower part of the Nari F (2) via the insulating layer (41). The conductive plate (6) is connected to the inner F through the insulator layer (51).
(It is glued on top of 24.

第２図は他の実施例を示し、口において、（１）はグラ
ンドプレートを兼ねるダイスパソｌ’、（３）は電源プ
レートである。FIG. 2 shows another embodiment, in which (1) is a dice paso l' which also serves as a ground plate, and (3) is a power supply plate.

第３図、第４図はそれぞれ第１図、第２図のリードフレ
ームを使って組立な半導体装置である。FIGS. 3 and 4 show semiconductor devices assembled using the lead frames shown in FIGS. 1 and 2, respectively.

次に製造方法について説明する。リードフレームの本体
は従来と同様、Ｃｕ合金１枚板から金型パンチもしくは
エツチングにより、要求するパターン、即ち、ダイスパ
ッド（１）、吊リード（７）、インナーリード（２）、
フレームを形成する。その後、イ〉ナーリード（２）の
下面から接着剤層を有する絶縁体層（４１）を介して、
Ｃｕ合金て製造Ｌ　ｆ、−電源プレート（３１）とグラ
ン１〜プレート（３２）をフレームの１片に対して、１
対ずつ接着させる。以に、インナーリードの上面からも
接着剤層を有する絶縁体層（５１）を介して、ＣＬＩ合
金で製造した導電プし−１（６１）、（６２）を先の電
源プレート（３１）とクランドプレート（３２）と対面
する位置に接着させる。こ二で、ダイスパッド（１）と
グランドプレート（３２）は一体止して、両方を兼用し
たものでも良い。これがリードフレームの製造方法であ
る。Next, the manufacturing method will be explained. As before, the main body of the lead frame is made from a single Cu alloy plate by die punching or etching to form the required pattern, namely, die pad (1), suspension lead (7), inner lead (2),
form a frame. After that, from the bottom surface of the inner lead (2) through the insulator layer (41) having an adhesive layer,
Manufactured using Cu alloy Lf, - Power supply plate (31) and Gran 1 to plate (32) 1 piece for one piece of frame.
Glue each pair. Above, conductive plates-1 (61) and (62) made of CLI alloy are connected to the power supply plate (31) from the upper surface of the inner lead through the insulator layer (51) having an adhesive layer. It is glued at a position facing the clamp plate (32). In this case, the die pad (1) and the ground plate (32) may be integrally fixed to serve as both. This is the method for manufacturing lead frames.

このリードフレームのダイスパッド（１）の上に半日ま
たは樹脂などのダイホント材を介して半導体素子（８〉
を接合し、半導体素子（８）の電極パッド（８３）とイ
ンナーリード（２）をへＵワイヤにより超音波熱圧着ワ
イヤボンドする。電源パッド（８１）は電源プレー）　
（３１）にワイヤボンド後、電源リード（２１）に再度
ワイヤボンドされる。グランドパッド（８２）はグラン
ドプレー）　（３２）または電源プレート（３）にワイ
ヤボンド後、グランドリード（２２）に再度ワイヤボン
ドされる。その後、電源リード（２１）と導電プし−１
−（６２）をワイヤボンドし、グラン１〜リード（２２
）と導電プレート（６１）をワイヤボンドして、信号系
のインナーリード（２）か絶縁体層を介して、電源プレ
ートとグランドプレートに挟まれた多層構造にし、全体
をエポキシ系樹脂て封止して外形リードのフォーミンク
加工を施して、半導体装置として完成する。A semiconductor element (8>
The electrode pads (83) and inner leads (2) of the semiconductor element (8) are bonded by ultrasonic thermocompression wire using a U wire. Power pad (81) is a power play)
After wire bonding to (31), wire bonding is performed again to the power supply lead (21). After the ground pad (82) is wire-bonded to the ground play (32) or power supply plate (3), it is wire-bonded again to the ground lead (22). Then, connect the power lead (21) and conductive wire to -1.
- (62) wire-bonded, grand 1 to lead (22)
) and the conductive plate (61) are wire-bonded to create a multilayer structure sandwiched between the power supply plate and the ground plate via the signal system inner lead (2) or the insulator layer, and the whole is sealed with epoxy resin. Then, the external leads are formed and processed to complete the semiconductor device.

なお、上記実施例では、イ〉ナーリードを挟んて、ゲラ
ンドブし−１・と電源プレー１−が交互に並んだが、イ
ンナーリードの下全体をグランドプレート、インナーリ
ードの上全体を電源プレートとなる構造でも良い。In the above embodiment, the Guerande plate 1 and the power supply plate 1 are arranged alternately with the inner lead in between, but the structure is such that the entire bottom of the inner lead serves as the ground plate, and the entire top of the inner lead serves as the power supply plate. But it's okay.

また、インナーリード上の導電プレートは信号系のイン
ナーリードの特性に応して、ワイヤボンドの方法を変え
て、電位を変えても良い。Further, the electric potential of the conductive plate on the inner lead may be changed by changing the wire bonding method depending on the characteristics of the inner lead of the signal system.

［発明の効果］ 以上のように、この発明の第一の発明によれば、Ｃｕ合
金を使って、ダイスパッドとインナーリードを形成し、
このインナーリードの下にＣｕ合金の電源プレー１−と
ゲランドブし一トを広げた多層構造にしたので、従来技
術の延長で、安定した品質で安価に、低インダクタンス
で熱伝導率の高いり一トフレームを得られる効果がある
。[Effects of the Invention] As described above, according to the first aspect of the present invention, the die pad and the inner lead are formed using a Cu alloy,
The multi-layer structure is made by expanding the Cu alloy power supply plate 1- and Guerande plate under this inner lead, so by extending the conventional technology, it is possible to achieve stable quality at low cost, low inductance, and high thermal conductivity. It has the effect of obtaining a frame.

また、第二の発明によれは、ワイヤボ〉トて導電ブし−
１−の電位わ設定し、信号系のインナーリードを絶縁体
層を介して電源プレートとグランドプレートて挟んた構
造にしたのて、クロストークを抑えた半導体装置を得ら
れる効果かある。また同時に、モールド樹脂の中で応力
を発生しにくい構造になり、パッケージクランクを防止
する効果がある。Further, according to the second invention, the wire bolt can be used as a conductive block.
By setting a potential of 1- and having a structure in which the inner lead of the signal system is sandwiched between a power supply plate and a ground plate via an insulating layer, it is possible to obtain a semiconductor device with suppressed crosstalk. At the same time, it has a structure that makes it difficult for stress to occur in the molding resin, which has the effect of preventing package cranking.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は第一の発明の一実施例の正面図（ａ）と断面図
（ｂ）、第２図は他の実施例の正面図（、）と断面図、
／第３図は第二の発明の一実施例の正面図（ａ）と断面
図（ｂ）、第４図は他の実施例の正面図（、）と断面図
（ｂ）、第５図は従来のリードフレームの分解斜視図、
第６図は従来の半導体装置の正面図である。 （１）はダイスパ・／ド、（２）　　　・インナーリー
ド、（３）は電：原ブＬ−−１へ、（３２）は７ラン１
〜フ・シート、（４１）　、　（５１）は絶縁体層、（
６）は導電プレート、（８）は半導体素子、（８１）は
電源パッド、（８２）はクランドパＩト、（８３）は信
号系の電極バ・／ト、（９）は＾Ｕワイヤ。 なお、各図中、同一符号は同一また（ま相当部分を示す
。 代　　理　　人　　　　　曾　　我　　道　　照第１図 （（］） ｂ、導ｌノルート 第２図 （ａ） 第３図 ９：Ａｕ７７ｆ’＃ 第４図 ３１３２　　　ン 手続補正書 平成　３年　９月２６日1 is a front view (a) and a sectional view (b) of one embodiment of the first invention, FIG. 2 is a front view (,) and a sectional view of another embodiment,
/Figure 3 is a front view (a) and sectional view (b) of one embodiment of the second invention, Figure 4 is a front view (,) and sectional view (b) of another embodiment, and Figure 5 is an exploded perspective view of a conventional lead frame.
FIG. 6 is a front view of a conventional semiconductor device. (1) is die spa / de, (2) - inner lead, (3) is electric: to original block L--1, (32) is 7 run 1
〜F sheet, (41), (51) are insulator layers, (
6) is a conductive plate, (8) is a semiconductor element, (81) is a power supply pad, (82) is a ground pad, (83) is a signal system electrode bar/to, (9) is a U wire. In addition, the same reference numerals in each figure indicate the same or corresponding parts. # Figure 4 3132 Written amendment of procedure dated September 26, 1991

Claims (4)

【特許請求の範囲】[Claims] （１）半導体素子を固定するダイスパッドと、前記半導
体素子の信号系電極パッドを結線するインナーリードと
、電源パッドを結線する電源プレートと、グランドパッ
ドを結線するグランドプレートとを備えたリードフレー
ムにおいて、前記インナーリードの下に絶縁体層を介し
て、前記電源プレートと前記グランドプレートを配し、
かつ、前記インナーリードの上に絶縁体層を介して導電
プレートを配してなることを特徴とするリードフレーム
。(1) In a lead frame including a die pad for fixing a semiconductor element, an inner lead for connecting a signal system electrode pad of the semiconductor element, a power plate for connecting a power supply pad, and a ground plate for connecting a ground pad. , disposing the power supply plate and the ground plate under the inner lead with an insulating layer interposed therebetween;
A lead frame further comprising a conductive plate disposed on the inner lead with an insulating layer interposed therebetween. （２）グランドプレートおよび電源プレートのいずれか
がダイスパッドと一体構造になっている請求項（１）記
載のリードフレーム。(2) The lead frame according to claim (1), wherein either the ground plate or the power supply plate has an integral structure with the die pad. （３）ダイスパッド、インナーリード、電源プレート、
グランドプレートおよび導電プレートの材質がＣｕ合金
である請求項（１）記載のリードフレーム。(3) Die pad, inner lead, power plate,
The lead frame according to claim 1, wherein the material of the ground plate and the conductive plate is a Cu alloy. （４）リードフレームのダイスパッドに固定後、信号系
電極パッドとインナーリードを金属ワイヤで結線した半
導体素子と、 電源プレートに結線後、電源リードに結線された電源パ
ッドと、グランドプレート、グランドリードに結線後、
電源プレートに対面する導電プレートと前記グランドリ
ードを結線してなるグランドパッドと、 全体を封止したエポキシ系樹脂と、 を備えてなる半導体装置。(4) After fixing to the die pad of the lead frame, the semiconductor element is connected to the signal system electrode pad and the inner lead with metal wire, and after being connected to the power supply plate, the power supply pad is connected to the power supply lead, the ground plate, and the ground lead. After connecting to
A semiconductor device comprising: a ground pad formed by connecting a conductive plate facing a power supply plate and the ground lead; and an epoxy resin sealed entirely.
JP2330482A 1990-11-30 1990-11-30 Semiconductor device Expired - Fee Related JP2569217B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2330482A JP2569217B2 (en) 1990-11-30 1990-11-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2330482A JP2569217B2 (en) 1990-11-30 1990-11-30 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH04206654A true JPH04206654A (en) 1992-07-28
JP2569217B2 JP2569217B2 (en) 1997-01-08

Family

ID=18233119

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2330482A Expired - Fee Related JP2569217B2 (en) 1990-11-30 1990-11-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2569217B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0878610A (en) * 1994-08-31 1996-03-22 Nec Corp Semiconductor device
EP0847087A3 (en) * 1996-12-04 1999-11-17 Texas Instruments Incorporated A leadframe
DE19755954B4 (en) * 1997-04-18 2005-04-21 LG Semicon Co., Ltd., Cheongju Leadframe structure, this semiconductor device using and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0878610A (en) * 1994-08-31 1996-03-22 Nec Corp Semiconductor device
EP0847087A3 (en) * 1996-12-04 1999-11-17 Texas Instruments Incorporated A leadframe
DE19755954B4 (en) * 1997-04-18 2005-04-21 LG Semicon Co., Ltd., Cheongju Leadframe structure, this semiconductor device using and manufacturing method thereof

Also Published As

Publication number Publication date
JP2569217B2 (en) 1997-01-08

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