JPS6133211B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a color display circuit for displaying character and graphic information in color in a computing device or the like.

In recent years, with the rapid development of LSI technology, microcomputers have appeared in which the central processing circuit (hereinafter abbreviated as CPU) of a computer is integrated into a single LSI, and the conventional general-purpose digital IC system has become
We are starting to move towards CPU-centric systems. In addition to the CPU, such a system also includes a playback-only memory circuit (hereinafter referred to as program ROM) that stores CPU processing procedures (programs), and a CPU
Temporarily store data during processing or program
The main components are a rewritable memory circuit (hereinafter referred to as data RAM) that can take the place of a ROM, and an input/output circuit.

FIG. 1 is a block diagram showing an example of the above-mentioned configuration, and shows a character display device. In this figure, 1 is the CPU, 2 is the clock generation circuit that generates the clock signal for CPU 1, 3 is the data RAM, 4 is the program ROM, and 5 is the data
A refresh control circuit that performs a refresh operation at a constant cycle regardless of reading and writing from the CPU 1 so that the contents of the RAM 3 are not lost; 6 an address switching circuit that supplies an address to be refreshed to the data RAM 3 during refresh; 7 is a character code display circuit capable of displaying character code information, and 8 is a display device typified by a cathode ray tube. Further, 13 is a signal path for exchanging data between the CPU 1 and each circuit, that is, a data bus, and 14 is a signal path for supplying address signals from the CPU 1 to each circuit, that is, an address bus.
6 is a signal path for supplying a clock signal generated from the clock generation circuit 2; 17 is a signal path for supplying a refresh address signal generated from the refresh control circuit 5 to the address switching circuit 6; and 18 is a signal path for supplying a refresh address signal generated from the refresh control circuit 5. A signal path for supplying a refresh request signal is shown. The character code display circuit 7 clocks a display timing pulse generation circuit 71 that generates a synchronization signal of a television signal and an address signal for display, an address bus 14, and a display timing pulse signal path 15 from the display timing pulse generation circuit 71. an address switching circuit 72 which is switched by the signal a supplied from the generation circuit 2 via the clock signal path 16; a memory circuit (hereinafter referred to as display RAM) 73 which has a relative positional relationship with the display screen and stores character code information; A reproduction-only memory circuit (hereinafter referred to as character pattern generation ROM) 74 that stores character code patterns corresponding to this character code information in advance, and a parallel signal that converts parallel signals from the character pattern generation ROM 74 into serial signals. It is composed of a serial conversion circuit 75. This character display circuit 7 corresponds to the output circuit of the CPU 1, and in an actual character display device, input circuits such as a keyboard are generally connected via a data bus 13 and an address bus 14, but the present invention It is omitted because it has nothing to do with the essence of .

FIG. 2 is a diagram showing an example of the address assignment of the system shown in FIG. FIG. 3 is a diagram illustrating timing relationships among signal paths;

First, the circuit shown in Figure 1 plays an important role.
The operation of CPU1 will be explained. In FIG. 1, a CPU 1 is a central processing circuit of a so-called microcomputer. The CPU 1 can normally perform arithmetic processing on multiple bits at the same time, but for convenience of explanation, it is assumed here that the CPU is capable of 8-bit parallel arithmetic processing, and the address bus 14 has 16 parallel lines output. In other words, CPU1 is from address 0 to address 2 ¹⁶ - 1 = 65535 (expressed in hexadecimal)
Since the address is FFFF and is easy to represent, it is possible to output address signals up to (hereinafter address representation will be in hexadecimal). Moreover, the data bus 13 is eight parallel lines, and runs from the CPU 1 to each memory circuit (program ROM 4, data RAM 3, display RAM 7).
This is a signal path that sends parallel 8-bit signals to CPU 3) and vice versa.

Generally, in a microcomputer system, a CPU 1 and each circuit are connected by the same address bus 14 and the same data bus 13, as shown in FIG. Therefore, in order to separate each circuit, a different address is assigned to each circuit. FIG. 2 shows an example of this address assignment. In Figure 2, program ROM 4 has a total of 4096 addresses from (F000) ₁₆ to (FFFF) ₁₆ .
The address and data RAM 3 are from (0000) ₁₆ to (0FFF) ₁₆ , a total of 4096 addresses, and display RAM 7.
3 has the total from (8000) _16th to (83FF) _16th
Address 1024 has been assigned.

Microcomputers, like regular electronic computers, store programs, so
The ROM 4 stores processing procedures (programs) for operating the system shown in FIG. Program ROM4 is (F000) ₁₆ as shown in Figure 2.
It occupies 4096 addresses from address to (FFFF) ₁₆ , and the stored contents are read out to the data bus 13 according to the address information of the address bus of the CPU 1. This memory content is taken in by the CPU 1, decoded as an instruction, and operates this system. That is, a program counter is normally provided inside the CPU 1, and the value indicated by this counter determines the address of the program ROM 4 containing the instruction being executed.

Next, this address is output to the address bus 14, and the data stored at that address in the program ROM 4 is taken into the CPU via the data bus 13. CPU1 decodes this data as an instruction,
It operates the entire system by changing the storage contents of the data RAM 3 and the display RAM 73, and by exchanging data with other input/output circuits. The relationship between the clock signal, address bus, and data bus during operation is explained in the fourth section.
As shown in the figure. FIG. 4a shows that the CPU is
1, b is the address signal on signal path 14, and c is the data signal on signal path 13. Since the address signal b is output from the CPU 1 in one direction, the address advances within the _T1 period with a certain time delay from the falling edge of the clock signal, but the data signal c is a bidirectional signal, so it is mainly
The operation is such that output signals are output only during the _T2 period to prevent output signals from competing with each other on the data bus 13.

The above is an explanation of the general operation of the CPU 1. Next, the character code display circuit 7 that displays the character code information taken into the CPU 1 on the display 8 will be explained. This circuit is a well-known circuit known as a cycle steal display system.
The feature of this method is that no special processing is required for the CPU 1 to access the display RAM 73, and character codes can be displayed stably. In other words, as shown in Figure 4, focusing on the fact that the data signal from CPU 1 is sent and received only during the T ₂ period of the clock signal, in the T ₁ period, the data signal is sent and received from CPU 1 and the display signal.
This is a method in which the RAM 73 is separated by an address switching circuit 72, a display address signal from the display timing pulse generation circuit 71 is supplied to the display RAM 73 via the address switching circuit 72, and character code information stored therein is read out. . This cycle-steal display method is based on the bus method of the CPU 1.
There is a difference between asynchronous bus type CPUs such as the American Intel CPU 8080 - whether or not the clock generation circuit 2 requires clock stretching, but regardless of the CPU used, the display can be used even during display.
It is an excellent display system that allows access to RAM73.

The state of the combined address signal supplied to the display RAM 73 at this time is shown in FIG. 4d. The read character code information is supplied to a character code pattern generation ROM 74 that stores character code patterns in advance, as in other display systems. Further, a display address signal from the display timing pulse generation circuit 71 is also simultaneously supplied to the character code pattern generation ROM 74, and character code pattern information is read out. The read character code pattern information is supplied to the parallel-to-serial conversion circuit 75,
The signal is converted into a signal that can be input to the display 8 and output.

FIG. 3 shows an example of an image displayed on the display 8 in this way.
A total of 1024 character code pattern information can be displayed, 16 in the vertical direction. The character code pattern information displayed here is shown in the display RAM 7 with a total of 1024 addresses from (8000) ₁₆ to (83FF) ₁₆ in Figure 2.
It is configured to have a one-to-one correspondence with the character code information stored in No. 3. In other words, if the location (1, 1) in Figure 3 corresponds to address (8000) ₁₆ , the display timing pulse is set so that address (8000) ₁₆ is read out at the location (1, 1) in Figure 3. A generation circuit 71 supplies a display address signal to a display RAM 73.

The above is an overview of the character display circuit 7. Next, the refresh operation will be described. In FIG. 1, when the data RAM 3 has a small capacity, a static RAM that does not require a refresh circuit 5 or an address switching circuit 6 is used, but static RAM is expensive and unsuitable for large capacity applications. Therefore, if you want to obtain a large-capacity memory circuit at a lower cost, you should use a dynamic circuit as shown in Figure 1.
RAM will be used. But dynamic
RAM loses its memory contents if it is not accessed for a certain period of time, so the CPU
It is necessary to sequentially refresh all addresses at a certain fixed period (refresh period), regardless of read/write operations from/to.

This operation will be explained using FIG. The refresh control circuit 5 has an oscillator inside, and outputs a refresh request signal to the refresh request signal path 18 at regular intervals. A part of the address bus 14 is separated by the address switching circuit 6, and the refresh request signal is output from the refresh control circuit 5. Connected to refresh address signal path 17. This refresh request signal is also supplied to the data RAM 3 to create a refresh operation state in which no data information is output to the data bus 13. The reason why refresh addresses are supplied to only some of the addresses supplied to the data RAM 3 is that in commercially available dynamic RAM, it is not necessary to refresh all addresses sequentially, but several tenths of the addresses are refreshed sequentially. This is because the structure is sufficient. During refresh operation, the switching information of the address switching circuit 6 is supplied to the CPU 1 via the data bus, and the data
Prohibit access to RAM3. As a result
The actual processing speed of the CPU 1 decreases.

Next, an example of a circuit for displaying a character code pattern in color, based on the character display device for black and white display shown in FIG. 1, will be shown. FIG. 5 shows an address switching circuit 76 in addition to the character code display circuit 7 in FIG.
This is an example of a conventional circuit in which a RAM 77 and a color signal synthesis circuit 78 are added to enable color display, and the same parts as in FIG. 1 are given the same reference numerals. The color RAM 77 is for display as already explained.
It is configured similarly to RAM73, and its address is the second
It can be placed anywhere in the unused addresses in the address allocation example shown in the figure. However, in general, 1024 addresses are allocated consecutively starting from a specific address, for example from (9000) ₁₆ to (93FF) ₁₆ . This color RAM77 has
The address signal b from the CPU 1 and the display address signal from the display timing pulse generation circuit 71 are switched and alternately supplied by the address switching circuit 76 as address signals. In this example, during the _T1 period when the display address signal is supplied, a signal specifying addresses (9000) ₁₆ to (93FF) ₁₆ is supplied to the color RAM 77, and color information is read out. The read color information is supplied to a color signal synthesis circuit 78. moreover,
The capacity of the color RAM 77 is correlated with the display surface of the display 8 as in the case of the display RAM 73, and in the case of the information display shown in FIG.
It is configured to have a capacity N times 1024 bits. At this time, since N bits of color information can be obtained for each character, in principle 2 ^N colors can be displayed. In the color signal synthesis circuit 78,
This color information and the output signal from the parallel-to-serial conversion circuit 75 are combined into a signal that can be displayed in color and supplied to the display 8 to obtain a color image.

Conventional examples of character display devices for monochrome display and color display have been described above, but the conventional devices have the disadvantage of requiring a large number of circuits and being expensive. Especially in the case of color display, color RAM and display RAM
Because it requires two independent systems of small-capacity RAM and large-capacity data RAM, RAM alone is expensive, and conversely, if dynamic RAM is used to reduce the cost, processing speed will decrease. Ta.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above, to provide a color display circuit capable of color display, and to be used in computer systems and the like with an inexpensive configuration. In order to achieve this purpose, in the present invention, the large-capacity data RAM is composed of at least two systems of RAM, and a part of one system of the data RAM is used as a display RAM,
A part of the other data RAM is used as color RAM.
Furthermore, if there are data RAMs from the third system onwards, these are used for data storage. Address signals from the CPU and display timing generation circuit, which are switched in synchronization with the CPU's clock a, are simultaneously (commonly) supplied to all of these RAM systems, and the address signals are sent to the CPU as address signals.
When an address signal is supplied from the address signal, each system of RAM operates independently according to the signal content, and when a display address signal is supplied as an address signal, only the above two systems of RAM operate to process the signal. output, and the other RAM systems are in a refresh state. By doing so, the RAM circuit can be constructed using only a large capacity RAM, which is cheaper per bit than the small capacity RAM conventionally required. Furthermore, even when using dynamic RAM as data RAM, the dynamic
The RAM's unique refresh circuit can be omitted, and the overall device can be constructed at low cost.

Hereinafter, the present invention will be explained in more detail with reference to the drawings. FIG. 6 is a block diagram showing an embodiment of the present invention, showing an example in which the data RAM is divided into two systems.
The same reference numerals are used for the same parts as in FIG. 1 or FIG. 5. In the figure, 20 is a timing control circuit that generates signals for controlling the read/write timing of the RAM and the operation of the buffer circuit, and 21 and 22 are buffer circuits. 7 and 8 are diagrams each showing an example of address allocation in the system shown in FIG. 6. Display RAM of the present invention shown in FIG.
73A and color RAM 77A are RAMs having a capacity many times that required in the conventional apparatus shown in FIGS. 1 or 5. That is, in this embodiment, each RAM has a capacity of 4 kilobytes, as shown in the address allocation example in FIG.
Of these, 1 kilobyte is allocated for storing character code information and color information, and the remaining 3 kilobytes are for storing data of CPU1, that is, data storage.
It is configured to be used as RAM.

Now, in FIG. 6, the display RAM 73A has an address signal b from the CPU 1 and a display address signal from the display timing generation circuit 71 as described in the conventional example of FIG. 1 and as shown in FIG. 4d. are alternately switched and supplied at the clock cycle of CPU1, that is, every character display period, and the same signals as these address signals are used for color.
It is also supplied to RAM77A. Also, from the timing control circuit 20, as shown in FIG.
During the _T2 period when the address signal b of 1 is supplied as an address signal, the display RAM 73A and the color
A control signal is output so that the RAM 77A operates separately at different addresses, while during the _T1 period when a display address signal is supplied as an address signal, the display RAM 73A and color RAM 77A operate so that their addresses overlap. Such control signals are output to the display RAM 73A and the color RAM 77A.

Further, the timing control circuit 20 outputs a control signal to the buffer circuit 21 to turn on the buffer circuit 21 when the display RAM 73A is in the read state during the _T2 period, and also outputs a control signal to turn on the buffer circuit 21 when the color RAM 77A is in the read state. In this case, a control signal for turning on the buffer circuit 22 is simultaneously output to the buffer circuit 22. In addition, the buffer circuits 21 and 22 are circuits whose outputs can take values in three states: high impedance, high level, and low level, and are generally called 3-state buffers, and are OFF outside of the above period, i.e. It is a high impedance output.

The timing control of the display RAM 73A and the color RAM 77A will be explained in more detail using the address allocation example shown in FIGS. 7 and 8. Figure 7a shows the case where the display RAM 73A and the color RAM 77A are each ₁ kilobyte _.
(1000) From address ₁₆ to (1FFF) Number ₁₆ is for color.
It is configured as RAM77A. in this case,
The timing control circuit 20 outputs the display RAM 73A at the 4th bit from the top of the address signal of the CPU 1.
and the operation of the color RAM 77A can be determined. In other words, when the fourth bit from the top of the address signal is low level (=0), the display RAM
A control signal for the display RAM 73A is output so that the display RAM 73A operates. Also, when the fourth bit from the top of the address signal is at high level (=1), the color RAM 77A is activated.
Outputs a control signal for RAM77A. Furthermore, during the _T1 period when the address signal for display is supplied as the RAM address signal, the address signal for display is
Control signals are outputted so that both RAM 73A and color RAM 77A work.

Therefore, if the data bus 13 has 8 parallel lines, the display period _T1 has 4096 bits x
A timing control circuit 20 is configured to generate control signals to make the 16-bit configuration equivalent to the 8192-bit×8-bit configuration during the write period _T2 . With this configuration, if the display address signal outputs from address (0000) ₁₆ to address (03FF) ₁₆ , display RAM 7
Character code information and color RAM 77 stored from address 3A (0000) ₁₆ to address ₁₆ (03FF)
The color information stored from (1000) _16th address of A to (13FF) _16th address can be obtained at the same time, and the operation is equivalent to the conventional example shown in FIG. 4.

Furthermore, the areas from (0400) ₁₆ to (0FFF) ₁₆ and from (1400) ₁₆ to (1FFF) ₁₆ have the same function as data RAM 3 in Figure 1, and can be used as data RAM. Can be used. Therefore, with such a configuration, the RAM circuit can be configured using only a large capacity RAM with a low unit price per bit, and the overall cost can be significantly reduced. Furthermore, if you add data RAM and use dynamic RAM for all of these RAMs, you will get the configuration described in patent application No. 53-53491.
It eliminates the need for a refresh circuit specific to dynamic RAM, making it less expensive and at the same time
This eliminates the slowdown in processing speed, which is a disadvantage of RAM.

Figure 8a is an example of another address assignment.
The addresses of RAM 77A are arranged alternately every other address. In this example, the lowest bit of the address signal of CPU 1 is supplied to the timing control circuit 20, and (0000) ₁₆ is used as the display address.
This can be achieved by supplying the address excluding the least significant bit of address ₁₆ (07FF). As a result, there is no need to configure the RAM area that handles data into two separate areas as in the case of Figure 7, and it is possible to use consecutive addresses, making it more efficient.
It becomes possible to use RAM.

As described above, according to the present invention, all the memory used in the entire device is large-capacity dynamic RAM.
Since the circuit configuration is simple, the device can be configured at low cost. Also, even if dynamic RAM is used, the refresh time is absorbed as the time required for display, so
There is no decrease in CPU processing speed, leading to improved performance.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional character code display device configured using a CPU, Figure 2 is a diagram showing an example of the address assignment of the system shown in Figure 1, and Figure 3 is an example of a displayed image. 4 is a timing chart of various signals, FIG. 5 is a block diagram of a conventional character code display device capable of color display, FIG. 6 is a block diagram of an embodiment of the present invention, and FIG. , 8 is a diagram showing an example of address allocation of the system shown in FIG. 6. 1...Central processing circuit, 20...Timing control circuit, 71...Display timing generation circuit, 7
2...Address switching circuit, 73...For display
RAM, 77...RAM for color.

Claims (1)

[Claims] 1 Consists of at least two systems, each including a data memory requiring refresh;
A part of the data memory of the system serves as a first display memory for storing the first group of information to be displayed in color, and a part of the data memory of the second system stores the second group of information to be displayed in color. a memory circuit serving as a second display memory, a central processing circuit that exchanges information with the data memory of each system, a display timing generation circuit that generates an address signal for display, and a display timing generation circuit that generates an address signal for display. an address switching circuit that switches between an address signal output from the central processing circuit and an address signal output from the central processing circuit for information exchange, and supplies the first and second system data memories as a combined address signal; If the combined address signal is an address signal from the central processing circuit, one of the memory circuits of both systems is operated according to its contents, and the combined address signal is used for display. 1. A color display circuit comprising: a timing control circuit that generates a control signal that causes first and second systems of memory circuits to operate simultaneously when the signal is an address signal. 2. The color display circuit according to item 1, wherein the data memories of the first system and the second system have the same capacity. 3. The color display circuit according to item 1 or 2, wherein during a period when the data memories of the first system and the second system are selected, the data memories of the other systems are refreshed. 4. The address switching circuit is switched to the address signal side from the central processing circuit at least once within one character display period.
3. The color display circuit according to any one of items 3 to 3.