JPH0225187B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a character and graphic display device that is capable of scrolling the display contents when displaying the image of character and graphic information supplied from a digital computer or the like on the display device. In more detail,
The present invention relates to a character/figure display device that enables scrolling of displayed images in a partial area of a display memory. With the rapid development of LSI technology in recent years, the central processing circuit (hereinafter abbreviated as CPU) of computers
With the emergence of microcomputers that consist of a single LSI, conventional general-purpose digital IC systems are beginning to shift to CPU-centered systems. In addition to the CPU, such a system includes a playback-only memory circuit (hereinafter referred to as program ROM) that stores the CPU's processing procedures (programs).
The main components are a rewritable memory circuit (hereinafter referred to as data RAM) that temporarily stores data during CPU processing or serves as a program ROM, and an input/output circuit. FIG. 1 is a block diagram showing an example of an image display device using the above-mentioned microcomputer. In this figure, 1 is a CPU, 2 is a clock generation circuit that issues a clock signal for CPU 1, 3 is a data RAM, 4 is a program ROM, 7 is a character code display circuit that can display character code information, and 8 is a cathode ray tube. This is a typical display device. Also,
13 is a signal path for exchanging data between the CPU 1 and each circuit, that is, a data bus; 14 is a data bus;
A signal path through which the CPU 1 supplies address signals to each circuit, ie, an address bus, and 16 a clock signal path through which a clock signal generated from the clock generating circuit 2 is supplied. Character code display circuit 7
A display timing pulse generation circuit 71 that generates synchronization signals for television signals and display address signals, an address bus 14, and a display timing pulse signal path 15 from the display timing pulse generation circuit 71 are clocked from the clock generation circuit 2. An address switching circuit 72 that switches in response to a clock signal supplied via the signal path 16, a memory circuit (hereinafter referred to as display RAM) 73 that has a relative positional relationship with the display screen and stores character code information, and a memory circuit (hereinafter referred to as display RAM) 73 that stores character code information. A reproduction-only memory circuit (hereinafter referred to as character pattern generation ROM) 74 that stores the corresponding character code pattern in advance, and a parallel-serial conversion circuit 75 that converts parallel signals generated by the character pattern generation ROM 74 into serial signals. It consists of This character code display circuit 7 is CPU1
corresponds to the output circuit of Furthermore, in an actual character display device, input circuits such as a keyboard are generally connected via a data bus 13 and an address bus 14, but these are omitted as they are not relevant to the essence of the present invention. . FIG. 2 is a diagram showing an example of the address assignment of the system shown in FIG. FIG. 3 is a diagram illustrating timing relationships among signal paths; First, the circuit shown in Figure 1 plays an important role.
The operation of CPU1 will be explained. In FIG. 1, a CPU 1 is a central processing circuit of a so-called microcomputer. CPU 1 is usually capable of processing multiple bits at the same time, but for the sake of explanation here, it is assumed to be a CPU capable of 8-bit parallel processing.
It is assumed that the address bus 14 has 16 parallel lines output. In other words, CPU1 starts from address 0.
2 ¹⁶ - 1 = address 65535 (FFFF in hexadecimal)
Addresses are expressed in hexadecimal numbers below to simplify representation. ) address signals can be output. Moreover, the data bus 13 is eight parallel lines, and runs from the CPU 1 to each memory circuit (program ROM 4, data RAM 3, display RAM 7).
This is a signal path that sends parallel 8-bit signals to CPU 3) and vice versa. Generally, in a microcomputer system, a CPU 1 and each circuit are connected by the same address bus 14 and the same data bus 13, as shown in FIG. Therefore, in order to separate each circuit, different addresses are assigned to each circuit. FIG. 2 shows an example of this address assignment. In Figure 2, the program ROM
A total of 4096 addresses from (FOOO) ₁₆ to (FFFF) ₁₆ are allocated to data RAM 3, and a total of 4096 addresses from (OOOO) ₁₆ to (OFFF) ₁₆ are allocated to data RAM 3.
Address 4096 is allocated, and display RAM7
3 has the total from (8000) _16th to (87FF) _16th
Address 2048 has been assigned. Like regular electronic computers, microcomputers also store programs, so they
The ROM 4 stores processing procedures (programs) for operating the system shown in FIG. As shown in Figure 2, the program ROM 4 occupies 4096 addresses from (FOOO) ₁₆ to (FFFF) ₁₆ , and the stored contents are read out to the data bus 13 according to the address information on the address bus 14 of the CPU 1. It will be done. This memory content is taken in by the CPU 1, decoded as an instruction, and operates this system. That is, a program counter is normally provided inside the CPU 1, and the value indicated by this counter is the program ROM containing the instruction being executed.
Determine address number 4. Next, this address information is output to the address bus 14, and the data stored at that address in the program ROM 4 is transferred to the data bus 14.
After that, it is taken into the CPU. CPU1 decodes this data as an instruction and uses it for data RAM3 and display.
It operates the entire system by changing the memory contents of the RAM 73 and exchanging data with other input/output circuits. FIG. 4 shows the timing relationship among the clock signal, address signal, and data signal during operation. 4a shows the clock signal supplied to CPU 1 by signal path 16, FIG. 4b shows the address signal passing through signal path 14, and FIG. 4c shows the data signal passing through signal path 13. Since the address signal is output in one direction from CPU 1, the address is advanced within the T ₁ period with a certain time delay from the falling edge of the clock signal, but the data signal is a bidirectional signal, so it is output mainly during the T ₂ period. This operation prevents output signals from competing with each other on the data bus 13. The above is an explanation of the general operation of the CPU 1. Next, the character code display circuit 7 for displaying the character code information taken into the CPU 1 on the display device 8 will be explained. This circuit is a well-known circuit known as a cycle steal display system. The feature of this method is that CPU 1 uses display RAM 7
No special processing is required to access 3.
Moreover, character codes can be displayed stably. That is, as shown in FIG. 4, focusing on the fact that the data signal issued from the CPU 1 is sent and received only during the _T2 period of the clock signal, in the _T1 period,
CPU 1 display RAM 73 and address switching circuit 7
2, disconnect and display timing pulse generation circuit 7
In this method, a display address signal from 1 is supplied to a display RAM 73 via an address switching circuit 72, and character code information stored therein is read out. The state of the combined address signal supplied to the display RAM 73 at this time is shown in FIG. 4d. The read character code information is supplied to a character code pattern generation ROM 74 that stores character code patterns in advance, as in other display systems. Further, a display address signal from the display timing pulse generation circuit 71 is also simultaneously supplied to the character code pattern generation ROM 74, and character code pattern information is read out. The read character code pattern information is supplied to the parallel-to-serial conversion circuit 75,
The signal is converted into a signal that can be input to the display device 8 and output from the parallel-to-serial conversion circuit 75. FIG. 3 shows an example of an image displayed on the display device 8 in this way. The display device 8 displays 64 pieces of character code pattern information in the horizontal direction and 20 pieces in the vertical direction, for a total of 1280 pieces of character code pattern information. can. The character code pattern information displayed here is for display with a total of 1280 addresses from (8000) ₁₆ to (84FF) ₁₆ in Figure 2.
It is configured to have a one-to-one correspondence with the character code information stored in the display memory portion of the RAM 73.
In other words, if the locations 1 and 1 in Figure 3 correspond to address (8000) ₁₆ , then the locations 1 and 1 in Figure 3 correspond to address (8000) 16.
At position 1, the display timing pulse generation circuit 71 supplies a display address signal to the display RAM 73 so as to read address (8000) ₁₆ . The above is an overview of the character code display circuit. When using such a character code display circuit 7 to display the displayed character code pattern information in order from the bottom to the top, so-called scroll display, the CPU 1 displays the information a number of times equivalent to twice the number of characters to be raised. for
It had the problem of not being able to scroll quickly because it had to access 73 RAM. A display circuit that avoids such problems and enables high-speed scrolling will be described next. FIG. 5 is a block diagram showing a conventional example of an image display device capable of vertically scrolling display. In this conventional example, a data latch circuit 77 and a scroll counter circuit 76 are newly added, thereby converting the display address signal output from the display timing pulse generation circuit 71 into a scroll address signal. In FIG. 5, circuits that are the same as those in FIG. 1 are designated by the same reference numerals. Also, Figure 6 shows
An example of address setting during scroll display is shown to explain the operation of FIG. 5. Below, the general operation of FIG. 5 will be described. In FIG. 5, the addresses assigned to the display memory 73 exist between addresses (8000) ₁₆ and (87FF) ₁₆ when viewed from the CPU 1, but when viewed from the display timing pulse generation circuit 71, they are located at As shown in the figure, it is enough to distinguish 1280 addresses, so it is sufficient to generate at least 11 bits of address information. Therefore, below, address expressions when viewed from the CPU 1 are expressed in 4-digit hexadecimal numbers, and address expressions related to display, such as address information from the display timing pulse generation circuit 71 and setting data of the data latch circuit 77, are expressed in hexadecimal numbers. It shall be expressed in three digits. The data latch circuit 77 is set by the CPU 1 to the first address of the first row of the display screen. For example, as shown in FIG. 6, an address corresponding to the number of scroll lines is set, such as 0 in the initial state where no scrolling is performed, 64 when scrolling up by one line, and 128 when scrolling up by two lines. This set address is preset in the scroll counter circuit 76 before the screen is displayed, and thereafter, according to the display screen, the count of the scroll counter circuit 76 is incremented by one by a signal from the display timing pulse generation circuit 71. Increase by increments.
At the same time, the output signal of the scroll counter circuit 76 is supplied as a display address signal to the address switching circuit 72, and the character code information stored in the display RAM 73 is displayed in the same manner as in the case of FIG. In this case, the new line will be the bottom line, so it is shown in Figure 2 (8500) from address ₁₆ (87FF) ₁₆
Scroll to the address The contents of the RAM address will also be displayed on the screen. In addition, the scroll counter circuit 76 is configured to count up to address (7FF) ₁₆ (= address 211), and ignores the upper 5 bits of the displayed RAM address, and the next address after address (7FF) ₁₆ is address 0. It is configured so that Therefore, the displayed character code pattern information is from (8000) ₁₆ to (87FF) ₁₆ in Figure 2, of a total of 2048 addresses, from the address specified by the data latch circuit 77 to 1280 (horizontal 64, It is constructed in a relatively one-to-one relationship with character code information stored in 20) vertical columns. Furthermore, the data set in the data latch circuit 77 shifts by 64 characters each time one line is scrolled, so the configuration is such that the data cannot be returned to the initial state unless 32 lines are scrolled. With the conventional scroll display described above, it is possible to scroll the entire screen, but it is also possible to scroll only a portion of the display screen, such as scrolling only 15 lines from the top of the screen or 10 lines from the bottom of the screen. There is a drawback that it cannot be done. The purpose of the present invention is to eliminate the drawbacks of the above-mentioned prior art,
To provide a character/figure display device capable of arbitrarily setting the top address of a display screen and performing scrolling at high speed in a partial area of a display RAM. In order to achieve the above object, the present invention includes: memory means for storing character and graphic information; display means for displaying on a display screen a character and graphic pattern corresponding to the character and graphic information read from the memory means; a counting means that sequentially generates a count value that increases or decreases from a value and returns to the first value when it reaches a second value; a plurality of types of data corresponding to the first address on the display screen; A start data setting means 77 to be set; a determining means for determining a position where display addresses on the display screen are discontinuous; and data corresponding to a new start address of the position determined by the determining means is set. and a second start data setting means for calculating a read address of the memory means from the output of the counting means, the output of the start data setting means, and the output of the second start data setting means, and supplying the read address to the memory means. The apparatus comprises an address calculation means; and a control means 1 for controlling the start data setting means and the second start data setting means so that the read address outputted from the address calculation means becomes a partial area of the memory means. With the above configuration, the read address from the memory means can be configured in a loop in partial areas, so that no matter where the top address of the display screen is assigned, the memory can be read only by setting data to the data setting circuit. It becomes possible to scroll at high speed using the partial area of the means. Furthermore, the above object is characterized in that the determining means comprises a memory address determining means for determining the end address position of the partial area of the memory means, and a position determining means for determining the position of the display screen, and
A higher degree of freedom can be achieved by the second start data setting means having a data setting circuit for setting a plurality of data according to the outputs of the memory address determining means and the position determining means. That is, the start address of the display screen and the start address of the scroll area can be set independently. Furthermore, the read addresses assigned to the scrolling area can be configured in a loop, so that no matter where the top address of the display screen and the top address of the scrolling area are assigned, the data setting circuit can be accessed. Just by setting the data,
High-speed partial scrolling is possible in a partial area of the memory means. Hereinafter, the present invention will be explained in detail with reference to FIGS. 7 to 9. FIG. 7 is a block diagram showing an embodiment of the character/figure display device according to the present invention, and the same reference numerals are used for the same circuit parts as in FIGS. 1 and 5. In the figure, 78, 79, 7A, and 7B are data setting circuits, which use a data latch circuit so that they can be controlled by the CPU 1. Further, 7C and 7D are comparison circuits, and 7E, 7F, and 7G are addition circuits that add the output signals of the data setting circuits 77, 78, and 79 and the display address signal supplied from the display timing pulse generation circuit 71. . Furthermore, the eighth
9 and 9 are diagrams for explaining the operation of FIG. 7, respectively, and show examples of address setting during scroll display. Now, in FIG. 7, the data setting circuit 77,
78, 79, 7A, and 7B are structured so that arbitrary values can be set, like the data latch circuit 77 in FIG. Suppose a value like this is set. In this case, data setting circuits 78, 7B, comparison circuit 7D, and addition circuit 7
Since F is not particularly required, the data setting circuit 7
8 and 7B are set to 0 as an address setting value. The data setting circuit 77 also selects the first address of the display memory to be displayed on the screen.
9 is the difference between the address ²ⁿ and the final address of the display memory (300) ₁₆ addresses are set, and the data setting circuit 7A stores the (500) ₁₆ addresses next to the final address of the display memory, respectively. Set. Note that the data set in the data setting circuit 77 increases or decreases by a predetermined value in accordance with the scroll cycle. As in the case of Fig. 1, the signal is supplied from the display timing pulse generation circuit 71 from address (000) ₁₆ (4FF) ₁₆
The address display address signal is supplied to the adder circuit 7E, added to the address set in the data setting circuit 77, and output. Therefore, the adder circuit 7E
The output signal becomes a count value that increases sequentially from the address set in the data setting circuit 77. Further, this output signal is input to the adder circuit 7F, but since the address set in the data setting circuit 78, which is the other input, is 0, the output signal of the adder circuit 7F is the output signal of the adder circuit 7E. be equivalent to. Next, the output signal of the adder circuit 7F is supplied to the next adder circuit 7G and at the same time, it is also supplied to the comparator circuit 7C. The data setting circuit 7 is connected to the other input of the comparison circuit 7C.
Since address (500) ₁₆ , which is the setting value of A, is supplied, the address of the output signal of adder circuit 7F is (500) ₁₆
When the address exceeds the address, the output signal of the comparator circuit 7C is obtained. When this output signal is being supplied to the data setting circuit 79, the setting data of the data setting circuit 79 is supplied to the adder circuit 7G and added to the output signal of the adder circuit 7F. When the output signal of the comparison circuit 7C is not supplied to the data setting circuit 79,
The setting data of the data setting circuit 79 is the adding circuit 7G.
is not supplied. In other words, when the address of the output signal of the adder circuit 7F becomes address (500) ₁₆ or higher, the address (300) ₁₆ is added to the output signal of the adder circuit 7F,
(800) becomes address ₁₆ (100000000000), which equivalently becomes address 0. Therefore, in Fig. 6, the display screen displays numbers (500) ₁₆ and above as 0 as shown in Fig. 8.
It is possible to create a ring with the memory capacity of one screen and display it by shifting it, and even when scrolling, the memory capacity required for display is reduced to 3 64 in the example shown
×20=(500) It is only ₁₆ bytes, which is ₁₆ bytes less than the configuration shown in FIG. 5 by the capacity of the scroll memory (300). Furthermore, in this case, when scrolling 20 lines, the address relationship on the screen matches the initial state, so the data value set in the data setting circuit 77 can be simply set as the value of the number of lines to be scrolled, and the calculation of the data value is Almost unnecessary. This is because in the example of FIG. 7, the data setting circuit 77
The data values to be set are address 0, address N, address 2N, and address 3N, where N is the number of addresses displayed in one horizontal line.
This is the starting address of each line, so if each address is expressed in binary, the starting address of each line will be as follows.

[Table] Therefore, in this case, the lower 6 bits of the binary display are always 0, and the value set in the data setting circuit 77 can be a value corresponding to the upper 5 bits, and moreover, that value is the value of the number of scroll lines. The value will be exactly the same as the value, and there will be no need to calculate the setting data value. Furthermore, in the above example, the display RAM addresses (000) ₁₆ to (4FF) ₁₆ are displayed, but other addresses may be used to scroll the entire screen. For example, if we want to display memory addresses (300) ₁₆ to (7FF) ₁₆ , the result will be as follows. In the data setting circuit 77, addresses (000) ₁₆ to (4CO) ₁₆ corresponding to the display start address are set in accordance with the scroll amount, as in the case described above. Further, address (300) ₁₆ is set in the data setting circuit 78, and address (000) ₁₆ is set in the data setting circuit 7B.
At this time, the comparison circuit 7D compares the display address signal from address (000) ₁₆ to address (4FF) ₁₆ supplied from the display timing pulse generation circuit 71 with address (000) ₁₆ of the data setting circuit 7B. Therefore, the output signal of the comparator circuit 7D is always obtained. Therefore, the address (300) ₁₆ set in the data setting circuit 78 is always output to the addition circuit 7F. Since the output signal of the adder circuit 7E is supplied to the other input of the adder circuit 7F, as a result, the adder circuit 7
The output of F includes a display timing pulse generation circuit 7.
Address indicated by the display address signal from 1 and data setting circuit 78 (300) Address ₁₆ and data setting circuit 7
The resultant address is obtained by adding any one of the ₁₆ addresses (000) to ₁₆ (4CO) corresponding to the display start address of 7. The minimum value of this address is (300) ₁₆ , and the maximum value is (4FF) ₁₆ +
(300) ₁₆ + (4CO) ₁₆ becomes (CBF) _16th address. next,
Set address (800) ₁₆ in data setting circuit 7A,
Address (300) ₁₆ is set in the data setting circuit 79. When the output signal of the adder circuit 7F reaches address (800) ₁₆ or higher, the setting data of the data setting circuit 79 is changed to the adder circuit 7G by the comparison output from the comparator circuit 7C.
Considering only the lower 11 bits, the output of the adder circuit 7G is converted to an address of (300) ₁₆ or more. Therefore, the address obtained by adding the set value of the data setting circuit 77 and the set value of the data setting circuit 78 is outputted from the adder circuit 7G in response to the display address signal from the display timing pulse generating circuit 71. Ru. When the output of the adder circuit 7G reaches address (7FF) ₁₆ , the next address is outputted as address (300) ₁₆ . In this way, you can scroll from memory location (300) ₁₆ to (7FF) ₁₆ . In addition, in this case, when the output signal of the adder circuit 7F reaches address (800) ₁₆ or higher, the adder circuit 7F
The data setting circuit 79 can be directly controlled using the 12th bit output signal. At this time, data setting circuit 7
A and the comparator circuit 7C are not required, and the circuit can be simplified. Next, a case where scrolling is performed in a part of the screen as shown in FIG. 9 will be described. In this case, 0 is set in the data setting circuit 77, and the data set in the data setting circuit 78 by the CPU 1 controls scrolling. Further, address (380) ₁₆ is set in the data setting circuit 79, address (500) ₁₆ is set in the data setting circuit 7A, and address (080) corresponding to the third line in FIG. 9 is set in the data setting circuit 7B. Address ₁₆ is set. Similar to the example in FIG. 8, the display address signal is sent to the adder circuit 7.
E, and is added to the address set in the data setting circuit 77 and output. In this case, since the setting data of the data setting circuit 77 is set to 0, the adder circuit 7E outputs the address 16 from ( ₀₀₀ ) ₁₆ to (4FF) indicated by the display address signal supplied from the display timing pulse generation circuit 71 as is. be done. Further, the display address signal is simultaneously compared by the comparison circuit 7D with the first address (080) ₁₆ of the third row set in the data setting circuit 7B. Therefore, when the display address signal is at address (080) ₁₆ or higher, that is, from the third line onward on the display screen, the data setting circuit 78 is configured to output its output value according to the output signal of the comparator circuit 7D. controlled. Therefore, from the third line onward on the display screen, the setting data of the data setting circuit 78 is added to the output signal of the adding circuit 7E by the adding circuit 7F, and scrolling according to the setting value of the data setting circuit 78 is possible. becomes. Furthermore, since address (500) ₁₆ is set in data setting circuit 7A, comparison circuit 7C determines whether the output of adder circuit 7F is at address (500) ₁₆ or higher. When the output of the adder circuit 7F reaches address (500) ₁₆ or higher, the adder circuit 7G adds the address (380) ₁₆ set in the data setting circuit 79. As a result, an address of (880) ₁₆ or more is obtained as the addition output, and if only the lower 11 bits of the addition output are considered, it is converted to an address of (080) ₁₆ or more. Therefore, the output of the adder circuit 7G is (080) ₁₆ from the third line onwards on the display screen.
It is possible to configure a loop from address (4FF) to address ₁₆ . Furthermore, when address (080) ₁₆ is set in the data setting circuit 78, it will scroll up by two lines, and the third and subsequent lines will be scrolled one after another according to the set value, up to address (440) ₁₆ , i.e. , you can scroll 17 lines. If you scroll one more line after scrolling 17 lines, the address arrangement will be the same as the initial state, so next to address (440) ₁₆ , set 0 again to scroll 18 lines. Therefore, in this case, 1
The 2nd and 2nd lines are displayed in a fixed manner, and the 3rd to 20th lines are scrolled. In the case of FIG. 9, an example is shown in which the third and subsequent lines are scrolled, but of course it is also possible to set data such that the second and subsequent lines are scrolled and the third and subsequent lines are fixed. In that case, as an example,
An output signal with the polarity inverted from the comparison circuit 7D is supplied to the data setting circuit 78, and when the display address signal from the display timing pulse generation circuit 71 is smaller than the value from the data setting circuit 7B, the output signal from the comparison circuit 7D is supplied to the data setting circuit 78.
Further, the data setting circuit 77 is set to address (280) ₁₆ , and the data setting circuit 7B is set to address (080) ₁₆ , which corresponds to the third row. The data setting circuit 78 outputs only the first and second lines to the adding circuit _{7F according to the number of lines to be scrolled (500), and the data setting circuit 7A outputs (800) 16 to} the data setting circuit. circuit 7
For 9, set addresses (780) _{and 16} , respectively. Then, (000) ₁₆ of the display address signal from the display timing pulse generation circuit 71 is displayed on the first and second lines.
The starting address (780) 16, _which is the sum of the address, (280) ₁₆ of the data setting circuit 77, and (500) ₁₆ of the data setting circuit 78, is assigned to (7FF) ₁₆ . Further, from the third line onward, address (500) ₁₆ of the data setting circuit 78 is not output, and address (080) ₁₆ , which is the address of the third line of the display address signal from the display timing pulse generation circuit 71, and data setting. From the starting address (300) ₁₆ , which is the sum of (280) and ₁₆ of circuit 77, to (77F) ₁₆ will be allocated. In this case, the data setting circuit 78
The data set in determines the number of scroll lines for the first and second lines. In addition, the data setting circuits 77, 78,
This can be realized by changing the setting values of 9, 7A, and 7B. In addition, the data setting circuits 79, 7A, 7 in FIG.
It is clear from the examples shown in FIGS. 8 and 9 that it is not necessary to allow all values of B to be set from the CPU 1. Therefore, except for the data setting circuit that controls scrolling, a data setting circuit that sets fixed numerical values will suffice for the purpose. The above-mentioned examples have been explained for all character display devices, but the present invention can also be applied to pattern display devices in which the character pattern generation ROM 74 is not provided and the display RAM 73 and the parallel-to-serial conversion circuit are directly connected. can be applied. In this manner, in the above embodiment, scrolling display can be performed only in a portion of the display screen. Also, for displaying 2 ⁿ addresses, which was previously required.
The RAM capacity can be set equal to the number of character code patterns to be displayed, for example 64 x 20
Previously, a pattern required 2048 bytes.
The RAM capacity is 1280 bytes, and the display circuit can be constructed at low cost. Furthermore, since the number of lines to be scrolled matches the number of lines that can be displayed on the screen, the capacity of the program to process scrolling is reduced, which also makes it cheaper. Furthermore, since the program capacity is reduced, the processing time required for the program can be shortened, and there is an advantage that high-speed scrolling operation is also possible. As described above, according to the present invention, there is provided a character/figure display device which has a new function of arbitrarily setting the top address of the display screen and performing scrolling at high speed using a partial area of the display RAM. Available.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional character code display device, Fig. 2 is an address allocation diagram showing an example of the address allocation of the character code display device shown in Fig. 1, and Fig. 3 is a diagram showing a display image. Fig. 4 is a timing chart showing the timing relationship of the main signals of the character code display device shown in Fig. 1, Fig. 5 is a block diagram showing a conventional character code display device capable of scrolling display, and Fig. 6 is a scroll diagram showing the timing relationship of the main signals of the character code display device shown in Fig. 1. An address state diagram showing the correspondence between display image positions and memory addresses during display, FIG. 7 is a block diagram showing an embodiment of the character/figure display device according to the present invention, and FIG. 8 is a display during full screen scroll display. FIG. 9 is an address status diagram showing the correspondence between image positions and memory addresses. FIG. 9 is an address status diagram showing the correspondence between display image positions and memory addresses during partial scroll display. DESCRIPTION OF SYMBOLS 1...Central processing circuit, 7...Character code display circuit, 71...Display timing pulse generation circuit, 73
...Display RAM, 77, 78, 79, 7A, 7B
...Data setting circuit, 7C, 7D...Comparison circuit, 7
F, 7G...addition circuit.

Claims (1)

[Scope of Claims] 1. Memory means for storing character and graphic information; display means for displaying on a display screen a character and graphic pattern corresponding to the character and graphic information read from the memory means; increasing from a first value; or a counting means that sequentially generates a count value that changes in one direction of decrease and returns to the first value when it reaches a second value; corresponds to the first address of the character/figure pattern displayed on the display screen; a first start data setting means 77 that can set a plurality of types of data; and a determining means 7 that determines the position where the display address of the character/figure pattern displayed on the display screen is discontinuous.
B, 7D, 7A, 7C; second start data setting means 78, 79 in which data corresponding to the new start address of the position determined by the determination means is set; output signals of the counting means; address calculation means 7 which calculates a read address of the memory means from the output data of the first start data setting means and the output data of the second start data setting means and supplies it to the memory means;
E, 7F, 7G; control means for controlling the first start data setting means and the second start data setting means so that the read address output from the address calculation means corresponds to a partial area of the memory means; 1. A character and graphic display device comprising: 1. 2. The address calculation means includes a first address calculation means 7E that generates a first read address from the count value of the counting means and the output data of the first start data setting means 77, and It is composed of a calculation means and a second address calculation means 7G that generates a read address of the memory means from the output data of the second start data setting means 79, and the determination means is configured to perform the first address calculation. Address determination means 7 for determining the first read address output from the means
A character/graphic display device according to claim 1, wherein the display device is A, 7C. 3. The determining means is a position determining means composed of a position setting means 7B for setting an arbitrary position on the display screen; and a comparison means 7D for comparing the output of the position setting means and the output of the counting means. A character and graphic display device according to claim 1, characterized in that: 4. The determining means comprises address determining means 7A, 7C for determining the end address position of the partial area of the memory means, and position determining means 7B, 7D for determining the position of the display screen, and The start data setting means 2 is a data setting circuit 79, 7 for setting data according to the output data of the address determining means and the position determining means.
Claim 1 characterized in that it consists of 8
The character/graphic display device described in Section 1.