JPS6132445A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6132445A
JPS6132445A JP15460284A JP15460284A JPS6132445A JP S6132445 A JPS6132445 A JP S6132445A JP 15460284 A JP15460284 A JP 15460284A JP 15460284 A JP15460284 A JP 15460284A JP S6132445 A JPS6132445 A JP S6132445A
Authority
JP
Japan
Prior art keywords
chip
low melting
melting point
semiconductor
resistant resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15460284A
Other languages
Japanese (ja)
Inventor
Satoshi Kikuchi
智 菊地
Kenichi Yazaki
健一 矢崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15460284A priority Critical patent/JPS6132445A/en
Publication of JPS6132445A publication Critical patent/JPS6132445A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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    • H01L2224/29001—Core members of the layer connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8389—Bonding techniques using an inorganic non metallic glass type adhesive, e.g. solder glass
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L2924/078—Adhesive characteristics other than chemical
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    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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    • H01L2924/19043—Component type being a resistor

Abstract

PURPOSE:To enhance the reliability by removing the adverse effect of cracks in the back of a semiconductor chip on the characteristics by a method wherein a semiconductor chip is adhered via heat-resistant resin to a low melting point glass provided on the cavity of a semiconductor package. CONSTITUTION:The semiconductor chip 1 is adhered via heat-resistant resin 10 to the low melting point glass 2 provided on the cavity of the semiconductor package. For example, using polyimide as the heat-resistant resin 10, a polyimide tape is previously thermally press-bonded to the back of the chip 1, and such a chip 1 is adhered to the low melting glass 2 melted by heating to 450- 500 deg.C. This manner lessens the stress applied on the chip back with an elastic resin and then eliminates the cracks.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は半導体装置に係り、特にガラスキャビティ型パ
ッケージを用いた半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device using a glass cavity type package.

半導体集積回路（ＩＣ）を収納する容器（パッケージ）
は、大別してセラミックパッケージとモールド型パッケ
ージ（プラスチックパッケージ）の２種却がある。前者
は高価な反面、信頼性が高い利点があり、後者は安価に
作成できるが、気密性が十分てない欠点がある。A container (package) that stores a semiconductor integrated circuit (IC)
There are two types of packages: ceramic packages and molded packages (plastic packages). Although the former is expensive, it has the advantage of being highly reliable, while the latter can be produced at low cost, but has the disadvantage of not being sufficiently airtight.

また、セラミックパッケージは種々の型に分類されてお
り、最も安価に製造できるものとして、サーディツプ型
がある。これは低融点ガラスを用いてリード線をセラミ
ック製ベースとセラミック製キャンプとで挟む構成のパ
ッケージである。Furthermore, ceramic packages are classified into various types, and the cerdip type is the one that can be manufactured at the lowest cost. This is a package in which a lead wire is sandwiched between a ceramic base and a ceramic camp using low melting point glass.

このようなセラミックパッケージにおいては、一般にセ
ラミック製ベースのキャビティに金集付けをし、その上
に半導体チップを接着するが、更に安価とするために、
金集付けの代わりに低融点ガラスを用いて接着する場合
もある。このような低融点ガラスを用いて、半導体チッ
プをキャビティ上に接着するパンケージをガラスキャビ
ティ型と云う。In such ceramic packages, gold is generally attached to the cavity of the ceramic base, and the semiconductor chip is bonded on top of it, but in order to make it even cheaper,
In some cases, low melting point glass is used instead of gold bonding. A pancage in which a semiconductor chip is bonded onto a cavity using such low melting point glass is called a glass cavity type.

［従来の技術］ 第２図は半導体チップを低融点ガラスを用いて接着する
サーディツプ型パッケージ形状の半導体装置の断面構造
図を示しており、１は半導体チップ（以下、チップと呼
ぶ）、２ば低融点ガラス。[Prior Art] Fig. 2 shows a cross-sectional structural diagram of a semiconductor device in the form of a cerdip package in which semiconductor chips are bonded using low-melting glass. Low melting point glass.

３はセラミック製ベース、４はセラミック製キャップ、
５はリード線、６はボンディングワイヤーである。3 is a ceramic base, 4 is a ceramic cap,
5 is a lead wire, and 6 is a bonding wire.

図のように、サーディツプ型の半導体装置は、リード線
５がセラミックベース３上の低融点ガラス２′に融着さ
れており（これを総称してリードヘースと云う）、且つ
セラミック製ベース３とセラミック製キャップ４とが低
融点ガラス２１で融着され、十分に気密封止されている
。また、半導体装ツブ１も低融点ガラス２によりセラミ
ック製ベース３のキャビティ上に融着された構造となっ
ている。As shown in the figure, in a cerdip type semiconductor device, a lead wire 5 is fused to a low melting point glass 2' on a ceramic base 3 (this is collectively referred to as a lead heath), and a ceramic base 3 and a ceramic base 3 are bonded to each other. The cap 4 is fused with a low melting point glass 21 and is sufficiently hermetically sealed. The semiconductor chip 1 also has a structure in which a low melting point glass 2 is fused onto a cavity of a ceramic base 3.

［発明が解決しようとする問題点］ 第３図は第２図のうち、チップ１を低融点ガラス２で融
着したベース部分の図である。このようにチップ１を直
接低融点ガラス２に融着するチップボンディング（チッ
プ付け）工程は、ベース３を４５０〜５００℃に加熱し
て低融点ガラス２を溶かし、チップ１を接着している。[Problems to be Solved by the Invention] FIG. 3 is a diagram of a base portion of FIG. 2 in which the chip 1 is fused with a low-melting glass 2. In the chip bonding (chip attaching) step in which the chip 1 is directly fused to the low melting point glass 2 as described above, the base 3 is heated to 450 to 500° C. to melt the low melting point glass 2 and the chip 1 is bonded.

、 しかし、チップボンディング後、常温に戻して固化させ
ると、ガラスと融着したチップ１との熱収縮率の違いか
ら応力が生じ、チップの背面ＩＲに、小さなりランクが
発生する。However, after chip bonding, when the temperature is returned to room temperature and solidified, stress is generated due to the difference in thermal contraction rate between the glass and the fused chip 1, and a small rank is generated on the back surface IR of the chip.

このクラック　（割れ）は、動作中の熱放散が悪くなる
等の問題を起こし、特性上に微妙な悪影響を与える。従
って、信頼性上法して好ましいものではない。These cracks cause problems such as poor heat dissipation during operation, and have a subtle negative effect on characteristics. Therefore, it is not desirable in terms of reliability.

本発明は、このチップ背面のクラックを解消させる構造
の半導体装置を提案するものである。The present invention proposes a semiconductor device having a structure that eliminates cracks on the back surface of the chip.

［問題点を解決するための手段］ その目的は、半導体パッケージのキャビティ上に設げら
れた低融点ガラスに、耐熱性樹脂を介して半導体チップ
が接着されている半導体装置によって達成される。[Means for Solving the Problems] The object is achieved by a semiconductor device in which a semiconductor chip is bonded to a low-melting glass provided on a cavity of a semiconductor package via a heat-resistant resin.

尚、上記低融点ガラスとは、４００〜５００℃程度の比
較的低い温度で熔融するガラスのことである。Note that the above-mentioned low melting point glass refers to glass that melts at a relatively low temperature of about 400 to 500°C.

［作用コ 即ち、半導体チップと低融点ガラスの間に、耐熱性樹脂
を介在させて、チップ背面のクランクを防止した構造の
半導体装置とするものである。[In other words, the semiconductor device has a structure in which a heat-resistant resin is interposed between the semiconductor chip and the low-melting glass to prevent cranking of the back surface of the chip.

［実施例コ 以下１図面を参照して実施例によって詳細に説明する。[Example code] An embodiment will be described in detail below with reference to one drawing.

第１図は本発明にかかる半導体装置のベース部分の断面
構造を示しており、第３図の従来構造に対応した部分拡
大図で、１０が耐熱性樹脂を示している。耐熱性樹脂１
０としては、例えばポリイミドを使用する。他の記号は
、第２図および第３図と同様である。FIG. 1 shows a cross-sectional structure of a base portion of a semiconductor device according to the present invention, and is a partially enlarged view corresponding to the conventional structure of FIG. 3, in which numeral 10 indicates a heat-resistant resin. Heat resistant resin 1
For example, polyimide is used as the material. Other symbols are the same as in FIGS. 2 and 3.

ボンディング方法は、チップ１の背面にポリイミドテー
プを予め熱圧着しておき、そのようなチップ１を４５０
〜５００℃に加熱し溶融した低融点ガラス２に接着する
。ポリイミドテープは厚み１ｍ程度のものを用いるが、
ポリイミドは約５００℃の高温に耐える耐熱性樹脂とし
て知られており、融点４００〜４５０℃のガラス２に埋
めても問題はない。The bonding method is to heat and press a polyimide tape onto the back of the chip 1 in advance, and then attach the chip 1 to a 450mm
It is adhered to the low melting point glass 2 which has been heated to ~500°C and melted. Polyimide tape with a thickness of about 1 m is used,
Polyimide is known as a heat-resistant resin that can withstand high temperatures of about 500°C, and there is no problem even if it is buried in glass 2 having a melting point of 400 to 450°C.

かくすれば、チップ背面に加わる応力が弾性のある樹脂
で緩和され、クランクが解消する。In this way, the stress applied to the back of the chip is alleviated by the elastic resin, and the crank is eliminated.

［発明の効果］ 従って、本発明によれば半導体チップ背面のクランクに
よる特性への悪影響が除去され、半導体装置の信頼性を
高めることができる。[Effects of the Invention] Therefore, according to the present invention, the adverse influence on the characteristics due to the crank on the back surface of the semiconductor chip can be eliminated, and the reliability of the semiconductor device can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明にかかる半導体装置のベース部分の断面
構造を示す図、 第２図は従来の半導体装置の全断面構造を示す図、第３
図は従来の半導体装置のベース部分の断面構造を示す図
である。 図において、 ■は半導体チップ（チップ）、ＩＲはチップ背面、２は
低融点ガラス、 ３はセラミック製ベース、 ４はセラミック製キャップ、 ５はリード線、　　　　１０は耐熱性樹脂を示している
。FIG. 1 is a diagram showing the cross-sectional structure of the base portion of the semiconductor device according to the present invention, FIG. 2 is a diagram showing the entire cross-sectional structure of the conventional semiconductor device, and FIG.
The figure is a diagram showing a cross-sectional structure of a base portion of a conventional semiconductor device. In the figure, (2) indicates a semiconductor chip (chip), IR indicates the back surface of the chip, 2 indicates low melting point glass, 3 indicates a ceramic base, 4 indicates a ceramic cap, 5 indicates a lead wire, and 10 indicates a heat-resistant resin.

Claims (1)

【特許請求の範囲】[Claims] 　半導体パッケージのキャビティ上に設けられた低融点
ガラスに、耐熱性樹脂を介して半導体チップが接着され
てなることを特徴とする半導体装置。A semiconductor device characterized in that a semiconductor chip is bonded to a low melting point glass provided on a cavity of a semiconductor package via a heat resistant resin.
JP15460284A 1984-07-24 1984-07-24 Semiconductor device Pending JPS6132445A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15460284A JPS6132445A (en) 1984-07-24 1984-07-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15460284A JPS6132445A (en) 1984-07-24 1984-07-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6132445A true JPS6132445A (en) 1986-02-15

Family

ID=15587767

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15460284A Pending JPS6132445A (en) 1984-07-24 1984-07-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6132445A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0433695A2 (en) * 1989-12-22 1991-06-26 Texas Instruments Incorporated Integrated circuit device and method to prevent cracking during surface mount

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0433695A2 (en) * 1989-12-22 1991-06-26 Texas Instruments Incorporated Integrated circuit device and method to prevent cracking during surface mount
EP0433695A3 (en) * 1989-12-22 1991-10-02 Texas Instruments Incorporated Integrated circuit device and method to prevent cracking during surface mount

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