JPS6132158A - Address setting circuit of common bus - Google Patents

Abstract

PURPOSE:To change easily a logical address without any setting error by setting a logical access sequence flag and setting a logical address to an input/output controller selected by a physical address. CONSTITUTION:When a processor accesses an input/output controller 4 via a common bus 6, a flag ADSEQ of an address setting sequence is set. When the flag ADSEQ is set, a comparator circuit 44 of an input/output controller 4 is activated. A low-order 4 bits of address buses AB00-15 and physical addresses PADR0-3 of the input/output controller 4 are collated and compared and when they are coincident, a coincident output is transmitted to an AND circuit 46. When AND is taken by a rising differentiation pulse of a write control signal WSRVI, a NAND circuit 47 is controlled, a clock CLK is fed to a logical address register 41 to set values of data buses DB00-15.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a system in which basic circuits such as a processor and memory, and a plurality of input/output control devices (IOC) groups that control various devices or interface circuits 9, etc. The present invention relates to a data processing system connected via a common bus, and particularly to a logical address setting method for a group of input/output control devices F (IOC) connected to the common bus.

Generally, a data processing system includes a service processor (hereinafter referred to as a service processor) that controls the operation and maintenance of the entire system.
svp), but since it is not directly related to the data processing operation of the main unit, it has the characteristic that high-speed processing is not required.

Therefore, for the purpose of making SvP more economical, minicomputers and the like are often used.

Such mini-computers have a so-called bus configuration, in which basic circuits such as a processor and memory, and a plurality of input/output control units (IOCs) that control various devices or ink face circuits are connected to the common bus. connected via.

FIG. 4 shows an example of the configuration of a common bus type data processing system used for the above-mentioned svp.

Here, 1 is the processor (CPU), 2 is the memory (M
tiM), 3 is a common circuit such as a timer, 4 is an input/output control device (IOC1-n), and 5 is various devices [for example, a printer (PRT), a display device (CRT), a file device (MDD), etc.].

and 6 is a common bus.

In this common bus type data processing system, each device connected to the common bus 6 [however, memory (M
(including EM)] 2 to 4, and each device can be accessed from the processor (CPU) 1 by the address assigned to each device.

In this case, the common bus 6 is composed of an address bus, a data bus, and various control buses, and the processor (CPU)
1 sends the address set in the device to the address bus and sends data to the data bus, or writes data to the device by reading data sent from the device to the data bus, Data can be read from the device.

Focusing on the data writing function of the common bus 6, a system has been awaited in which a logical address is set in a unique manner for each device connected to the common bus 6.

[Conventional technology]

FIG. 5 schematically shows a method of setting the logical address of a device according to the prior art. A portion for setting an address is shown, 41 is a logical address register (REG), and 42 is a short circuit (SC).

In this method, for example, a short circuit (SC) 42
Depending on whether or not to short-circuit terminals a and b with a shorting fitting,
Logic "0" and "1" can be set for each bit of the logical address register (REG) 41.

[Problem that the invention seeks to solve]

In the above conventional method, the short circuit (SC) 42
Since the short circuit (SC) 42, which requires a large mounting space, has to be mounted on the board on which the short circuit is mounted, it has become a factor that hinders the high-density mounting that is a recent trend in data processing systems.

Furthermore, when using the short circuit (SC) 42, the setting must be done manually, so there are problems in that setting errors cannot be avoided, the troublesomeness of the manual setting, and the need to change the logical address while the power is turned on. There was a problem of lack of flexibility, such as the inability to

In view of the above-mentioned conventional drawbacks, the present invention focuses on the fact that the common bus interface function has a data setting function in a common bus type data processing system. The purpose of this invention is to provide a method for setting a logical address in the logical address register (REG) 41 of a device (IOC 4) connected to the common bus 6.

・ [Means for solving the problem] And this purpose is to
A physical address is assigned to each 0C4, and a logical address setting sequence flag is provided in a part of the basic circuits such as the processor and memory, and the processor (CPU) 1 accesses the IOC group 4 via the common bus 6. When doing so, by turning on the logical address setting sequence flag, the Ioc selected by the physical address
This is achieved by the common bus address setting method of the present invention, which has the function of setting a logical address in the common bus 6 in the common bus 6.

[Operation] That is, according to the present invention, each IO connected to the common bus 6
In order to set the logical address to C group 4, each IOC4
A physical address is assigned to the mounting position of the board (printed board) constituting the board, and a common part (for example, common circuit 3 in FIG. A flag indicating the
When the flag is on, each IOC 4 stops normal address comparison, refers to a predetermined address pinpoint currently on the common bus 4, and writes data only when the predetermined address bits and the physical address bits match. Cycle glue line (
Since the old control vA) is captured and the address information on the data bus is set in the logical address register (12EG) 41 of the own l0C4, the Since the logical address can be arbitrarily set according to instructions from the processor (CPU), there is no troublesome manual setting and no setting errors, and the logical address can be easily changed.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and 4 and 6 are the same as those explained in FIG.
1 is the logical address register (RIl,
G).

FIG. 2 shows an example in which physical addresses (PADRO to 3) are assigned to the mounting positions of each 10C4 board.

As is clear from this figure, the physical address allocation described above can be realized by, for example, wiring the physical addresses assigned to each board in advance to the back panel on which each 10C'4 board is mounted.

Figure 3 is a memory map showing an example of address allocation used on the common bus 6 of this SvP.
From address ``H'' to address ``07EF'H'' indicates the system area, from address ``07FO'' H to address 07FF'H'' indicates the IOC address setting area necessary to implement the present invention, and address ``0800''H The area from '08FF' to the address is the input/output adapter area, which stores commands, transfer addresses, status, etc. for the IOC4, and the area from '0900'H address to °FFFF' is the memory (1'1EM). The main memory t for 2 is LM.

Hereinafter, the present invention will be explained in detail with reference to FIG. 1 while referring to FIGS. 2, 3, and 4.

First, when the power is turned on or the console is reset, initial program loading (hereinafter referred to as IPL) is started.

When the IPL is started, the processor (CPU) 1 uses the IPL program (including firmware) to set the address setting sequence flag (ADSEQ) built in the processor (CPU) 1 or the common circuit 3.
is turned on, and the lower 4 of the address bus (ABOO~15)
The virtual address is set to a predetermined address in the IOC address setting area that matches the physical address of the IOC4 (for example, '07FO's to '07FF' H address), and the logical address of the relevant IOC4 is transferred to the data bus (DBO).
O to 15), and operates to turn on the write control signal (WSRm) in order to perform a write operation of the logical address.

The common circuit 3 is accessed and the flag (ΔDSEQ
) can be realized by using a fixed address fixedly given to the common circuit 3.

When the flag CADSEQ) turns on, the corresponding ADSEQ line of the common bus 6 is activated, so in each 10C4, the comparison circuit ((:OMP) 44 is activated and the address bus (ABOO) of the common bus 6 is activated. The lower four bits (AB12 to AB15) of 15) and the physical address PADRO to 3 of the 10C4 are compared, and if they match, the -dispersed output is sent to the AND circuit (A) 46.

In each IOC 4, when the flag (ADSEQ) is turned on and a match output is obtained in the comparator circuit (GOMP) 44, the rise differentiation of the write control signal (WSRVI) obtained by the rise differentiation circuit 45 is performed. By the pulse, the above AND circuit (A) 46
The output signal controls the NAND circuit (N) 47, the clock (CLK) is supplied to the logical address register (REG) 41, and the value on the data bus (DBOO~15) is The logical address register (REG) 41 can be accessed.

In this case, the lower 4 pins (AB1
The values of 2 to 15) start from address ``0000'' and are incremented by 1 each time a logical address is set to one IOC4.
It operates to set logical addresses in all IOC4.

The IPL program turns off the address setting sequence flag (ADSEQ) immediately after the series of address setting sequences ends.

Also, during the address setting sequence operation, it operates so as not to run programs other than address setting, but if it becomes necessary to run a program other than address setting due to an interrupt etc., the above flag ( ADSEQ) must be controlled on/off.

When each IOC group 4 turns off the flag (ADSEQ), the contents set in the logical address register (REG) 4H become its own address, and the contents of the address bus (ABOO to 15) on the common bus 6 become the same. , and its own address are compared in a comparison circuit (GOMP) 43, and when a matching output is obtained, it is recognized that the own IOC 4 has been accessed, and a series of input/output operations are executed in the control circuit 49.

In this embodiment, as a means of allocating a physical address to each IOC4, a method of allocating the physical address to the position where the board of the IOC4 is mounted by wiring on the back panel was shown. It goes without saying that the present invention is not limited to this, and for example, a unique physical address may be set for each IOC4 within each 10C4 board.

〔Effect of the invention〕

As described above in detail, the common bus address setting method of the present invention is applicable to each IOC group 4 connected to the common bus 6.
In order to set a logical address to a common part [for example, the third Common circuit 3 in the figure]
A flag (ADSEQ) indicating that the processor (CPU) 1 is currently executing an address setting sequence is provided in the 10C4, and when this flag is on, each l0C4 stops normal address comparison and compares the addresses currently on the common bus 4. Only when the predetermined address bit and the physical address bit match, the write cycle tag line [write control line (WSRVI)] is captured and the logical address register of the own 10C4 is read. Since the address information on the data bus is set in the common bus 6, the logical address for the IOC group 4 connected to the common bus 6 can be set arbitrarily according to instructions from the processor (CPU), which eliminates the need for manual intervention. This has the advantage that the logical address can be easily changed without any trouble or setting errors.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing an example of assigning physical addresses to mounting positions on a board (printed board). FIG. 3 is a diagram illustrating a memory map of addresses used in this data processing system. FIG. 4 is a diagram showing the configuration of a common bus type data processing system. FIG. 5 is a diagram schematically showing a conventional logical address setting method. In the drawings, 1 is a processor (CPU), 2 is a memory (MEM), and 2 is a memory (MEM).
). 3 is a common circuit. 4 is an input/output control device (IOC1 to IOCnL5 are various devices, 6 is a common bus. 41 is a logical address register (REG). 42 is a short circuit (SC). 43.44 is a comparison circuit (GOMP). 45 is a rising differential Circuit. 49 is a control circuit. It shows respectively.

Claims (1)

[Claims] At least basic circuits such as processor and memory,
In a data processing system in which multiple input/output control unit (IOC) groups that control various devices, interface circuits, and other circuits are connected via a common bus, each input/output control unit (IOC) has a physical In addition to providing an address, a logical address setting sequence flag is provided in a part of the basic circuit, and when the processor accesses the input/output control device (IOC) group via the common bus, the logical access setting sequence flag is set in a part of the basic circuit. 1. A common bus address setting circuit comprising a function of setting a logical address to an input/output control device (IOC) group selected by the physical address through the common bus by turning on a flag.