JPS63116259A - Controlling method for system constitution - Google Patents

Abstract

PURPOSE:To dynamically reset a logical address from a master device at the time of replacing a functional allotment by setting up logical addresses of respective devices from the master device in a device and after the time point, accessing respective devices mutually in accordance with the logical addresses. CONSTITUTION:In case of transferring data from a certain device to a device 21, a sent address is latched by an address latching register 211 in each device. The sent transfer data are simultaneously latched by a data latch register 212 in each device. When an address format identification bit means a logical address, a logical address register 213 is selected and the logical address is sent to a comparator 216. An address part in the register 211 is also sent to the comparator 216, both the addresses are compared, and at the time of coincidence, a decoding circuit 217 in the device 21 decodes an instruction code part of the register 211. The decoded result is transmitted to a control part 218, the data latch 212 is controlled and the transferred data are outputted and processed by a processing circuit in the device.

Description

[Detailed Description of the Invention] [Industrial Applications] The present invention relates to a system configuration control method, and in particular, in a system consisting of a plurality of devices connected by a bus, it is possible to dynamically change the functional assignment of each device. Concerning possible dynamic system reconfiguration control methods.

[Conventional technology]

Conventionally, in a system consisting of a plurality of devices coupled to a common bus, when switching an operating device to another device on standby, the two devices were usually switched using a switching signal or the like using hardware. Further, as a software-based switching method, there is a method of referring to a table in memory, but all of these methods involve a master-slave relationship, for example, a relationship between a CPU and a terminal. In other words, the device number of the device in operation and the device number of the device on standby are registered in the table, and when switching from the device in operation to the device on standby, the device number 9 registered on the table is registered. By replacing the equipment, the equipment is transferred from the standby equipment to the equipment in operation.

Conventionally, such system reconfiguration methods include, for example, Japanese Unexamined Patent Application Publication No. 59-14066 ``Switching Control Device for Computer Organization'', Japanese Unexamined Patent Publication No. 58-176760 ``Terminal Connection Control System,'' or Kaisho 57-1.1317
There are publications such as No. 1 "System configuration control method".

[Problem that the invention seeks to solve]

In conventional systems, due to hardware switching, the number of devices in operation that could be replaced by a standby device was fixed and only in one or similar limited cases. . For example, for devices A, B, and C that are in operation, A, B, and C can be used as backup equipment.
It is necessary to put the devices of type B and C on standby.

Therefore, although the probability that multiple devices in operation at the same time will cause a failure is low, as the number of devices connected to a common bus increases, the problem arises that a corresponding number of spare devices must be provided. there were.

The purpose of the present invention is to solve these conventional problems, to enable switching to any device as long as it is functionally equivalent, and to minimize the number of spare devices connected to a common bus. The objective is to provide a system configuration control method that can limit the

[Means for solving problems]

In order to achieve the above object, the system configuration control method of the present invention provides a system configuration control method for each device from a master device among the devices.
By setting a logical address, from that point on, each of the above devices accesses each other according to the set logical address, and when changing the functional assignment of each device, the logical address can be dynamically reset from the above master device. There is a characteristic in doing.

[For production]

In the present invention, in addition to the conventional physical address given to devices connected to a common bus, by setting a logical address from the master device, each device thereafter uses this logical address. When the operating device and the standby backup device are functionally equivalent, the functions within the system can be replaced as is by exchanging the logical addresses between the two devices. . For example, if any device in operation becomes a failure, the master device will switch the logical addresses of the device in operation and the standby device. 9, the equipment that was previously in operation is removed from the system.

〔Example〕

Hereinafter, two embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a configuration diagram of a system showing an embodiment of the present invention. In Figure 1, 11, 21, 31° 41 are devices connected to the common bus 1, 12° 22, 32, 42
are physically rare subprograms that directly control each of the above-mentioned devices, and these are stored in a control unit in each device, that is, a ROM, etc., and executed by a microprocessor or the like.

13,23゜33.43 are each ablication simulation program located above the physical rare subprogram, and these are also stored in the control unit in each device, that is, ROM, etc., and executed by a microprocessor, etc. .

14 is a physical configuration management subprogram that is aware of the physical system configuration, and is stored in the main memory of the master device. The master devices are devices 11 and 2.
1, 31, and 41 is selected and designated, or a higher-level device (not shown) is designated as this.

Initially, under the control of physical rare subprograms 12, 22, 32.42 that directly control each device 11.21, 31.41, each device 11-41 follows a pre-given physical address. Perform mutual access.

In FIG. 1, the physical system configuration is shown as t! Since the physical configuration management subprogram 14 is located above the physical rare subprogram 12, the device 11 is the master device. However, other devices 21, 31.4
Of course, it is also possible to use No. 1 as the master device.

FIG. 2 is a block diagram of a self-address recognition circuit within the device in FIG. 1. In Figure 2, 1 is a common bus, 2
3 is also a data bus, 211 is an address latch register for latching the address (including instruction code) sent via address bus 2, and 212 is an address bus that constitutes common bus 1. 213 is a data latch register for latching data sent through the device; 213 is a logical address register for storing a logical address set from the master device; 214;
215 is a physical address register for storing a physical address given to this device in advance; 215 is a selector for selecting either a logical address or a physical address; 216 is a selector for selecting either a logical address or a physical address;
217 is an address conveyor circuit for comparing physical or logical addresses to determine whether the instruction is addressed to this device; 217 is for decoding or encoding the instruction code latched in the address latch register 211; instruction code decoding circuit 218 is the device 21
This is a control unit for controlling the ROM, RA
M, and a microprocessor.

FIG. 3 is a configuration diagram of an instruction format on the address bus of FIG. 2.

The instruction format consists of a physical/logical address identification bit 51, an address section 52, and an instruction code section 53, as shown in FIG.

The operation of this embodiment will be explained. In Figure 1, 11
．． 21.31 is in operation, and the device 41 is on standby.

The physical configuration management program 14 is stored in a control unit of any one of the devices 1i11 to 41, or in a control unit in a higher-level device other than these devices. In Figure 1, the physical rare subprogram 1
Although only subprograms 22, 32, and 42 of other devices can be controlled, the control is not limited to this.

First, at the time of system initialization, the physical configuration management program 14 assigns logical addresses "1" and "2" to the devices 11, 21, 31, and 41 to the physical rare subprogram 12.
”, “3”, and “9” according to a predetermined interface. Here, "1", "
"2" and "3" mean the logical addresses in operation, and "9"
means that it is on standby. The physical rare subprogram 12 sequentially runs the devices 11, 121, 31.41.
A command is sent on the common bus 1 to set the logical address for the number; That is, the control section 2 of the device 11
18, a physical rare subprogram 12 sequentially sends commands onto the common bus 1 from an address sending circuit (not shown) to first the device 21, then the device 31, then the device 411, and then the own device 11. and sends out a logical address, which is data.

In this case, the instruction is physical/logical address identification bit 5]
indicates a physical address, the address section 52 indicates the physical address of the device 21, 31, 41, 11 to be accessed, and the instruction code section 53 is a code meaning "latch the data value into the logical address register 214 of that device". It becomes. Further, on the data bus 3, a logical address to be set at the same time is sent. As a result, each device i11
, 21.degree. 31.41, the address (physical address and instruction) is latched into the address latch register 211 shown in FIG. 2, and the data (logical address) is latched into the data latch register 212 shown in FIG.

Since the physical/logical address identification bit 51 is a physical address, selector 2]5 is the physical address register 214.
The contents of are selected and sent to the address conveyor circuit 216. At the same time, the physical address of the address latch register 211 is also sent to the address conveyor circuit 216, so both addresses are compared and if they match, it is determined that the device is the corresponding device. If they match, the instruction code/decode circuit 21 is controlled by the conveyor circuit 216.
7 is activated, the decoding circuit 217 decodes the instruction code section 53 of the address latch register 211, and sends the decoding result to the control section 218. Control unit 218
Under the control of, the contents of the data latch register 212°,
That is, the logical address is sent to the logical address register 213 and latched.

By setting logical addresses for all devices 11, 21, 31.41 by the same operation.

Initial settings are completed.

After initial configuration, each device 11, 21, 31 performs two normal functions (for example, data transfer between devices) under the control of physical rare subprograms that operate according to the instructions of each ablicator program. are doing. In this case, the physical/logical address identification bit 51 in the instruction means a logical address, the address part 52 shows the logical address value of the device to be accessed, and the instruction code part 53 shows the code of the function.

FIG. 4 is an operational flowchart for transferring data between devices.

For example, when transferring data from device 31 to device 21, the address sent from device 31 is
It is latched into the address latch register 211 in 1, 21.41. Further, the transfer data sent out at the same time is transferred to each device 1711. :2L, latched into data latch register 212 in 41 (step?, 01.102)
. At this time, as shown in FIG. 2, since the physical/logical address identification bit 51 means a logical address, the selector 215 selects the logical address register 213 side,
The logical address of this device is sent to conveyor circuit 216.

Since the address field 52 in the address latch register 211 is also sent to the conveyor circuit 216, the two wheel addresses are compared in the conveyor circuit 21G (step 103).
). Then, in step 21, when a match is found, the decoding circuit 217 further decodes the contents of the instruction code section 53 of the address latch register 211, and sends the result to the control section 21.
8 (steps 104, 105), control unit 218
teeth.

By controlling the data latch register 212 according to the decoding result, the contents of the data latch register 212, that is, the transferred data, are sent out as indicated by the arrow and processed by a processing circuit (not shown) in the device (step 1
06,107,1.08).

FIG. 5 is a flowchart of a logical address replacement operation when a device becomes a failure.

Suppose that a failure occurs in the device 21 and an instruction to change the system configuration is sent to the physical configuration management program 14 on the device 11 (Step 2 OL 202).
, this transmission is performed by sending an alarm from the device 21 to the device 11 via the data bus 3 from an alarm circuit (not shown), so that the receiving circuit (not shown) of the device 11 receives this alarm, An interrupt is made to the management subprogram 14. This allows the physical configuration management program 14
issues an instruction to the physical rare subprogram 12, and the device 2
1's logical address from "2" to "9", and the logical address of device 41 from "9" to "2" (
Step 203). The method of resetting the logical address is as described above. That is, the logical address change command and the changed logical address are sent from the unillustrated transmission circuit of device 1 via address bus 2 and data bus 3 (step 204). The address latch registers 211 and data latch registers 212 of the devices 21, 31, and 41 contain instructions (logical address change instructions, physical addresses) sent via the address bus 2 and data bus 3.
and data (logical address after change) are latched (
Step 205). The selector 215 selects bit 5 of the physical/logical address Q21 of the address latch register 211.
Since 1 is the physical address, physical address register 2
14 side is selected and its contents are sent to the conveyor circuit 216.

On the other hand, the address section 52 of the address latch register 211
The physical address of is also sent to the conveyor circuit 216, where the two addresses are compared (step 206>, when they match, the instruction code decode circuit 217 is activated,
By decoding the instruction code, it is determined that it is a logical address change instruction (steps 207 and 20).
8).

According to the decoding result, the control unit 218 changes the contents of the data launch register 212, that is, the changed logical address, to 3
The fl address register 213 is loaded (steps 209, 110).

By resetting the logical address, the device 41 is incorporated into the system as being in operation, and the device 2 is removed from the system.

In this way, when switching to a spare device in the system due to the occurrence of a failure, etc., the physical system configuration is only recognized by the physical configuration management subprogram 14 on the master device 11, and other application programs and physical rare devices are aware of the physical system configuration. There is no need to be aware of the subprograms. Also,
The device 41, which originally existed as a pre-installed device, can be dynamically switched with other devices 1721 and 31 as long as they are functionally equivalent. As a result, the Yodate entrance is n
: m (n>m) (in this example, 2; 1),
The number of spare devices may be small compared to the number of operating devices.

〔Effect of the invention〕

As explained above, according to the present invention, when a device connected to a common bus has a spare device, it is possible to switch between functionally equivalent devices in any way, so that resources can be effectively used. It can be used. Further, since the program for controlling these devices can be incorporated without being conscious of the physical image, the configuration can be simplified.

[Brief explanation of the drawing]

Fig. 1 is a system configuration diagram showing one embodiment of the present invention;
The figure is a configuration diagram of the self-address recognition circuit in the device shown in Figure 1.
FIG. 3 is a format diagram of instructions used in the present invention, FIG. 4 is an operation flowchart of data transfer between devices, and FIG.
The figure is a flowchart of the logical address change operation in the event of a failure. 1: Common bus, 2 Near address bus, 3: Data bus, 1
1,21,31.41: Apparatus, 12,22°32.4
2: Physical rare subprogram that controls the device, 13,
23, 33.43 Near bridge program, 1:
Physical configuration management subprogram, 211 Near address latch register, 212: Data latch register, 213: Logical address register, 214: Physical address register,
215: Selector, 216: Address conveyor times M%
217: Instruction code/decode circuit, 218; Control unit,
51: Physical/logical address identification bit, 52 Near address section, 53: Instruction code section. Figure 1 L Figure 2 Figure 4 Figure 5

Claims (1)

[Claims] 1. In a system consisting of multiple devices connected to a common bus, where each of the devices accesses each other according to a unique physical address given in advance, a master device among the devices connects to each of the devices. By setting a logical address, from that point on, each of the above devices accesses each other according to the set logical address, and when switching the functional assignments of each device, the logical address is dynamically rewritten from the master device. A system configuration control method characterized by setting.