JPH06243101A - Inter-cpu communications system for multiprocessor system - Google Patents

Abstract

PURPOSE:To provide an inter-CPU communications system which never causes such abnormal processing as 'no response from another CPU', etc., nor deteriorates the system processing performance when the communication is carried out between CPUs in a multiprocessor system including plural CPUs of different processing speeds. CONSTITUTION:In a multiprocessor system including plural CPU1-CPUn of different processing speeds, a type storage part 21 stores the types of all CPUs of the system. When the inter-CPU communication is carried out, the communication starting CPU refers to the part 21 to confirm the types of itself and the opposite party CPU. Meanwhile various counters count the time when the starting CPU starts and then ends the periodical check of the end information on the inter-CPU communication area in a shared memory based on those confirmed types of CPUs. Then the values of these counters are corrected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to CPUs having different processing speeds.
The present invention relates to an inter-CPU communication method for performing communication between CPUs in a multiprocessor system in which

[0002]

2. Description of the Related Art FIG. 6 shows a configuration example of a multiprocessor system having a plurality (n) of CPUs and a common memory which can be commonly accessed by all the CPUs. In FIG. 6, the CPUs 1 to CPUn and the common memory 11 are connected via the system bus 12, and each CPU accesses the shared memory 11 to generate an interrupt to any other CPU, thereby performing communication between the CPUs. It is carried out.

In this multiprocessor system, FIG.
As shown in FIG.
---, n-1, n corresponding to fixed areas 11-1
11-n are assigned, and fixed areas for writing communication information between CPUs are provided in these fixed areas corresponding to the CPUs other than the self.

In FIG. 7, "interrupt (x → y)"
Indicates that an interrupt from CPUx to CPUy occurs. However, the shaded area in the fixed area for writing communication information between CPUs in FIG. 7 corresponds to the fixed area for writing communication information between the same CPUs, but communication between the same CPUs is possible in the local memory in the CPUs. Therefore, shared memory is not used.

In the multiprocessor system shown in FIG. 7, when each CPU uses the shared memory 11 for inter-CPU communication, for example, when the CPU 2 issues an interrupt to the CPU 1, the fixed area 11-corresponding to the CPU 1 The communication information is written in the fixed area (2 → 1) for writing communication information between CPUs for self in 1 and the “interrupt (2
→ 1) ”is generated. On the other hand, in the CPU 1, when the “interrupt (2 → 1)” occurs, the CPU corresponding to the CPU 2
The fixed area for writing inter-communication information (2 → 1) is accessed and interrupt processing is executed. In this case, the addresses of the fixed areas for writing communication information between CPUs in the shared memory are recognized in advance by both communicating CPUs.

In the multiprocessor system as shown in FIG. 7, (n × (n-1)) fixed areas for writing communication information between CPUs shown in FIG. 8 are set in the shared memory. As shown in the figure, in this fixed area for writing communication information between CPUs, an issuer CPU-ID area in which an inter-CPU communication request (system call) issuer CPU writes its own CPU-ID (identification number) and a communication destination CPU are An end information area in which communication status information between CPUs (processing, processing end, etc.) is entered,
INT number area to enter the interrupt type number, AX / BX
In the CX and DX (register) areas, the issuing CPU writes the system call type, various common resource numbers, message addresses, and other parameters, and the communication destination CP
U is composed of an error code, other parameters, and other communication information area.

CPU of this microprocessor system
The inter-communication procedure will be described below with reference to FIG. First, a task (hereinafter referred to as task A) in the CPU 1 issues a system call for inter-CPU communication request to the CPU 2.

Next, the OS of the CPU 1 sends various parameters of the system call (issuer CPU-ID, interrupt type number, system call type, various common resource numbers, message addresses, etc.) to the CPU in the shared memory.
The data is written in the fixed area (1 → 2) for writing CPU-to-CPU communication information of CPU1 → CPU2 in the inter-communication area. After that, the OS of the CPU 1 makes an inter-CPU communication request (that is, an interrupt) to the OS of the CPU 2.

When there is an interrupt from the CPU 1, the CP
U2 suspends task B being processed, and the OS of CPU2
By the interrupt from the CPU 1, the CP in the shared memory is first
The parameters of the inter-CPU communication request are read from the fixed area (1 → 2) for writing the inter-CPU communication information of CPU1 → CPU2 in the inter-U communication area. Next, the OS of the CPU 2 performs processing for the system call. When the processing corresponding to the system call is completed, the OS of the CPU 2 sets the end information of the fixed area (1 → 2) for writing the communication information between the CPUs 1 → 2 of the CPU 1 → CPU 2 in the communication area between the CPUs in the shared memory to “ Enter the code "End of processing" and write various parameters such as error code. After that, the task B is restarted.

On the other hand, the OS of the CPU 1 confirms whether the CPU 2 has read various parameters written in the inter-CPU communication area in the shared memory by the CPU 2 in the above process. The content of the end information written in the inter-CPU communication area is read. If “processing end” is not written in the end information, the process of checking the end information again by repeating the retry after the predetermined check waiting time has elapsed,
If the end information does not become “processing end” even after the retry is repeated a predetermined number of times, the task A is notified of the information “no other CPU responds”. The OS of the CPU 1 notifies the task A of information of various parameters when the end information of the inter-CPU communication area is “processing end”.

The task A reads the return value and the values of various parameters and performs the subsequent processing. As described above, it is possible to exchange necessary parameters between the CPU 1 and the CPU 2 to realize the inter-CPU communication.

Next, O of the CPU 1 that issued the system call
S is the CPU after issuing the system call for the inter-CPU communication request
The procedure for checking the intercommunication end information will be described with reference to the flowchart of FIG.

First, the OS of the CPU 1 makes an inter-CPU communication request (process) to the CPU 2 (step S).
1), the number of loops (the value of the initial check wait counter) is read (step S2), and the process waits until the initial check waiting time elapses (step S3). This initial check waiting time can be calculated by the following formula: initial check waiting time = 1 loop processing time × initial check waiting counter value.

After the initial check waiting time has elapsed (step S3), the CPU1 in the inter-CPU communication area in the shared memory
→ CPU2 fixed area for writing communication information between CPUs (1 →
The end information of 2) is checked (step S4). When the content of the end information is “processing end”, that is, when the CPU 2 turns O
When S has already completed the processing corresponding to the communication between CPUs, the task A is notified of information of various parameters such as an error code (step S5).

On the other hand, when the content of the end information is "processing not completed", the loop count (value of the check wait counter) and the retry count (value of the retry counter) are read (steps S6 and S7), and the check waiting time is reached. Waits until (step S8). This check waiting time can be calculated by checking wait time = 1 loop processing time × check waiting counter value.

After the check waiting time has elapsed (step 8), the end information is checked again (step S9),
If the content has already been “processed”, information of various parameters is notified to the task A (step S
5). On the other hand, if the content is still "processing not completed", the value of the retry counter is decremented by one (step S10), and the value of the retry counter is "0", that is, the predetermined number of retries is completed. It is checked whether it has been done (step S11). If the predetermined number of retries has not ended, the end information is checked again after the check waiting time of step S8 has elapsed (step S9).

This process is repeated a predetermined number of times until the content of the end information is "processing completed" (steps S10 and S11), and if the content of the end information is not "processing completed", the communication destination CPU It is presumed that there is a fault in the task A, and task A is notified of the information "no other CPU responded" (step S12).

FIG. 11 shows the CPU that issued the system call.
A time chart for explaining the operation of the OS of 1 for checking the end information of the communication between CPUs is shown. This time chart is a time chart of the flowchart of FIG.

OS of CPU 1 that issued the system call
Waits for the OS of the communication destination CPU 2 to perform a process corresponding to the system call and write “processing end” in the end information of the communication region between the CPUs after making the inter-CPU communication request to the communication destination CPU. . At this time, the time for the OS of the communication destination CPU 2 to process the system call varies depending on the type of system call, so that the initial check waiting time is the shortest expected time for the OS of the communication destination CPU 2 to perform the processing. Set the value of the initial check wait counter, and the time of (initial check wait time + check wait time x retry counter value) is the CP of the communication destination.
The initial values of the check waiting time and the retry counter are set so that the OS of U2 has a slight margin in the expected maximum time for the processing.

[0020]

In a multiprocessor system as shown in FIG. 6, each CPU is normally used.
Since the processing speed of each is the same, each CP of the communication destination
The time required for the processing (processing of FIG. 9) for the inter-CPU communication system call performed by the OS of U is the same for all CPUs.

Therefore, the values of the initial check wait counter, the check wait counter, and the retry counter shown in FIGS. 10 and 11 are common to each CPU, and only one of these values is defined in the multiprocessor system.

However, in a multiprocessor system as shown in FIG. 6, a specific CPU (hereinafter, CPU)
In some cases, there is a function requiring a high processing speed. In that case, it is necessary to increase the function of the CPU 1, that is, the processing speed. Hereinafter, the CPU 1 having a high processing speed is referred to as a high-speed CPU (or a 32-bit C
PU) and other currently used CPU2 to CPUn
Is called a low-speed CPU (or 16-bit CPU).

In the above case, it is ideal to unify all the CPUs in the multiprocessor system into high-speed CPUs, but this cannot be realized due to reasons of cost, inventory, etc.
There may be a multiprocessor system configuration in which the high speed CPU and the high speed CPU are mixed.

In this case, regarding the time required for the OS of the communication destination CPU to perform the processing (see FIG. 9) for the inter-CPU communication system call, a 32-bit high-speed CPU
The time required for one OS to perform its processing is shorter than the time required for the same processing to be performed by the OSs of the 16-bit low-speed CPU2 to CPUn, and is about 1/2. .

Naturally, if the processing speed of the OS differs, the time required for one loop processing of the dynamic loop also differs, and the 16-bit low-speed CPU2 to CPUn
The time required for the OS to perform one loop processing of the dynamic loop is longer than that in the case of the 32-bit high speed CPU 1, and is about three times as long.

Even in a multiprocessor system in which high-speed and low-speed CPUs are mixed, a 16-bit low-speed CPU 2
~ When CPUs communicate with each other, the OS of the system call issuer CPU and the communication destination CPU
Since the processing speeds of the two OSs are the same, the conventional method (the initial check waiting counter in the multiprocessor system,
There is no problem even if the check wait counter and retry counter values are common and only one is defined. However, 32-bit high-speed CPU 1 to 16-bit low-speed CPU 2 to C
Inter-CPU communication to PUn, or 16-bit low-speed C
C from PU2-CPUn to 32-bit high-speed CPU1
When performing PU-to-PU communication, the CP that issued the system call
Since the processing speeds of U and the communication destination CPU are different, the conventional method has the following problems.

First, referring to FIG. 12, a CP is sent from the high speed CPU 1 as the system call issuer to the low speed CPU 2 as the communication destination.
The problems in performing U-to-U communication will be described.

Task A of the high-speed CPU 1 issues a system call for inter-CPU communication to the low-speed CPU 2 (see FIG. 9).
Processing) and the OS of the high-speed CPU 1 are C in the shared memory.
After writing various parameters of the system call to the PU communication area (processing in FIG. 9), the CPU communication request is issued to the low-speed CPU 2 (processing in FIG. 9).

The OS of the high-speed CPU 1 then waits for the OS of the low-speed CPU 2 to finish the processing for the system call by the method shown in FIGS.
The time required for the OS of PU1 to perform one loop of the dynamic loop is 1/3 as compared with the case of the low-speed CPU 2.

Therefore, according to the conventional method, as shown in FIG. 12, the longest waiting time for the CPU 1 to check the presence or absence of the “processing end” notification from the CPU 2 (= initial check waiting time + check waiting time ×) Even if it waits until the end information reaches "processing end" over the retry counter, the CPU 2 on the low speed side cannot finish the processing during that time, and therefore the end information does not become "processing end", so the CPU 2 on the low speed side Despite the normal execution of the system call for the system call, the OS of the high-speed CPU 1 notifies task A of the information "no other CPU responded" and the CPU 2 has a failure. There is a problem of making a judgment.

Next, referring to FIG. 9, the CPU 2 on the low speed side
A problem in performing inter-CPU communication from the high-speed side to the CPU 1 will be described.

Task B of CPU 2 on the low speed side is C on the high speed side
When a system call for inter-CPU communication is issued to PU1, the OS of the CPU 2 on the low speed side is the CPU in the shared memory.
After writing various parameters of the system call to the inter-communication area, the inter-CPU communication request is issued to the high-speed CPU 1.

After that, the OS of the CPU 2 on the low speed side is
0 and the method shown in FIG.
Although it waits for S to finish the processing for the system call, the processing speed of the OS of the high-speed CPU 1 is twice as fast as the OS of the low-speed CPU 2 as described above.

Therefore, according to the conventional method, as shown in FIG. 13, when the CPU 2 on the low speed side waits for the initial check waiting time, the CPU 1 on the high speed side has already finished the processing for the system call. In particular, in the type of system call whose processing time is the shortest, the processing is completed when half the initial check waiting time has elapsed.
Therefore, there is a problem in that the time when the OS of the CPU 2 on the low speed side starts the subsequent processing is delayed compared to the time when the CPU 1 on the high speed side finishes the processing, and the processing performance of the system deteriorates.

The present invention has been made in view of the above problems, and an object of the present invention is to provide C in a multiprocessor system in which CPUs having different processing speeds are mixed.
When performing CPU-to-CPU communication between PUs,
This is to prevent abnormal processing such as "no response" from occurring or the processing performance of the system from deteriorating.

[0036]

FIG. 1 is a diagram illustrating the principle of the present invention. The inter-CPU communication method in the multiprocessor system of the present invention is based on CPUs 1 to 1 having different processing speeds.
In a multiprocessor system in which CPUs coexist, a type storage unit 21 that stores the types of all CPUs in the system is provided, and when performing inter-CPU communication, the communication source CPU refers to the type storage unit 21 to communicate with the communication source CPUs. Communication destination CPU
The type of each counter is checked, and based on the result, various counter values for counting the time from when the communication source CPU periodically checks the end information of the inter-CPU communication area in the shared memory to when it ends The feature is that correction is performed and communication between CPUs is performed.

In the above inter-CPU communication method, when the processing speeds of the communication source CPU and the communication destination CPU are different,
As the correction of the various counters, the value of the initial check waiting counter and the value of the check waiting counter or the retry counter can be corrected.

[0038]

[Function] Here, the CPU 1 is a high-speed CPU, and another C
PU2-CPUn as low-speed CPU, these CPUs
It is assumed that the CPUs communicate with each other.

An area 21 for the CPU type table is newly provided on the shared memory 2 or the like so that each CPU can execute its own C at system startup.
PU is the type (type of CPU such as high speed or low speed) is C
Write to the PU type storage unit 21. When actually making a communication request between CPUs, the OS of the communication source CPU confirms the types of the communication source CPU and the communication destination CPU in the CPU type table in the shared memory 2.

First, if the source CPU and the destination CPU are low-speed CPUs of the same type, that is, CPU2 to CPUn
In the case of mutual communication between CPUs, various counters such as an initial check waiting counter, a check waiting counter, and a retry counter are used as they are, as in the conventional method.

Next, when the communication source CPU is the high-speed CPU 1 and the communication destination CPU is the low-speed CPU 2 to CPUn, the time required for one dynamic loop of the communication high-speed CPU 1 is 1 to the communication destination low-speed CPU 2 to CPUn. Since it is 1 / m of the above case, the waiting time for the high-speed CPU 1 to check is 1 / m of the normal time. Therefore, a counter or the like for the high-speed CPU to count the check waiting time is multiplied by m times the normal value.

On the contrary, the communication source CPU 1 is the low speed CPUs 2 to C.
When the communication destination CPU is the high-speed CPU 1 in PUn, the time taken for the communication-destination high-speed CPU 1 to process the inter-CPU communication system call is 1 / k of the case where the communication-source low-speed CPU 2 to CPUn. Therefore, a low-speed CPU uses a counter or the like for counting the check waiting time, which is 1 / k
To do so.

[0043]

Embodiments of the present invention will be described below with reference to the drawings. Here, the 32-bit high-speed CPU 1 and the other 16
Consider a multiprocessor system in which low-speed CPU2 to CPUn of bits coexist, and inter-CPU communication is performed between the CPUs with a shared memory interposed in the system.

As shown in FIG. 3, a new CPU type table area is provided on the shared memory so that each CP can be activated at system startup.
U writes the type of its own CPU (type of 16-bit low-speed CPU or 32-bit high-speed CPU) in the CPU type table. When actually making a communication request between CPUs, the communication source CP
U's OS is the source CPU of the CPU type table in the shared memory
And the type of the communication destination CPU are confirmed. Then, the CP is transmitted between the communication source CPU and the communication destination CPU that have the same or different processing speeds.
When performing the U-to-U communication, the initial check waiting counter, the check waiting counter, and the retry counter are corrected according to Table 1 according to the confirmed type.

First, in the case of a 16-bit low-speed CPU in which the source CPU and the destination CPU are of the same type, that is, the CPU
In the case of the communication between the CPUs 2 to CPUn, the initial check waiting counter, the check waiting counter, and the retry counter are used as they are as in the conventional method.

Next, the 32-bit high-speed CPUs 1 to 16
A procedure for performing inter-CPU communication with the bit low-speed CPU 2 will be described below with reference to FIG.

In such a case, the time required for one loop of the dynamic loop of the OS of the communication source CPU 1 is one-third that of the normal communication destination CPUs 2 to CPUn. Time becomes 1/3 of usual time. Therefore, the value of the initial check waiting counter is tripled as usual, and the value of the check waiting counter or the retry counter is tripled as usual.

That is, when the OS of the CPU 1 requests the CPU 2 to communicate with the CPU 2 (processing of FIG. 9), the CP
The OS of U1 is CPU by the method shown in FIG. 10 and FIG.
Wait until the OS of No. 2 finishes the processing for the system call, but the time required for one dynamic loop of the OS of CPU 1 (here, 10 μsec) is
OS takes one loop (30μse here)
It is 1/3 compared to c).

Therefore, first, by correcting the value of the initial check counter to three times (here, 300 times) that of the OS of the CPU 2 (here, 100 times), the initial check waiting time is 16 bits CPU. Mutual C
It is equivalent to that in the communication between PUs (here, 3 msec).

The value of the check waiting counter is set to the CPU2.
3 times the OS (here, 10 times) (30 here)
CPU1 by correcting the value of the retry counter to three times the OS of the CPU2 (here, 14 times) (42 times here).
From the time when the OS periodically starts checking the end information of the inter-CPU communication area in the shared memory until the end of the check (= 1 loop processing time x check waiting counter x
The number of retries is C between 16-bit low-speed CPUs.
It is the same as in PU communication (4.2 msec).

As a result, as shown in FIG.
Even if the OS of U2 finishes the processing for the system call for inter-CPU communication at any timing, the OS of high-speed CPU1
Can normally read that the end information of the inter-CPU communication area in the shared memory has been rewritten to the end of processing, which can solve the problem in the conventional technique as shown in FIG.

Next, referring to FIG. 5, a procedure for performing inter-CPU communication from the 16-bit low-speed CPU 2 to the 32-bit high-speed CPU 1 will be described. If the source CPU 1 is a 16-bit low-speed CPU2 to CPUn and the destination CPU is a 32-bit high-speed CPU 1 (see FIG. 13), the destination CP
The time required for the OS of U1 to process the inter-CPU communication system call is half that of the normal communication source CPUs 2 to CPUn. Therefore, the value of the initial check wait counter is set to 1/2 of the normal value, and the value of the check wait counter or the retry counter is set to 1/2 of the normal value.

That is, the OS of the low-speed CPU 2 is the high-speed CP
When an inter-CPU communication request (processing) is issued to U1, C
The OS of the PU2 waits for the OS of the high-speed CPU 1 to finish the processing for the system call by the method shown in FIG. 10 or 11, but the processing speed of the OS of the high-speed CPU 1 is the low speed C.
Twice as fast as PU2.

Therefore, first, the value of the initial check counter is 1 / th of the OS of the high-speed CPU 1 (here, 100 times).
By correcting to 2 (here, 50 times), the initial check waiting time becomes the same (1.5 msec) as in the inter-CPU communication between 32-bit high speed CPUs.

In addition, the value of the check waiting counter is set to the high-speed CP.
Correct the value of the retry counter value to 1/2 of the OS of U1 (here, 10 times) (5 times here), or set the value of the retry counter to 1/2 of the OS of high-speed CPU 1 (14 times here). By correcting to (7 times here),
The time from when the OS of the low-speed CPU 2 regularly checks the end information of the inter-CPU communication area in the shared memory to when it finishes checking (= 1 loop processing time x check waiting counter x number of retries) is 32 bits. High speed CP
Equivalent to communication between CPUs between U (2.1m
sec).

As a result, as shown in FIG. 5, no matter which timing the OS of the high-speed CPU 1 of the communication destination ends the processing for the system call of the inter-CPU communication, the OS of the low-speed CPU 2 of the communication source is the CPU of the shared memory. It is possible to normally read that the end information of the inter-communication area is rewritten to "end of processing", and thus it is possible to solve the problem in the prior art as described in FIG.

Finally, the inter-CPU communication between the 32-bit high-speed CPUs when there are a plurality of 32-bit high-speed CPUs in the multiprocessor system will be described. In this way, in the case of a 32-bit high-speed CPU in which the source CPU and the destination CPU have the same type, the value of the initial check wait counter is set to 3/2 and the value of the check wait counter or the retry counter is set to 3/2. Good.

That is, from FIG. 4 and FIG. 5, the initial check waiting time is 1.5 msec, the time required for one loop of the dynamic loop is 10 μsec, and (1 loop processing time × check waiting counter × retry counter) ) Is 2.1 msec, the value of the initial check waiting counter is corrected to 150, and the value of (check waiting counter x retry counter) is corrected to 210, so that the OS of the communication source CPU is corrected. Is the destination C
It becomes possible to normally receive the information of "processing completed" from the OS of the PU.

[0059]

As described above, according to the present invention, when performing inter-CPU communication between CPUs in a multiprocessor system in which CPUs having different processing speeds are mixed, an abnormality such as "no other CPU responds" is generated. It is possible to prevent the occurrence of processing or the deterioration of the processing performance of the system.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating an example of a method of correcting a processing check wait counter, a check wait counter, and a retry counter between a communication source CPU and a communication destination CPU in an inter-CPU communication system as an embodiment of the present invention.

FIG. 3 is a diagram showing an example of a CPU type table on a shared memory in the embodiment system.

FIG. 4 illustrates a high speed CPU to a low speed CPU in the embodiment system.
FIG. 6 is a diagram showing a time chart of an inter-CPU communication request to the CPU.

FIG. 5 is a low-speed to high-speed CPU in the embodiment system.
FIG. 6 is a diagram showing a time chart of an inter-CPU communication request to the CPU.

FIG. 6 is a diagram illustrating a configuration example of a multiprocessor system.

FIG. 7 is a diagram showing a configuration of an inter-CPU communication area in a shared memory in a multiprocessor system.

FIG. 8 is a diagram illustrating the contents of a fixed area for writing communication information between CPUs.

FIG. 9 is a diagram illustrating a communication procedure between CPUs in a multiprocessor system.

FIG. 10: The OS of the CPU that issued the system call is CP
It is a flowchart which shows the procedure which checks the completion information of communication between U.

FIG. 11: The OS of the CPU that issued the system call is CP
7 is a time chart illustrating an operation of checking end information of U-to-U communication.

FIG. 12 is a diagram for explaining a problem of the conventional technique when the inter-CPU communication request is issued from the high-speed CPU to the low-speed CPU.

FIG. 13 is a diagram for explaining a problem of the conventional technique when the inter-CPU communication request is issued from the low speed CPU to the high speed CPU.

[Explanation of symbols]

 CPU1 to CPUn Central processing unit 11 Common memory 12 System bus 21 Type storage unit

Claims (2)

[Claims] 1. CPUs having different processing speeds (CPU1 to C)
In a multiprocessor system in which PUN) are mixed, a type storage unit (2) that stores the types of all CPUs in the system
1) is provided, and when performing communication between CPUs, the communication source CPU refers to the type storage unit to check the types of the communication source CPU and the communication destination CPU, and based on the result, the communication source CPU periodically C in a multiprocessor system characterized by correcting the values of various counters for counting the time from the start to the end of checking the end information of the inter-CPU communication area in the shared memory and performing the inter-CPU communication
Communication method between PUs. 2. When the communication source CPU and the communication destination CPU have different processing speeds, the value of the initial check wait counter and the value of the check wait counter or the retry counter are corrected as corrections of the various counters. A CP in the multiprocessor system according to claim 1.
U-to-U communication method.