JPH0535457B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a peripheral device and a central processing unit (hereinafter referred to as
The present invention relates to an information processing device that allows flexible configuration between CPUs (referred to as CPUs).

[Prior art and its problems]

In a typical computer system,
The configuration of various system components is fixed. In the static configuration of prior art computing systems, a central processing unit (CPU) 50 is coupled to peripheral devices 51, 52, 53, and 54, as shown in FIG. Each of the peripheral devices 51 to 54 includes, for example, a storage device such as a random access memory (RAM) or a read-only memory (ROM);
It may be a device other than a storage device, such as a display device, a printer, or a communication control device. Peripherals 51 - 54 are coupled to CPU 50 via bus 65 . Peripheral devices 51-54 are each assigned a fixed address. The CPU 50 is connected to each of the peripheral devices 51 to 54,
They can communicate with each other independently using their fixed addresses. Peripheral devices 51-54 are coupled to corresponding address comparison registers 61-64 and address selection circuits 71-74, respectively. When the CPU 50 or other device sends an instruction onto the bus 65, the address comparison registers 61-64 and the address selection circuits 71-
74 checks this command and sends each peripheral device 51 to
54 can only respond to instructions that include a fixed address assigned to that peripheral.

Using static configuration schemes such as those described above inherently limits the flexibility of the system. for example,
Adding or removing equipment becomes difficult. This is because if you change the physical configuration within the system,
This is because it is required to provide access to a new device or to indicate that a removed device no longer exists.

[Purpose of the invention]

The present invention eliminates the problems of the prior art described above,
The purpose is to provide an information processing device that allows flexible system configuration.

[Summary of the invention]

According to a preferred embodiment of the invention, a CPU;
An information processing device including peripheral devices dynamically configured by this CPU is provided. Each peripheral device has a built-in identification code that identifies its characteristics. By reading this identification code, the CPU determines the type of peripheral device (e.g.
ROM, RAM, control device, etc.) and other pertinent information related to the peripheral device (eg, memory size of the storage device).

Each peripheral also has a configuration register. The number of bits in each configuration register is equal to or less than the number of bits used by the information processing device to address the entire address space. Each peripheral also has a 1-bit register called a configuration flag. The state of a configuration flag in a peripheral device indicates whether that peripheral is under configuration control by the CPU and, therefore, whether the contents of its configuration registers are valid. be.

After characterizing the peripheral device through the identification code, the CPU uses this information to allocate address space to the peripheral device. Next, the CPU
Writes one or more bits to the configuration register to set the peripheral's configuration flag and include the peripheral in the system configuration. Similarly,
The CPU removes the peripheral from the system configuration by clearing the peripheral's configuration flag. With this method, the CPU can dynamically change the system configuration of the information processing device.

As can be seen from the above explanation, the peripheral devices referred to in this application include not only input/output devices;
It should be understood that it includes various devices such as RAM, ROM, etc.

[Embodiments of the invention]

FIG. 2 shows a system configuration of an information processing apparatus according to an embodiment of the present invention. In Figure 2, CPU20
1 is a series of peripheral devices 101, 111, 121,
131, 141, 151. Each peripheral device 101, 111, 121, 131, 141, 1
51 are the corresponding buses 109, 119, 1, respectively.
29, 139, 149, 159. Bus 109, 119, 129, 139, 14
9,159 are connected in parallel to a bus 202, and this bus 202 is further coupled to the CPU 201.

The CPU 201 uses buses 109, 119, 129,
Bus 202 coupled to 139, 149, 159
Upper peripheral devices 101, 111, 121, 131,
Commands and data are sent to 141 and 151. In addition, the CPU 201 is connected to the bus 2 of the CPU 201.
Buses 109, 119, 129, coupled to 02
peripheral device 1 through 139, 149, and 159, respectively.
01,111,121,131,141,151
Receive data from.

Bus 109, 119, 129, 139, 14
9,159 all have the same configuration. FIG. 3 shows the configuration of the bus 109. Each bus includes a ground line 106, a power line 105, and a command line 10.
4, consists of a strobe line 103 and some data lines 102. In this embodiment, four data lines 102 are provided. Ground line 106 is maintained at a constant voltage of 0.0V. The power line 105 is different from 0.0V,
For example, it is held at a constant voltage of +4.5V. The instruction line is normally driven by the CPU 201, but
One or more peripheral devices 101, 111, 1
21, 131, 141, 151. strobe line 103
is driven only by the CPU 201. Data line 102 is connected to CPU 201 or peripheral devices 101, 111, 121, 131, 14.
1,151. These lines have a logic value of 0 when the voltage is the same as that of the ground line 106, and a logic value of 1 when the voltage is the same as that of the power line 105. strobe line 103
is active when the logic value is 0, and is inactive when the logic value is 1. Command line 104 is active when it is a logic zero and inactive when it is a logic one. The information on the data line is data when the command line is active and is an instruction when the command line is inactive. Also,
The information on data line 102 is
It is valid immediately before and during the transition of line 103 from the active state to the inactive state.

In FIG. 2, peripheral devices 101, 111, 1
21,131 is a replaceable module.
On the other hand, peripheral devices 141 and 151 are fixedly attached. The address settings of these peripheral devices are exactly the same as those according to the prior art. Specifically, unique addresses are assigned to each of these peripheral devices from the initial stages of design and manufacturing. These peripheral devices thus have means for decoding the addresses assigned to them in advance, and detect access to them. Note that since the CPU "knows" what addresses have already been assigned to these peripheral devices, the peripheral devices 101, 111, 121, 13, which are replaceable modules,
It also knows which remaining addresses can be assigned to 1. Therefore, there is no problem even if permanently attached peripheral devices and replaceable peripheral devices coexist. Such a fixed address setting/access detection method is well known in the prior art and is not important for understanding the present invention, so further explanation will be omitted.

Replaceable peripheral devices 101, 111, 121,
131 is the daisy chain 203 or 20, respectively.
Combined with 4. In this embodiment, the peripheral device 10
1, 111, 121 are coupled to the daisy chain 203 coming out of the CPU 201. Peripheral devices 131 are also coupled to daisy chain 204, which also originates from CPU 201. Daisy chain 203 exits CPU 201 , enters peripheral device 101 at daisy chain input 107 , and exits at daisy chain output 108 . Next, the daisy chain input 117 to the peripheral device 111
It enters from the daisy chain output 118 and exits from the daisy chain output 118. It also enters peripheral device 121 at daisy chain input 127 and exits at daisy chain output 128 . Daisy chain 203 ends here. On the other hand, daisy chain 204 uses CPU2
01, enters the peripheral device 131 through the daisy chain input 137, and enters the daisy chain output 13.
Leave from 8. The daisy chain 204 ends here. Daisy chain 203 and 204 are
It is driven by the CPU 201. The daisy chains 203 and 204 are activated when the logic value is 1, and are inactivated when the logic value is 0.

FIG. 1 shows registers within the peripheral device 101. As shown in FIG. Identification code register (ID) 251 (here, 20 bits) contains information that identifies the characteristics of peripheral device 101. CPU201 has ID2
51, the functions of the peripheral device 101 (for example, if this peripheral device 101 is ROM, RAM,
It is possible to check whether the peripheral device 101 is a control device or an input/output device mapped to memory) and other information regarding this peripheral device 101 (for example, memory capacity).
Replaceable peripheral devices 101, 111, 121, 1
ID is required only for 31. Fixedly attached peripheral devices 141, 151 do not require an ID.

Peripheral device 101 also has configuration registers 252. The bit length of configuration register 252 is
The number of bits required for the CPU 201 to access the entire address space (hereinafter referred to as CPU address length).
For example, the CPU address length in this embodiment is 20 bits). For example, configuration register 25
2 may be 12 bits long. On the other hand, peripheral device 1
11, 121, 131, 141, and 151 may have more or fewer bits of configuration registers depending on the memory size each peripheral has. The contents of configuration register 252 establish for peripheral device 101 the memory address that peripheral device 101 was assigned by CPU 201 .

Configuration flag 253 is a one bit long register that is set when CPU 201 assigns a memory address to peripheral device 101 (ie, when peripheral device 101 is incorporated into the system configuration). Also, if configuration flag 253 is reset, then CPU 201 has not yet assigned a memory address to this peripheral device 101, or the address was previously deallocated (i.e.,
(Peripheral device 101 has been removed from the system configuration)
That's what I understand.

The peripheral device 101 also includes a data line 102.
An instruction register 256 having a number of bits equal to the number of bits (that is, 4 bits in this embodiment) is provided. The function of the instruction register 256 is that the CPU 20
It is to memorize the current command sent from 1. Please refer to Table 1 for instructions. Peripheral devices 111, 121, 131, 141, 151
also each have an instruction register.

The peripheral device 101 also includes data pointers,
A register (DP) 254 and a program counter register (PC) 255 are also provided.
DP 254 and PC 255 each have the same bit length as the CPU address length. Peripheral devices 111, 121,
DPs are also provided at 131, 141, and 151, respectively. Furthermore, depending on the function, a PC may also be provided. These registers DP and PC are
Instruction ID and instruction as explained below
It is not related to the incorporation of this peripheral device into the system configuration using CONFIGURE, that is, the address setting of this peripheral device itself. As explained below, these registers are used to determine when a peripheral device's address is set, by taking the address given by the CPU to access the peripheral and comparing it to the configuration registers. It is used for the purpose of determining whether or not it is pointing to you.

If the peripheral device 101 is not incorporated into the system configuration, the CPU 201 can incorporate it into the system configuration as follows. CPU20
1, an address range having one or more addresses directly addressable by CPU 20
1 is specified for peripheral devices. To do this, CPU 201 first activates daisy chain input 107. Next, CPU201
ID2 to read the characteristics of the peripheral device 101
Check 51. To do this, use the instruction IDs in Table 1 at the end of this document. This results in
Having learned the characteristics of the peripheral device 101 and determined the address to be set, the CPU 201 then issues an instruction.
Issue CONFIGURE (i.e. the instruction
sends the binary code corresponding to CONFIGURE). Then the configuration address (here 20 bits)
is transferred to the peripheral device 101. Peripheral device 101
copies the upper 12 bits of the received configuration address to configuration register 252. Additionally configuration flag 2
53 to indicate that it has been incorporated into the system configuration.

CPU 201 can also deselect the memory address of peripheral device 101 (ie, remove it from the system configuration). To perform this operation, CPU 201 issues the instruction LOAD DP (see Table 1) to transfer, via data bus 201, a 20-bit address corresponding to the configuration address assigned to peripheral device 101. Each peripheral device 101, 111, 121, 131, 14
1,151 takes this 20-bit address and places it in the DP. The CPU 201 then executes the instruction
Send UNCONFIGURE (see Table 1). Each peripheral device 101, 111, 121, 131, 14
1,151 is the contents of its own configuration register and DP
Compare with the corresponding number of high-order bits in the register. In this case, the address stored in the DP register corresponds to the configuration address assigned to peripheral device 101, so peripheral device 101 resets configuration flag 253.

The CPU 201 can include or remove other peripheral devices from the system configuration in the same way that the peripheral device 101 is included or removed from the system configuration. Since each peripheral device is given a unique configuration address when incorporated into the system configuration, the CPU 201
1, 121, 131, 141, and 151 can be individually addressed.

When a peripheral device's configuration flag is reset, the peripheral device deactivates its daisy chain output (logic value 0). Therefore, if the peripheral device 101 is not included in the system configuration,
Daisy chain output 108 is held inactive regardless of the value of daisy chain input 107. When a peripheral's configuration flag is set, that peripheral forces its daisy chain output to the same value as its daisy chain input. Thus, when peripheral device 101 is included in the system configuration (ie, configuration flag 253 is set), its daisy chain output 108 is held at the same logic value as daisy chain input 107.

When the peripheral device 101 is included in the system configuration, an instruction issued from the CPU 201 compares the address given via the bus 109 with the contents of the configuration register 252, and determines whether the given address is assigned to itself. Determine whether it points to the specified address. For example, the command
When PCRREAD is issued, the peripheral device 101:
In order to check whether the CPU 201 is addressing the memory space in the peripheral device 101, the PC 25
5 and the contents of configuration register 252. Similarly, upon receiving the instruction PCRREAD, each peripheral device 111, 121, 131, 141, 151
compares the contents of the PC with the contents of the configuration register to see if CPU 201 is addressing itself. Only the peripheral devices addressed by the CPU 201 operate in response to instructions issued by the CPU 201.

Each peripheral device 101, 111, 121, 131,
PCs 141 and 151 always have the same address value. In other words, CPU2
When 01 issues the command LOAD PC, each peripheral device 101, 111, 121, 131, 141, 15
1 because it simultaneously loads new values into its own PC. When the loading of the address value to the PC in each peripheral device is completed, the instruction switches to the READ PC instruction, as shown in the explanation of the LOAD PC instruction in Table 1. When a peripheral device determines that an address in the PC is the address assigned to it, that peripheral device reads out a program instruction from the address indicated by the PC, that is, the program counter, and sends it to the CPU 201. Similarly, each peripheral device 101, 111, 121, 13
All DPs 1, 141, and 151 always contain the same address value. This person is
The command LOAD DP causes each peripheral to be loaded simultaneously. As the name suggests, the DP is used for accessing normal data.

The CPU 201 keeps the strobe line 103 inactive except when performing nibble transfer (transfer in units of 4 bits here, as seen from the number of data lines) through the data line 102. ing. data line 10
During execution of nibble transfer through 2, CPU201
performs the strobe operation as shown in Table 1 (that is, once strobe line 103 is activated and then deactivated).

The instruction code (i.e., binary code, see Table 1) is sent to the peripheral devices 101, 111, 121, 13.
Unless you are forwarding to 1,141,151,
U201 holds command line 104 inactive. In order to send out the instruction code, the CPU 201
sets a logic value (ie, logic value 0 or 1) on data line 102 that corresponds to the instruction code (see Table 1) of each instruction. The CPU 201 then activates the instruction line 104 and strobes.
Line 103 is strobed (ie, activated and then deactivated). Each peripheral device 101, 111, 121, 1
31, 141, 151 are strobe line 1
03 is deactivated by CPU 201, it copies the instruction code to an instruction register (eg, instruction register 256 of peripheral device 101). Each peripheral device 101, 111, 121, 13
The contents of instruction registers 1,141,151 are interpreted by the peripheral in question. With this interpretation,
It is determined how each peripheral responds to subsequent data sent on the data line, or whether it provides data on the data line 102.

Table 1 below shows instructions and their binary codes and peripherals 101, 111, 121, 131, 14
1,151 is shown below.

Table 1 Binary Code Instruction Operation Summary 0000 NOP All peripherals ignore the strobe signal until the next instruction code is sent (each peripheral
03).

[0001] Peripherals not incorporated into the ID system configuration whose daisy chain inputs have a logic value of 1 send out the bit string in the ID register in units of 4-bit nibbles. This transmission is performed sequentially from the lower nibble at the strobe timing after this instruction.

0010 PC READ (PC) → A peripheral device whose upper bit of the bus program counter register matches the contents of the configuration register will read the data indicated by the contents of the program counter register after this instruction. Send at each strobe timing. Also, each strobe
After timing, all peripherals increment the contents of their program counter registers.
Note that a dummy strobe appears once immediately after issuing the command PC READ.

0011 DP READ (DP) → The peripheral device whose upper bit of the bus data pointer register matches the contents of the configuration register will read the data pointed to by the contents of the data pointer register after this instruction. At each strobe timing, and after each strobe timing, all peripherals increment their data pointer registers. In addition, the instruction DP
A dummy strobe appears once immediately after issuing READ.

0100 PC WRITE bus → (PC)
The peripheral device whose upper bit of the program counter register matches the contents of the configuration register loads data into the address pointed to by its own program counter register at the strobe timing after this instruction. do. Also, after each strobe timing, all peripherals increment their program counter registers.

0101 DP WRITE bus → (DP)
A peripheral device whose upper bit of the data pointer register matches the contents of the configuration register loads data into the address pointed to by its own data pointer register at the strobe timing after this instruction. do. Also, after each strobe timing, all peripherals increment their data pointer registers.

0110 LOAD PC bus→PC
At the strobe timing after this instruction, all peripheral devices sequentially load data into their own program counter registers starting from the lower nibble. Once all five nibbles have been transferred, the instruction code is automatically transferred to the PC.
It becomes READ (0010).

0111 LOAD DP bus → DP At the strobe timing after this instruction, all peripheral devices load data into their own data pointer registers sequentially starting from the lower nibble.
Once all five nibbles are loaded, the instruction code will automatically
It becomes READ (0011).

1000 CONFIGURE A peripheral device not included in the system configuration whose daisy chain input has a logical value of 1.
loads the five data nibbles following this instruction into its configuration register sequentially starting from the lowest nibble position.

1001 UNCONFIGURE A peripheral whose upper bit in the data pointer register matches the contents of its configuration register removes itself from the system configuration. This peripheral will no longer be
GONFIGURE, only responds to ID. Peripheral data pointer register is an instruction
Must be loaded immediately before UNCONFIGURE.

1010 POLL All peripherals requiring processing have one data line pulled high while the next strobe is low.

1011 (Reserved) 1100 BUSCC Peripherals whose upper bits in their data pointer registers match the contents of their configuration registers perform special operations defined for each peripheral.

1101 (Reserve) 1110 SHUTDOWN Each peripheral responds to this command based on its specific needs.

1111 RESET All peripherals perform a local reset. This may include, for example, resetting configuration registers in the case of replaceable peripherals.

〔Effect of the invention〕

As described above, according to the present invention, a flexible information processing device whose system configuration can be freely changed is provided.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a register configuration of a peripheral device in an embodiment of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIG. FIG. 4, a diagram showing lines, is a configuration diagram of a conventional information processing device. 101, 111, 121, 131, 141, 1
51: Peripheral device, 109, 119, 129, 13
9,149,159,202: bus, 201: central processing unit, 203, 204: daisy chain, 251: identification code register, 252: configuration register, 253: configuration flag, 254: data pointer register, 255: program·
Counter register, 256: instruction register.

Claims (1)

[Claims] 1. An information processing device comprising the following (A) to (D): (A) A first peripheral device connected to the CPU means: The first peripheral device is connected to the CPU means. a first plurality of memory locations serving as directly addressable memory for the first plurality of memory locations; (B) identification register means connected to said first peripheral device for storing data identifying a characteristic of said first peripheral device; Peripheral devices are as described above.
(C) providing data from said identification register means to said CPU means for causing said CPU means to identify an amount of memory locations in said first plurality of memory locations; (C) connected to said CPU means; Second Peripheral Device: Said second peripheral device comprises a second peripheral device which serves as a directly addressable memory for said CPU means.
a plurality of memory locations connected to the second plurality of memory locations and the second memory location connected to the second plurality of memory locations;
(D) second configuration register means for storing a bit serving as a high address of a memory location in a plurality of memory locations; (D) connected to said CPU means and said first and second peripheral devices; daisy chain means for enabling said CPU means to individually initialize first and second configuration register means; said second peripheral device is connected to a daisy chain output line of said first peripheral device; an input line, the daisy chain input line of the first peripheral device is connected to the CPU means, and the first peripheral device configures the first peripheral device in response to commands from the CPU means. and flag means for indicating that the first peripheral is incorporated into a daisy chain output line of the first peripheral based on the signal on the daisy chain input line of the first peripheral. including means for changing. 2 the high order address bits stored in the first configuration register means of the first peripheral device define a first address space and are stored in the second configuration register means of the second peripheral device; 2. The information processing apparatus according to claim 1, wherein said high-order address bits defined by said address space define a second address space different from said first address space. 3. The first peripheral device further comprises data pointer register means for storing a third address to which the CPU means requests access, and the first peripheral device stores the contents of the first configuration register means in the Claim 2, further comprising: comparing high order bits from a third address to determine whether the third address addresses memory within the first address space.
The information processing device described in the section.