JPS60238961A - Information processor - Google Patents

Abstract

PURPOSE:To obtain the information processor with flexible system constitution by providing an identification register which holds characteristics of each peripheral device in a bit pattern for every peripheral device. CONSTITUTION:Peripheral devices 101, 111, 121, and 131 which are replaceable are coupled with a daisy chain 203 or 204, and the dasisy chains 203 and 204 are driven by a CPU201. The daisy chains 203 and 204 are active at a logical value 1 and nonactive at a logical value 0. An identification code register (ID)251 (20 bits in this case) is stored with information for identifying characteristics of the peripheral device 101. The CPU201 reads the ID251 to check on functions (e.g. whether the peripheral device 101 is an input/output device mapped in a ROM, RAM, controller, or memory) and other pieces of information (e.g. memory capacity) regarding this peripheral device 101.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an information processing device that allows flexible configuration between peripheral devices and a central processing unit (hereinafter referred to as CPU).

[Prior art and its problems]

In a typical computer system, the configuration of various system components is fixed. In the static configuration method of the computing system according to the prior art, as shown in FIG.
, 53. and 54.

Each of the peripheral devices 51 to 54 includes, for example, a random access memory (RAM) or a read-only memory IJ (ROM).
), display devices, printers, communication control devices, and other devices other than storage devices may be used.

Peripheral devices 51 - 54 are coupled to CCPU 50 via bus 65 . Peripheral devices 51-54 are each assigned a fixed address. The CPU 50 can independently communicate with each of the peripheral devices 51 to 54 by using its fixed address once. Peripheral devices 51-54 are coupled to corresponding address comparison registers 61-64 and address selection circuits 71-74, respectively. When a CPO 50 or other device issues an instruction on bus 65, address comparison registers 61-64 and address selection circuits 71-74 check the instruction and each peripheral 51-54 receives the fixed address assigned to that peripheral. Allows responses only to commands that include an address.

Using static configuration schemes such as those described above inherently limits the flexibility of the system. for example.

Adding or removing equipment becomes difficult. This is because changing the physical configuration within a system requires that new devices be accessible, or that removed devices no longer exist. .

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned problems of the prior art and provide an information processing apparatus capable of flexible system configuration.

[Summary of the invention]

According to a preferred embodiment of the invention, a CPU and a
An information processing apparatus including a peripheral device dynamically configured by U is provided. Each peripheral device has a built-in identification code that identifies its characteristics. By reading this identification code, the CPU can determine the type of peripheral device (e.g., is the peripheral device ROM, RAM, control device, etc.) and other appropriate information related to the peripheral device (e.g., the memory of the storage device). size).

Each peripheral also has a configuration register. The number of bits in each configuration register is equal to or less than the number of bits used by the 1N information processor to address the entire address space. Each peripheral also has one called a configuration flag.
It has a bit register. The state of the configuration flags within a peripheral indicates that the peripheral
whether the configuration is controlled by U and therefore whether the contents of the configuration register are valid or not.

After characterizing the peripheral device through the identification code, the CPU uses this information to allocate address space to the peripheral device. The CPU then writes one or more bits to the configuration register and sets the peripheral's configuration flag to incorporate the peripheral into the system configuration. Similarly, the CPU removes a peripheral device from the system configuration by clearing the peripheral device's configuration flag. With this method, the CPU can dynamically change the system configuration of the information processing device.

As can be seen from the above explanation, the peripheral devices referred to in this application include not only input/output devices but also RAM.

It should be understood that it includes various devices such as ROM.

[Embodiments of the invention]

FIG. 2 shows a system configuration of an information processing apparatus according to an embodiment of the present invention. In FIG. 2, the CPU 201 has a series of peripheral devices 101,
1. Each peripheral device 101%llll, 121.
131, 141.151 are the corresponding no.
It is connected to 9.119°129.139, 149.159. ) Kusu 109°119.129.139.
149.159 are connected in parallel to a bus 202K, which is connected to the CPU 201 in parallel.

The CPU 201 uses the bus 109.119.129.139
．． Peripherals 101.149.159 on bus 202 coupled to ill.

Send commands and data to 121.131.141%151. The CPU 201 connects to the bus 109.119.129. which is connected to the bus 202 of the CPU 201.
139, 149, and 159, respectively, to peripheral devices 101.
111%t 21°131, 141.151 also receives data.

Bus 109.119.129.139.149.159
have the same configuration. FIG. 3 shows the configuration of the bus 109. Each bus includes a ground line 106, a power line 1
05, command line 104, strobe line 103
and several data lines 102.

In this embodiment, four data lines 102 are provided. The ground line 106 is 0. It is maintained at a constant voltage of Ov. Power line 105 is 0. It is held at a constant voltage of, for example, +4.5v, which is different from OV. The command line is typically driven by the CPU 201, but may also be driven by one or more peripheral devices 101. ill, 121%13],
141.151.

The strobe Φ line 103 is driven only by the CPU 201. The data line 102 is connected to the CPU 20
．． 1; or peripheral device 101. Ill, 121
%131.14L151. When these lines have the same voltage as the ground line 106, they have a logic value O, and when they have the same voltage as the power line 105, they have a logic value l. Strobe-line 103 is a logic 0
It is in an active state when the logic value is 1, and it is in an inactive state when the logic value is l. Command line 104 is active when the logic value is 0 and inactive when the logic value is l.

The information on the data line is data when the command line is active and is an instruction when the command line is inactive. In addition, the 19 reports on Data Line +02 are
It is effective immediately before and during the transition of the strobe line 103 from the active state to the erotic state.

In Figure 2, peripheral device lot, 111% 121.1
31 is a replaceable module. On the other hand, peripheral devices 141 and 151 are fixedly attached. Replacement port]
The capable peripheral devices 101.111.121%131 are each
It is coupled to a daisy chain 203 or 204. In this embodiment, the peripheral devices 101, Ill, 121 are CPU
It is coupled to a daisy chain 203 coming out from 201.

Peripheral device 131 is also coupled to daisy chain 204, which also originates from CPU 20t. The daisy chain 203 exits from the CPU 201, also enters the daisy chain input 107 to the peripheral device 101, and exits from the daisy chain output l18. Furthermore, the peripheral device 121 is input from the chain power 127, and the daisy chain output 12
Leave from 8. The daisy chain 203 ends here. On the other hand, the daisy chain 204 outputs from the CPU 201 , inputs the chain power 137 to the peripheral device 131 , and exits from the daisy chain output 138 . The daisy chain 204 ends here. Daisy chains 203 and 204 are driven by CPU 201. The daisy chains 203 and 204 are activated when the logic value is 1, and are inactivated when the logic value is O.

FIG. 1 shows the registers in the peripheral device 101. Identification code register ([D) 251 (here 20 bits)
contains information that identifies the characteristics of the peripheral device lot. By reading the ID 251, the CPU 201
Peripheral device 1010 functionality (e.g., whether this peripheral device 101 is a ROM, RAM, control device, or memory-mapped input/output device) and other information about this peripheral device 101 (e.g., memory capacity) can be examined. can. Only replaceable peripherals lot, 111, 121, and 131 require an ID. Fixedly attached peripheral device 14
1.151 does not require an ID.

The peripheral lot also has configuration registers 252. The configuration register 2520-bit length is the number of bits required for the CPU 201 to access the entire address space (hereinafter referred to as CPU address length).
The address length is 20 bits). for example,
Configuration register 252 may be 12 bits long. On the other hand, the peripheral device tti%121°131.141%151
may have more (or fewer) bits of configuration registers depending on the memory size each peripheral has.

The contents of the configuration register 252 are as follows:
01 is set for the peripheral device lO1.

The configuration flag 253 is a 1-bit long register, and the CP
Set when U201 assigns a memory address to peripheral device 101 (ie, when peripheral device 101 is incorporated into the system configuration). Also configuration flag 25
3 has been reset, whether the CPU 201 has not yet assigned a memory address to this peripheral device 101 or
or the address was previously unassigned (i.e.
It can be seen that the peripheral device 101 has been removed from the system configuration.

Peripheral device 101 is also provided with an instruction register 256 having a number of bits equal to the number of data lines 1020 (ie, 4 bits in this embodiment).

The function of instruction register 256 is to store the current instruction sent from CPU 201. Please refer to Table 1 for instructions. Peripheral device t t l.

121, 131, 141, and 151 also each have an instruction register.

The peripheral lot also includes a data pointer register (DP) 254 and a program counter register (P
C) 255 is also provided. D P 254 and P
Each C255 has a pit length that is the same as the CPU address length. Peripheral device 1111, 121.131.141.1
51 are also each provided with a DP. Furthermore, depending on the function, a PC may also be provided.

If the peripheral device 101 is not incorporated into the system configuration, CP[J201 can incorporate it into the system configuration as follows. CPU 201 specifies an address range for peripheral devices that has one or more addresses that are directly addressable by CPU 201 . To do this, CPU 201 first activates daisy chain power 107. Next, the CPU
201 is a ZD2 for reading the characteristics of the peripheral device 101.
Check 51. The CPU 201 executes the instruction C0NF'IGUR
E (i.e., the instruction C0NF”IGURE
). Subsequently, the configuration address (here 20 bits) is transferred to the peripheral device 101. The peripheral device 101 selects the top one of the received configuration addresses.
Copy 2 bits to configuration register 252. Furthermore, the configuration flag 253 is set to indicate that it has been incorporated into the system configuration.

The CPU 201 can also cancel the designation of the memory IJe address of the peripheral device 101 (that is, exclude it from the system configuration). To perform this operation, CP
[J201 issues the instruction LOAD DPC (see Table 1) to transfer the 20-bit address corresponding to the configuration address assigned to the peripheral device 201 over the data bus 201. Each peripheral device 1011111.121.13
1,141,151 takes this 20-bit address and places it in DP. The CPU 201 then executes the instruction UNC
Send ON F' I G (JRE (see Table 1). Each peripheral 101.111% 121.131.14
1°151 compares the contents of its own configuration register with the high-order bit of the corresponding number in the DP register.

In this case, the address stored in the DP register corresponds to the configuration address assigned to the peripheral device, so
Peripheral device 101 resets configuration flag 253.

The CP (J201) allows other peripheral devices to be added to or removed from the system configuration in the same way that peripheral device 101 is added to or removed from the system configuration.When incorporated into the system configuration, each peripheral device The CPU 201 can address each peripheral device tot, 111.121.131%141.151 individually.

When the peripheral device's configuration flag is reset, the peripheral device deactivates its daisy chain output. Therefore, if peripheral device 101 is not included in the system configuration, daisy chain output 108 is held inactive regardless of the value of daisy chain power 107. When a peripheral's configuration flag is set, that peripheral drives its daisy chain output to the same direct voltage as the daisy chain input. Therefore, when peripheral device 101 is included in the system configuration (ie, when configuration 7 lug 253 is set), its daisy chain output 108 is held at the same logic value as daisy chain output 107.

Once integrated into the system configuration, peripherals are used for various purposes. For example, when the instruction PCRFJAD is issued, the peripheral device 101 checks whether the CPU 201 is addressing a memory space within the peripheral device 101 by
The contents of the PC 255 and the configuration register 252 are compared. Similarly, upon receiving the instruction PCRREAD, each peripheral device i, i11.121.131.1411151,
To determine whether CPU 20t is addressing itself, the contents of the PC and the contents of the configuration register are compared.

Only peripheral devices addressed by CPU201 are addressed by CPU2.
It operates in response to the command issued by 01.

Each peripheral device 101.111.121.131%141.
151 PCs always contain the same value. That is, when the CPU 201 issues the command LOAD PC, each peripheral device 1 old, 111.121.131,
This is because 141° and 151 simultaneously load new values into their own PC. Similarly, each peripheral device tot, tt
t, 121, 131.141.151 to any DP, all the time.

Both have the same value.

The CPU 201 keeps the strobe line 103 inactive except during nibble transfer (transfer in units of 4 bits here, as seen from the number of data lines) through the data life 102. . During execution of a nibble transfer through data line 102, CPU 201 performs a strobe operation as described in Table 1 (ie, once strobe line 103 is activated and then deactivated).

The instruction code (i.e. binary code, see Table 1) is set to Peripheral 101,111%121.131.141.151
U2O5 is at instruction line 10 unless you are forwarding to
4 is held inactive. To send out the instruction code, the CPU 201 sets a logic value (ie, logic value 0 or l) corresponding to the instruction code (see Table 1) of each instruction on the data line 102-hi. The CPU 201 then activates the command line 104 and activates the strobe fist line 1.
A strobe operation is performed on 03 (that is, it is once activated and then deactivated). Each peripheral device
oi, III, 121.131, 141.151 copies the instruction code to an instruction register (eg, instruction register 256 of peripheral device 101) at the time strobe line 103 is deactivated by CPU 201. Each peripheral device lot, 111.121.131.1
The contents of the instruction register of 41.151 are interpreted by the peripheral in question, and this interpretation determines how each peripheral will respond to data subsequently sent on the data line. data line 1
It is determined whether or not to supply to 02.

Table 1 below lists the instructions and their binary codes and peripherals 101. ill, 121.131.141%151
A summary of the response behavior is shown below.

Table 1 Binary Code Instruction Operational Summary 0000 NOP All peripherals ignore strobe signals until the next instruction code is sent (each peripheral receives a strobe signal from strobe line 103).

0001 ID Peripheral devices not incorporated in the system configuration whose daisy chain input is set to 1 send out the bit string in the ID register in units of 4-bit nibbles. This transmission is performed sequentially from the lower nibble at the strobe timing after this instruction.

0010 PCREAD (PC) → Bus A peripheral device whose upper bit of the program counter register matches the contents of the configuration register will transfer the data pointed to by the contents of the program counter register to each strobe after this instruction. Send at the right time. Also, after each strobe timing, all peripherals increment the contents of their program counter registers. Immediately after the instruction PCR [2AD is issued, a dummy strobe appears once (0011 DPRID CDP) → bus The contents of the data pointer register of the peripheral device whose upper bit of the data pointer register matches the contents of the configuration register The data indicated by is sent at each strobe timer after this instruction. Also, after each strobe timing, all peripherals increment their data pointer registers. Note that a dummy strobe is seen immediately after the instruction DP RgAD is issued.

0100 PCWRITE bus → (PC) A peripheral device whose upper bit of the program e counter register matches the contents of the configuration register writes the strobe following this instruction to the address pointed to by its own program counter register. Load data at the right time. Also, after each strobe timer, all peripherals increment their program counter registers.

0101 DP WRITB bus → (DP) A peripheral device whose upper pit of the data pointer e register matches the contents of the configuration register writes the strobe following this instruction to the address indicated by its own data pointer register.・Load data with timing.

Also, each strobe timing After that, all peripherals are set to their own data pointer fist register Increment.

0110 LOAD PC bus→PC At strobe timing after this instruction, all peripherals load j-visual data from the lower nibble of their program counter register l\. When all five nibbles are transferred, the instruction code automatically becomes PCRREAD (0010).

0111 LOADDP bus→DP At the strobe timing after this instruction, all peripheral devices sequentially load data into their own data pointer registers starting from the lower nibble.

All 5 nibbles are loaded Then, the instruction code is automatically D. P RIE:AD(Ootx).

1000 C0NF'lGURg A peripheral device that is not included in the system configuration and whose daisy chain input is high will send the five data nibbles following this instruction to its own configuration register starting from the lower nibble position. Load sequentially.

1001 UNCON-E'IGURE Data Peripheral device whose upper bit of the register matches the contents of the configuration register removes itself from the system configuration. This peripheral will now only respond to the command GONFIGURg, ID. The peripheral's data pointer register must be loaded immediately before the instruction UNCONFIGURE.

rOto POLL All peripherals that require processing will pull one data line high while the next strobe is low.

+011 (Reserved) 1100 BUSCC A transport device whose upper bit of its data pointer register matches the contents of a configuration register performs special operations defined for each individual peripheral device.

rtot (reserve) 1110 SHU'rDOWN Each peripheral responds to this command based on its particular comfort level.

1111 RESET All peripherals are reset to local
Perform a reset. This may include, for example, resetting configuration registers in the case of replaceable peripherals.

〔Effect of the invention〕

As described above, according to the present invention, a flexible information processing device whose system configuration can be freely changed is provided.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a register configuration of a peripheral device in an embodiment of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIG. FIG. 4, a diagram showing lines, is a configuration diagram of a conventional information processing device. 101.111, 121, 131, 141, 151:
Peripheral devices, 109.119, 129, 139, 149,
159, 202: Bus, 201: Central processing unit, 203.204: Daisy chain, 251: Identification code register, 252: 111I configuration register, 253: Configuration flag, 254: Data e pointer, register, 255 Niprogram counter Φ register, 256: instruction register. Applicant: Yokozutsu Heuret Backard Co., Ltd. Agent: Patent Attorney Tsuguo Hasegawa

Claims (1)

[Scope of Claims] A central processing unit; and at least one peripheral device; an identification register for holding characteristics of each peripheral device in a bit pattern is provided for each peripheral device. Information processing device.