JPS6132128A - Key input device - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution by connecting any of a row or a column electrode to a common potential via an individual resistor respectively and giving sequentially repetitively to a prescribed potential to the other for scanning. CONSTITUTION:A switching element SW is arranged at the cross position among row electrodes L1-Ln and column electrodes P1-Pm. Input terminals KS1-KSn of the row electrodes L1-Ln are connected to a power supply terminal A and a common terminal B of a common power supply +Vcc via resistors r1-rn having the same characteristic. Output terminals KD1-KDm of the column electrodes P1-Pm are connected to an A/D converter 7 via lines D1-Dm and a pull-up resistor 8 connected in parallel with the power supply +Vcc via resistors R1-Rm having the same characteristic is connected to the lines D1-Dm. An analog signal from a key matrix circuit 6 is subjected to level up by the pull-up resistor 8 and given to the A/D converter 7 and an output of the A/D converter 7 is given to a processing circuit CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a key input device formed in a matrix by arranging switching elements at the intersections of a plurality of row electrodes and a plurality of column electrodes.

Background Art A typical prior art is shown in FIG. The key matrix circuit 1 includes a plurality of n row electrodes L1. L2..., Ln-1, L
n and a plurality of column electrodes P 1 , P 2 , -Pa+-1,
P+* are arranged to intersect with each other, and switching elements S are arranged at the intersections of row electrodes L1 to Ln and column electrodes P1 to P+++.
W are placed respectively. Each input terminal KSI, KS2 . , KSn-1, KSn are connected to the timing pulse generation circuit 2. Timing pulses are repeatedly generated from this timing pulse generating circuit 2 in a time-sequential manner and scanned to the row electrodes L1 to Ln. Each output terminal KDI, KD2 . of one column electrode Pi-Pm. −.

KDm-1, KDm are lines Di, D2.・、'D
It is connected to buffer 3 via a+-1 and Dm,
Also, the lines D1 to DI11 have resistors R1, R2...R.
m-1-Rm, respectively, to a pull-up resistor 4 connected in parallel to the power supply +Vcc.

For example, when the switching element SWI is pressed repeatedly, the timing pulse from the output terminal KD1 of the key matrix circuit 1 is raised in level by the pull-up resistor 4 and is applied to the buffer 3. The data output from the buffer 3 is given to a processing circuit CPU realized by a microcomputer or the like, and in this processing circuit CPU, the pressed switching element SW1 is identified and read.

Problems to be Solved by the Invention In the above prior art, the key matrix circuit 1 has n input terminals Ll, L2 . −． Ln-1, Ln, and m output terminals KDI, KD2 . ..., KDm-1°KDm, and the configuration of the key matrix circuit 1 becomes complicated.
Productivity will be lower.

Purpose An object of the present invention is to solve the above-mentioned technical problems and to provide a key input device that simplifies the electrical configuration of a key matrix circuit.

Means for Solving Problem α The present invention provides a key input device formed in a matrix by arranging switching elements at the intersections of a plurality of row electrodes and a plurality of column electrodes. Either one is connected to a common potential through individual resistors, and a predetermined potential is sequentially and repeatedly applied to the other of the row electrodes or column electrodes to scan or individually respond. This is a key input device characterized by applying a potential.

According to the invention, either the row electrode or the column electrode connects one to a common potential through individual resistors, and either the row electrode or the column electrode sequentially and repeatedly applies a predetermined potential to the other. The electrical configuration of the key input device is simplified by scanning the keys or applying corresponding potentials individually, thereby improving the productivity of the key input device.

Embodiment FIG. 1 shows an electric circuit of a key input device 5 according to an embodiment of the present invention. The key matrix circuit 6 has a plurality of n row electrodes L.
l, L2. −． Ln-1, Ln and plural column electrodes Pi,
P2. ..., P-1, P-1 are arranged to intersect,
At the intersections of the row electrodes L1-Ln and the column electrodes P1-Pm, switching elements are arranged, indicated by the general reference symbol SW. Each input terminal KSI, KS2 .
..., KSn-1, KSn are resistors r1, r2 . . . having the same characteristic value. ..., rn-1*rn are connected to the power supply terminal A of the common power supply Vcc and the ground side terminal B, respectively.

Each output terminal KDI, KD2° of column electrodes Pi-Pm=-,
K'Dt11-1, K Dm are lines Di, D2. −
.

It is connected to the A/D conversion circuit 7 via Dm-1, Dm, and the lines D1 to Dm are connected to the power supply via resistors R1, R2, -, Rn+-1, Rm, respectively, which have the same characteristic value. Pull-up resistor 8 connected in parallel to +Vcc
connected to. The analog signal from the key matrix circuit 6 is raised in level by the pull-up resistor 8 and is applied to the A/D conversion circuit 7. The digital signal A/D converted by the A/D conversion circuit 7 is given to a processing circuit CPU realized by a microcomputer or the like, and the switching element SW pressed and operated is identified and read in this processing circuit CPU. .

When none of the switching elements SW is pressed, the resistances rl, r2, . . . between the terminals A and B.

Each output terminal KSI, KS divided by rn-1+rn
The voltages of 2, -, K S n -1, and K S n have the values shown by the first equation.

V ksi= Electrician LX V ec −(1
) Here, Vksi represents the first voltage, and i is 1 to n.
represents any value of .

Next, assume that the position of the switching element SW1 disposed at the intersection of the row electrode L1 and the column electrode P1 is suppressed. Resistors R1 to Rm of pull-up resistor 8 connected in parallel to lines D1 to Dm of output terminals KDI to KDm
are each selected to be larger than the voltage dividing resistors r1 to rn, and the analog signal from the output terminal KDI is raised in level by this resistor R1 and input to the A/D conversion circuit 7. The A/D conversion circuit 7 has input terminals KYI, KY2 . ..., KYm-1
, KY+n. Said analog signal from line D1 is input to multiplexer 9 via input terminal KYI. An address signal generated from an address signal generation circuit 10 controlled by a processing circuit CPU is input to the multiplexer 9 via a latch circuit 11, and this latch circuit 11 is activated by an activation signal generated from an enable signal circuit 12. activated. The analog signals inputted to the multiplexer 9 are individually selected by address signals from the latch circuit 11, and A/D converted by the A/D converter 13.

After the digital signal from the A/D converter 13 is held in the data latch circuit 14, it is given to the processing circuit CPU via the data bus f. In this way, the processing circuit CPU
controls the address signal generation circuit 10 and the enable signal circuit 12, sequentially A/D converts the input voltages of the input terminals KYI to KYm, and by identifying the value, the pressed switching element SW is read.
In this way, the row electrodes L1 to Ln are connected to a voltage-divided common power source +
By connecting to Vcc, the input/output terminals of the key matrix circuit 6 are two terminals A.

There are B and m output terminals KDI to KDm, which can be reduced compared to the conventional M1n terminals, and the circuit configuration of the key input device 1 can be simplified.

FIG. 2 shows a key input device IA according to another embodiment of the present invention.
This is an electrical circuit. The configuration of this embodiment is similar to the configuration shown in FIG. 1, and corresponding parts are given the same reference numerals. Row electrode L
Each of the input terminals KS1 to KSn of 1 to Ln is connected to a timing pulse generation circuit 2o, and timing pulses are sequentially generated from the timing pulse generation circuit 2o and scanned. On the other hand, the column electrodes P1 to Pm have resistances R1,
They are connected to a common resistor R8 via R2, . Further, the branch line G1 is connected to the resistors R1 and R2, and the branch fin G1 is connected to the line G through the output terminal B.
Connected to 2.

Assume that the position of the switching element SW1 arranged at the intersection of the row electrode L1 and the column electrode P1 is suppressed. The timing pulses generated from the timing pulse generation circuit 20 are input to the input terminals KSI~ by the processing circuit CPU.
One of the input terminals KSn, for example, KSI, is set to O volts, and the remaining input terminals KS2 to KSn are set to high impedance and are controlled to be scanned time-sequentially. At this time, the voltage between the switching element SWI of the column electrode P1 and the resistor R1 becomes O volts, and the voltage vb of the output terminal B takes a value shown by the second equation.

This output voltage vb is applied to the A/D converter 2 via line G2.
1 is given. The digital signal A/D converted by the A/D converter 21 is given to the processing circuit CPU via the data latch circuit 22, and the processing circuit CPU identifies and reads the suppressed switching element SW.

In this way, the number of input/output terminals of the system circuit 23 is n input terminals KSI to KSn, power supply terminal A1, and output terminal B, which is smaller than the conventional n10m terminals.
This makes it possible to simplify the circuit configuration of the key matrix circuit IA.

The key input device according to the present invention is not limited to personal computers, word processors, etc., and can be implemented in other technical fields in the store range.

Effects As described above, according to the present invention, one of the row electrodes and the column electrode is connected to a common potential through individual resistors, and a predetermined voltage is connected to the other of the row electrode or the column electrode. The number of input terminals of row electrodes or the output terminals of column electrodes can be reduced by sequentially and repeatedly applying potentials for scanning or by individually applying corresponding potentials, thereby simplifying the circuit configuration. This significantly improves the productivity of the key input device.

[Brief explanation of the drawing]

FIG. 1 shows an electric circuit of a key input device 5 according to one embodiment of the present invention, FIG. 2 shows an electric circuit of a key input device IA according to another embodiment of the present invention, and FIG. 3 shows an electric circuit for explaining the prior art. It is an electrical circuit.

Claims (1)

[Claims] In a key input device formed in a matrix by arranging switching elements at intersections between a plurality of row electrodes and a plurality of column electrodes, either the row electrodes or the column electrodes is connected to an individual resistor. A key input characterized in that the key input is connected to a common potential through each of the row electrodes or the column electrodes, and is scanned by repeatedly applying a predetermined potential to the other of the row electrodes or the column electrodes, or individually applying a corresponding potential. Device.