SU1495846A1 - Graphic information display unit with gas-discharge indicator - Google Patents

Abstract

The invention relates to automation and computing and can be used in devices for displaying graphical information on the screen of a gas discharge matrix panel. The purpose of the invention is to increase speed. The goal is achieved by the fact that the device containing the memory block 8, the clock pulse generator 6, the counter 5, the decoder of columns 4, the keys of the first 2 and second 3 groups, the gas-discharge matrix indicator 1 and the first decoder of rows 10 are entered into the switch 7, the second decoder of lines 11, the elements AND the first 14, the second 12 and the third 13 groups, the elements OR the first 16 and the second 15 groups, the group of elements NOT 17, the isolation elements on the diodes 18, the keys of the third group 19 and the element NOT 9. The speed of the device increases by using a combinational circuit d imaging. 2 Il.

Description

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The invention relates to information display devices and is intended to reproduce graphic information in the form of envelope r or histogram on a gas discharge matrix indicator.

The purpose of the invention is to increase the speed.

FIG. a functional device schematic is presented; 2 is a schematic diagram of a key of a key block.

The device contains a gas-discharge matrix indicator 1, keys of the first 15 group 2, keys of the second group 3, a decoder of 4 columns, a counter 5, a generator of 6 clock pulses, a switch 7, a memory block 8, the HE element 9, the first 10 and the second 11 decrypt 20 row ratios, elements AND second 12, third 13 and first 14 groups, elements OR second 15 and first 16 groups, group of elements NOT 17, block 18 of the isolating elements on the diodes, block 19

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Each key of the third group of keys 19 contains a resistor 20, transistors 21-23, diodes 24 and 25, resistors 26-31. The base of the transistor 2 30 ppp-type is connected via a resistor 29 to the second control input, and through a resistor 28 to an emitter and a positive voltage source + inp, and the collector is connected via a resistor 30 35 to the base of the third transistor 23 p. p-p-type, connected through a resistor 20 to an emitter and a source of negative voltage. - Search, and its collector is connected to the cathode of diode 24 through a resistor 31 to a common bus connected to the cathode of diode 25, the anode of which is connected to the anode the diode 24 and with the emitter of the second transistor 22 pp-type, the collector of which is 45 through the resistor 26 is connected to the source of positive voltage + Unn2 and is the output of the key, and its base through the resistor 27 is connected to the first control, its input, VQ

The device works as follows.

In the Record mode, a signal is sent to the control inputs of the switch 7 and the memory block 8, which stores the code into the memory block 8, which is to be displayed at the address given to the input of the device. When using a gas discharge d5

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matrix indicator 1, containing horizontal horizontal buses, the code is written in the memory block as two tetrads of a binary-decimal code.

With the arrival of a pulse from the generator of 6 clock pulses, the counter 5 changes to the next state. In accordance with the code value at the output of counter 5, a signal appears at one output of the 4-column decoder. The next vertical bus of the gas-discharge matrix indicator 1 is connected to the common wire through the keys of the second group 3. If there is no signal, it goes through the switch 7 to the address inputs of the memory block 8, at the output of which the code to be displayed appears. The low bits of the code from the output of the memory block 8 are fed to the input of the first decoder of 10 lines, and the most significant bits to the input of the second decoder of 11 lines. When using a gas-discharge matrix indicator containing 100 horizontal electrodes, the first tetrad containing the lower digits of the code is fed to the input of the decoder 10, and the second tetrad containing the higher digits of the code to the input of the decoder 11. It is considered that, in accordance with the size of the code supplied, the number of outputs of the decoder 10 is equal to n, and the number of outputs of the decoder is 11 - t; In accordance with the code value at the output of the memory block 8, a logical O signal appears at one i-M output of the decoder 10, and at one j-th output of the decoder 11. At all the other outputs of the decoder 10 and. I1 present a logical 1 signal,

The formation of the image in the device is carried out either in the Envelope mode, when the gas-discharge matrix indicator 1 goes into the conducting state of the cell corresponding to the envelope of the graph, or in the Histogram mode, when the indicator 1 turns into the conducting state of the cell, corresponding to the envelope of the graph, and all located below the cells.

In the Envelope signal mode, the Envelope / histogram has a logical value of I. The signal at the output of the element 9 does not have the logical value of O. The first inputs of the keys of the first group 2 receive signals from the outputs of the decoder 10 from the high output directly, and from other outputs through the elements And the second groups 12 and elements OR of the second group 15. A logical signal 1 is present at all the outputs of the OR elements of the first group 16 connected to the first control inputs of the keys of the third group I9, since logic level 1 is applied to one of its inputs from the input envelope / histogram, logical signals 1 from the outputs of the elements OR 16 supplied through resistors 27 to the bases of transistors 22, these transistors (fig 1) of all keys of the third group 19 are open. For all. the second control key inputs of the third group 19 are open. All the second control inputs of the keys of the third group, except for one, are supplied with the logic level O from the outputs of the elements 17. The transistors 21 (Fig. 2) in the keys of the third group, to the bases of which through the resistor 29 the logic level O is applied, are opened and, respectively , transistors 23 are open. Therefore, the outputs of these switches (collectors of transistors 22) are transmitted through a collector-emitter junction of transistor 22, a diode 24 and a junction collector-emitter junction of transistor 23, which is supplied with a negative voltage Unnj.

In one key of the third group, in which logic level 1 is applied to the second control input, transistor 21 is closed and, accordingly, transistor 23 is closed. Therefore, a common bus level is applied to the emitter of transistor 22 of this key (diode level 25)

The transistors of those groups of keys 2, to the second inputs of which from the key of the third group 19, the UKne level is opened, regardless of the value of the signals at the first inputs coming from the outputs of the second group of 15 OR elements. The transistors of the keys of the first group 2, the inputs of which are supplied with a logic level 1 from the outputs of the elements OR 15 and a negative voltage from the outputs of the keys 19, are also open, but their degree of saturation is higher.

The transistors of that group of keys 2, to the second input of which, from the keys 19, the logical level O is applied, except for one, is open, since

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the base of the outputs of the elements OR 15 is supplied with the logic level 1. One transistor of this group, to the base of which the logic level O is applied, is closed, as the logic level O is applied to its emitter,

Thus, all transistors of keys 2, except one, are open. The voltage at the output of the keys 2 is equal to the half-voltage and is not enough to convert the cells of the gas discharge matrix indicator 1 to the conducting state. From the output of the key in which the transistor is closed, is applied to the horizontal bus of the gas discharge matrix indicator I Voltage, and the cell in the column, the vertical bus of which through the keys of the second group 3 is connected to the common bus, becomes conductive,

In the Histogram mode, the signal envelope / histogram at the device input has the value of logical O. The signal at the output of the element NOT 9 has the value of logical 1, In accordance with the value of the lower-order code bits, the signal of logical O appears at the output of the element 13

elements of the third group, arriving at the first input of the next element And, providing at its output the appearance of a logical O signal. Signal from the output; ode l3i - “- ro

the element is fed to the input of the 13 {.. 1st element, and at its output a logical O signal appears, and so on.

Thus, at the output of the i-ro element And the outputs of all the lower located elements And elements And 13, the signal is equal to logical O. The signal at the outputs of the block of elements And 13 located above the i-ro (according to the Scheme) has the value of logical 1. Signals on the outputs of the elements And 12 have a logical value of O, since at one outputs they come from the input envelope / histogram a signal of a logical O, At the first inputs of the groups

keys 2 receives signals from the output output of the decoder 10 and through the elements OR 15 from the outputs of the elements AND 13.

In accordance with the value of the starter

Our code bits appear with a logical O signal at the output of the AND 14j-i element | first group.

At the outputs of the elements And 14 below (according to the scheme) element

And, the signal has the value of logical O, and those located above (according to the scheme) - logical 1. Signals from the outputs of elements AND of the first group AND the signal from the senior output of the decoder 11 through the elements OR 16 go to the first control inputs of the key 19 , At the outputs j-1-x of the keys of the third group 19, to the first control inputs of which the logic level O is fed from the outputs of the elements OR 16, there is a positive voltage + VM, since the transistors 22 are closed (Fig. .2), In the jth key, the transistor 22 is open. From the output of the j-ro element HE 17, a logic level is applied. 1 to the second control input j-ro of the block 23, Therefore, the transistor 21 j-ro of the key is closed and, accordingly, the transistor 23 is closed. Therefore, at the output of the j-ro key, t, e, at the collector of transistor 22, the logic level. ,

Thus, regardless of the value of the signals at the first inputs, the transistors from the 1st to (j-l) group of keys of the first group 2 are closed, to which emitters positive voltage + Vcn from the outputs of the heated key block is applied: 23 ,. On the emitter | transistors of the jth group of keys of the cervical group 1, the logical level O is applied. Therefore, from the 1st to the i-th transistors of this group are closed, so icaK the logical level O is applied to their bases, and transistors with i + h-1-th through 1-th are open, since the logical level 1 is applied to their bases. The transistors of the j + 1-th and PG-th key groups are open, since negative emitters are supplied to their emitters from the outputs of the third group 19 keys. Unn4 C of the outputs of the keys of the first group, the transistors of which are closed, on the horizontal bus of the gas discharge matrix indicator 1, a voltage is applied to the yoke of the cells in the column, the vertical bus of which is connected to the common bus through the keys of the second group 3, and becomes conductive.

So, at zero value of the higher bits of the code entering the input of the decoder 1, the logical O signal is present at the youngest (its first output, and on all others - the logical I signal. At all outputs of the And 14 elements, the signal is equal to

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1 and, respectively, the first control inputs of the keys 19 are supplied through the elements OR 16, the logic level 1, Therefore, the transistors 22 (FIG. 2) of all the keys 19 are open. The second control inputs of all keys in the third group of keys 19, except the first 19i, from the outputs of the elements NOT 17 are supplied with a logical level of O. Therefore, at all outputs except the first, the keys of the third group 19 are UnUn. At the output of the first key 19i, the logic level O, the transistors of all groups except the first, the keys of the first group 2 are open. In the first group of keys, all transistors located above the i-ro are open, since the logical level 1 is applied to their base, and i- The transistors located below and below are closed, since the logic level O is applied to the base of them. Accordingly, i cells located in the lower part of the selected vertical column of the gas discharge matrix indicator 1, 1 will switch to the conducting state.

If the value of the higher bits of the code entering the input of the decoder 11 is such that a logical O signal is present at its second output, the logical O signal appears at the output of the AND 14 element and the first OR 16 element. Therefore, the transistor 22 (FIG. 22 ) the first key 19f is closed and the voltage at the output of this key is equal to the Transistors 22 of all the other keys 19 are open. To the second control inputs of all keys 19 from the outputs of the block of elements NOT 17, a logic level O is applied. Therefore, on all outputs of keys 19, except the first and second, the level is Uunl. The second control input of the second key from the element NOT 17 is given a logical 1 signal, so the output of this key is the logic level O, the transistors of the first group of keys 2 are closed, and the transistors of all other groups except the second are open. In the second group of keys, all transistors located at the i-ro top are open, and the i-th and lower transistors are closed. In accordance with this, ni cells located in the lower part of the selected vertical column of the gas-discharge matrix indicator 1 will go to the conducting state. .

Similarly, axis histogram is played at other values of the code received from memory block 8, and the connection of other vertical buses of the gas discharge matrix indicator 1.

Thus, in the proposed device, it is simplified by reducing the number of links with the horizontal tire control keys and the speed is improved by generating control signals with the help of combinational elements.

Claims (1)

1. A device for displaying graphic information on a gas discharge matrix indicator containing a memory block whose information and control inputs are COOT Respectively, the information input and input of the device record, the low-order bits of the memory block are connected to the inputs of the first row decoder, the keys of the first group, the outputs of which are connected to horizontal buses of the gas discharge matrix indicator, the vertical buses of which are connected to the outputs of the keys of the second group whose inputs are connected to the outputs of the column decoder, the input of which is connected to the output of the counter, the input of which is connected to the output of the clock pulse generator, which is indicated by the fact that, in order to increase the speed device actions, the second line decoder, diode isolation elements, keys of the third group, a group of elements NOT, two groups of elements OR, three groups of elements AND, the element NOT and a switch, whose control input is connected to the control input of the memory block, are entered into it. So, the first information input of the switch is the address input of the device, the second information input is connected to the output of the counter, and the output is connected to the address input of the memory unit, the outputs of the higher bits of which are connected to the input of the second. k, the outputs of a group of which are connected to the first inputs of elements AND of the first group, the second inputs of the subsequent with O 5 0 five 0 5 0 5 Q AND elements of the first group are connected to the outputs of the previous AND elements of the first group, except for the first AND element, the second input of which is connected to the first output of the second row decoder; the outputs of the AND elements of the first group are connected to the first inputs of the OR elements of the first group except the first OR element, the first input 6 is connected to the second output of the second row decoder, the second inputs of the OR elements of the first group are connected to the first inputs of the AND elements of the second group and with the input of the element are NOT and are the switching input of the display mode The device, the outputs of the SHS elements of the first group are connected to the corresponding first control inputs of the key block, except the first, the second control inputs of the key block are connected to the outputs of the elements NOT the groups whose inputs are connected respectively to the outputs of the second row decoder, the outputs of the first row decoder group connected to the second inputs of the elements And the torah and with the first inputs of the elements of the third group, the second inputs. the subsequent elements of the third group are connected to the outputs of the previous elements and the third group ppa, except the first element And, the second input of which is connected to the first output of the first row decoder, the third inputs of elements AND of the third group are connected to the output of the element NOT, the outputs of elements AND of the third group are connected to the first inputs of the elements OR of the second group whose second inputs are connected to the outputs of the elements of the second group, the code elements of the elements OR of the second group and the first output of the first row decoder are connected to the corresponding inputs of the first group of keys of the first group and to the cathodes of the diodes whose anodes are connected to the bus zero potential, the inputs of the second group of keys of the first group are connected to the outputs of the keys of the third group, the first and second information inputs of which are connected respectively to the positive and negative power buses, and the third information inputs of the keys of the third group are connected to the zero potential bus, the first control input The first key of the third group is connected to the positive power bus. 2, The apparatus of claim 1, wherein the three-key key of the three-key group includes three transistors, two diodes and seven resistors, one of the terminals of the first and second resistors are respectively the Lervo and the second control inputs the key and the other terminals are connected to the bases of the first and second transistors, respectively; the collector of the first SO2 transistor is the output of the key and is connected to one of the terminals of the third resistor, the other terminal of the second is the first information input of the key and is connected to the emitter fepoM second transistor and od him | i3 pins of the fourth resistor, the other pin of which is connected to the base of the second transistor, the collector of which is connected to one of the terminals of the fifth resistor, the other terminal of which is connected to the base of the third transistor and one of the terminals of the sixth resistor, the other terminal of which is connected to the emitter of the third transistor and the third transistor collector connected to one of the terminals of the seventh resistor and to the cathode of the first diode, the anode of which is connected to the emitter of the first transistor and to the anode of the second diode, the cathode of which is connected to another output of the seventh The resistor is the third key information input. Editor A. Shandor Compiled by E. Konyushenue Tehred L. Order 4272/49 Circulation 469 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5 t Fie.2 Proofreader M.Maksimishinets Subscription