JPH07225567A - Gradation driving circuit for active matrix liquid crystal display device and liquid crystal display device therefor - Google Patents

Abstract

PURPOSE:To provide a gradation driving circuit for an active matrix liquid crystal display device and liquid crystal display device therefor arranging two kinds or above of ramp voltages with gradation voltage values different from each other on the outside of a driver circuit, shortening the generation time of the ramp voltage, sufficiently securing the interval for holding data bus potential within the time when a scanning signal is in a conductive state and capable of surely writing the data bus potential in a liquid crystal cell. CONSTITUTION:After a pulse width modulation circuit 23 converts the gradation data to a pulse with a width according to the gradation data (n bits), inputs them to a decoder circuit 24, and after the decoder circuit 24 selects external gradation voltages Vref-1 to Vref-8 inputted to an output circuit 25 according to the gradation data (m bits) through analog switches 25-1 to 25-8, makes the analog switches 25-l to 25-8 an on state for the time of the output pulse width of the pulse width modulation circuit 23, and makes them a high impedance state at an off time, and the external gradation voltages Vref-1 to Vref-8 superimpose the ramp voltage to the pulse voltage, and set the pulse voltage and the ramp voltage to different voltage values.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a grayscale drive circuit and a liquid crystal display device for the grayscale drive circuit, which are capable of displaying a halftone of a liquid crystal display.

[0002]

2. Description of the Related Art Conventionally, there have been the following devices as this type of device. FIG. 9 is a gradation drive circuit diagram of a conventional active matrix type liquid crystal display device. As shown in FIG. 9, 1 is input with, for example, 8-bit grayscale data signals D ₀ , D ₁ , ..., D ₇ , a start signal ST which is a horizontal synchronizing signal, and a data shift clock CP 8. Bit × 60 shift register circuit, 2 receives the output of the shift register circuit 1, for example, 8 bits × 60
Of the shift register circuit 1 is stored in the latch circuit 2 by the LOAD signal.

The output of the latch circuit 2 is input to the pulse width modulation circuit 3. The pulse width modulation circuit 3 includes a pulse width control clock CPG and the LO signal as a reset signal.
The AD signal is input. The output of the pulse width modulation circuit 3 is level-converted by the level shifter circuit 4 and supplied to the analog switch 5 as an ON / OFF control signal. In addition, one of the analog switches 5 has a gradation reference voltage V
It was a driving method in which _ref was supplied and the output V _S was obtained from the other.

The gradation driving operation of the active matrix type liquid crystal display device will be described with reference to FIG. 10. First, when the horizontal synchronizing signal of the nth line is input to the shift register circuit 1 as the start signal ST, The grayscale data signals D _{0 to} D ₇ are sequentially transferred in the shift register circuit 1 by the data shift clock CP.

When the data transfer for 60 pixels is completed, a shift end pulse HO ₆₀ is outputted from the shift register circuit 1 and inputted as a start pulse to the gradation driving circuit (not shown) at the next stage. For example, when transferring 600 pieces of data, 600 ÷ 60 = 10 gradation driving circuits are connected in cascade. When the data transfer of the nth line is completed as described above, LOAD
The signal causes the data of the nth line to be stored in the latch circuit 2. Next, when the horizontal synchronizing signal on the (n + 1) th line is input to the shift register circuit 1 as the start signal ST, the gradation data signal on the (n + 1) th line is sequentially transferred in the shift register circuit 1, and so on. Repeat the operation.

In FIG. 11, gradation display data D ₀ ,
, D ₇ are stored in the latch circuit 2 by the LOAD signal, the stored data are input to the coincidence circuit 3-2 from the outputs Q ₀ , ..., Q _{7 of the} latch circuit 2. At the same time, the LOAD signal is input to the RST of the clock number counter 3-1 forming the pulse width modulation circuit 3, and the clock number counter 3-1 is reset. Further, the flip-flop 3-3 forming the pulse width modulation circuit 3 is set.

The clock number counter 3-1 counts the number of pulse width control clocks CPG and outputs g ₀ , ..., G.
₇ , the data of outputs Q ₀ , ..., Q ₇ of the latch circuit 2 and the data of outputs g ₀ , ..., G ₇ of the clock counter 3-1 are paired with the data of Q _m and g _m. So (m
= 0, ..., 7) The signal obtained by inputting to the EX / NOR circuit and the pulse width control clock CPG are input to the AND circuit to obtain the coincidence circuit output. The output obtained by the coincidence circuit 3-2 is input to the reset terminal of the flip-flop 3-3, and the output of the flip-flop 3-3 is reset.

As described above, the pulse width modulation circuit output P _O having the pulse width corresponding to the gradation data is obtained. For example, n
When the grayscale data of the -1st line is 00 in hexadecimal (0 in decimal), the pulse width modulation circuit output P _O becomes a signal which rises at the LOAD signal and falls at the first CPG clock. Also, the gradation data is hexadecimal FF (10
When the number is a decimal number 255), it falls by the LOAD signal and 2
The P _O output falls at the 56th CPG clock.

The output P _O is level-converted through the level shifter circuit 4 and then supplied to the analog switch 5 to control ON / OFF of the analog switch 5. One of the analog switches 5 has a gradation reference voltage V
_ref is supplied. The V _ref is a signal having, for example, a ramp-shaped voltage waveform having a horizontal synchronizing signal period. Then,
The output V _S of the analog switch 5 has the same voltage as the reference voltage V _ref only while the output P _O is “H”, and is in the high impedance state while the output P _O is “L”.

For example, when the gradation data is 00 as in the (n-1) th line, the output V _S gradually rises from V ₀ ,
After becoming V ₁ , it is in a high impedance state, and when the gradation data is FF as in the nth line, the output V _s gradually rises from V ₀ and becomes V ₂ and then becomes high impedance. It becomes the signal that becomes the state. By the way, the active matrix type liquid crystal display device has a circuit configuration shown in FIG.

In the figure, 6 is a data signal circuit,
It is composed of the gradation driving circuit described above. Reference numeral 7 is a scan signal circuit, 8 is a data bus line connected to the output of the data signal circuit 6, 9 is a scan bus line connected to the output of the scan signal circuit 7, and 10 is a data bus line 8 and a scan bus line 9. For example, an a-Si thin film transistor (hereinafter referred to as a TFT) 11, 11 is a liquid crystal cell connected to the TFT 10 at the intersection of the liquid crystal cell 1 and the liquid crystal cell 1.
The other one is connected to the counter electrode 13 and electrically serves as a capacitor of, for example, about 0.1 (pF). 12
Is a storage capacitor provided in parallel with the capacitor composed of the liquid crystal cell 11, and is, for example, a 0.5 (pF) capacitor.

The data bus line 8 is arranged to face the counter electrode 13 via the liquid crystal, forms a capacitor 14, and the capacitor 15 is formed by the parasitic capacitance between the data bus line 8 and the scan bus line 9. Is formed. In the case of a liquid crystal display device having a diagonal of 10 inches, the capacitor of the data bus line 8 is, for example, about 10 (pF). The sampling time (CPG clock cycle) of the ramp-shaped voltage waveform is substantially determined by the time constant τ = CR consisting of the capacitance C of the data bus line and the ON resistance R of the analog switch. The current CPG cycle is 100 ns.

When the output V _s of the analog switch 5 in FIG. 10 is supplied to the data bus line 8 in FIG. 12, the potential of the data bus line 8 is in the period during which the output V _s of the analog switch 5 is fixed. Is at the same potential as V _S. At this time, the capacitor 14 is charged according to the output V _s . When the output V _s is in a high impedance state, it has a potential determined by the charged capacitor 14. That is, it is held at the potential immediately before the high impedance state. For example, in the case of the (n-1) th line in FIG. 10, the potential V ₂ is held during the high impedance period.

Therefore, during the _VS output period of the (n-1) th line, the scanning signal VG _n-1 makes the TFT 10 conductive via the scanning bus line 9, and finally the potential V ₁ holds the data bus potential. In the output period of the nth line, the scanning signal VG _n makes the TFT 10 conductive, and finally the potential V ₂ holds the data bus potential during the time T _HD1. Time T
_Applied during _HD2 .

[0015]

However, in the device having the above structure, when the data bus potential becomes high, the period T _HDn during which the scan signal is held in the conductive state of the scan signal becomes short. In the current TFT, in order to accurately write the potential of the data bus to the liquid crystal cell,
A data bus potential holding time of about 25 μs is required. In the current circuit configuration, when the scanning time is set to 40 μs, the time required to sample the ramp waveform in 256 gradations is 25.6 μs [256 steps × 100 ns (CPG cycle)], which is sufficient. There is a problem that the data bus potential holding time cannot be secured.

According to the present invention, in order to eliminate the above-mentioned problem that the holding time of the data bus voltage cannot be sufficiently secured, two or more kinds of ramp voltages having different gradation voltage values are arranged outside the driver circuit. A floor of an active matrix type liquid crystal display device that shortens the lamp voltage generation time, secures a sufficient period for holding the data bus potential within the time when the scan signal is in the conductive state, and can accurately write the data bus potential in the liquid crystal cell. An object of the present invention is to provide a gradation drive circuit and a liquid crystal display device thereof.

[0017]

According to the present invention, in order to achieve the above object, each display pixel in a grayscale drive circuit of an active matrix type liquid crystal display device has a 2 ^K level (K is an integer of 2 or more). In a grayscale drive circuit of an active matrix type liquid crystal display device that performs grayscale display, a shift register circuit that sequentially transfers K-bit grayscale data, a latch circuit that stores the contents of this shift register circuit, and this latch circuit Of the stored grayscale data, the lower n bits are input to the pulse width modulation circuit, and among the grayscale data stored in the latch circuit, the upper m bits are input and the pulse width modulation circuit a decoding circuit output signal is input, is connected to the decoding circuit, 2 ^m of different 2 ^m pieces of analog switches and the gradation voltage value for one output A power supply is arranged externally, an external gray scale voltage is connected to one end of the analog switch, and the other end side of the analog switch is provided with an output circuit commonly connected, and the pulse width modulation circuit includes gray scale data (n Bit) and input to the decoding circuit, and the decoding circuit outputs the external grayscale voltage input to the output circuit to the analog switch according to grayscale data (m bits). After selecting via the pulse width modulation circuit, the analog switch is turned on for a time corresponding to the output pulse width of the pulse width modulation circuit, and is set to a high impedance state when the pulse width is turned off. The lamp voltage is set to different voltage values.

Further, there is obtained a liquid crystal display device comprising the gradation drive circuit of the active matrix type liquid crystal display device according to claim 1 and a liquid crystal panel driven by the gradation drive circuit.

[0019]

According to the present invention, as described above, two or more kinds of lamp voltages having different gradation voltage values are input from the outside, and the same number of analog switches as the lamp voltages are arranged in the gradation driving circuit. The ramp voltage is input to one end of the analog switch, the other end of the analog switch is made common, and one kind of ramp voltage is selected from a plurality of ramp voltage groups via the decoding circuit for the higher order data of the gradation data. The selected analog switch turns on the analog switch for the pulse width time generated by the lower data, and outputs the ramp voltage to the gradation drive circuit.

Therefore, each display pixel is set to 2 ^K level (K
Is an integer greater than or equal to 2) in the gradation drive circuit of the active matrix type liquid crystal display device for displaying gradation,
Since eight kinds of lamp voltages having different gradation voltage values can be input and the step time of the lamp voltage can be set to 32 steps, the generation period of the lamp voltage can be shortened to ⅛ of the conventional one.

As for the gradation level, it is possible to achieve 256 gradation levels by selecting eight kinds of ramp voltages by the logical product of the decode circuit and the pulse width control circuit. Furthermore,
Since the generation time of the lamp voltage can be shortened to 1/8 of the conventional one, the data bus voltage holding time within one scanning time can be sufficiently secured, and even in the current TFT, the potential of the data bus is set to the liquid crystal cell. Can be written accurately, and the display quality can be improved.

[0022]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a drive circuit diagram of an active matrix type liquid crystal display device showing an embodiment of the present invention. As shown in this figure, 21 receives, for example, 8-bit grayscale data signals D ₀ , D ₁ , ..., D ₇ , a start signal ST which is a horizontal synchronizing signal, and a data shift clock CP. For example, one circuit (SR-1) is a shift register circuit composed of 8 bits × 192 circuits, 22 is an input of the output of the shift register circuit 21, for example, one circuit (L-1) is 8 bits from the 192 circuits. Is a latch circuit which is stored by the LOAD signal.

The outputs (D _{0 to} D ₇ ) of the latch circuit 22 are
For example, the upper 3 bits (D _{5 to} D ₇ ) are the decoding circuit (D
EC-1) 24, lower 5 bits (D _{0 to} D ₄ )
Is input to the pulse width modulation circuit (PWM-1) 23.
The output (PWM) of the pulse width modulation circuit 23 is input to the decoding circuit 24. After selecting the analog switch group (25-1 to 25-8) in the output circuit 25, the decoding circuit 24 controls ON / OFF of the selected analog switch.

The output circuit 25 is composed of an analog switch group, and for example, eight analog switches are connected to one output. At one end of the analog switch group, for example, eight kinds of lamp voltages having different gradation voltage values (the gradation voltage V _ref-1 is connected to the analog switch 25-1, and the gradation voltage V _ref-8 is the analog switch 25). -8) is supplied, and outputs V _{O-1 to} V _O-192 are obtained from the other end side to which analog switches can be commonly connected.

Next, the operation of the gradation drive circuit of this active matrix type liquid crystal display device will be described with reference to FIG.
First, when the horizontal synchronizing signal of the nth line is input to the shift register circuit 21 as the start signal ST, the grayscale data signals D _{0 to} D ₇ of the nth line are stored in the shift register by the data shift clock CP. Are sequentially transferred. When the data transfer for 192 pixels is completed, the shift end pulse HO is output from the shift register circuit 21 and input as a start pulse to the gradation drive circuit (not shown) in the next stage.

Grayscale driving circuits are similarly cascaded according to the number of data to be transferred. As described above,
When the data transfer on the nth line is completed, the gradation data D _{0 to} D _{7 on} the nth line is stored in the latch circuit 22 by the LOAD signal. Next, as the start signal ST, n +
When the horizontal synchronizing signal of the first line is input to the shift register circuit 21, the gradation data signal of the (n + 1) th line is sequentially transferred in the shift register circuit 21, and the same operation is repeated thereafter.

FIG. 3 shows the pulse width modulation circuit 23. When the lower 5 bits (D _{0 to} D ₄ ) of the grayscale data are stored in the latch circuit 22 by the LOAD signal, the stored data is output from the latch circuit 22 (Q1 to Q5) and the match circuit 23 -2 is input. At the same time, the LOAD signal
Clock counter 2 constituting the pulse width modulation circuit 23
3-1 is input to the RST, and its clock number counter 2
3-1 is reset. In addition, the pulse width modulation circuit 23
Set input S of the flip-flop 23-3 that constitutes the
Is also input with the LOAD signal, and the flip-flop 23-3 is set.

The clock number counter 23-1 counts the pulse width control clock CPG and outputs it (G1 to G5).
Is input to the matching circuit 23-2. The matching circuit 2
3-2 sets the data of the outputs Q1 to Q5 of the latch circuit 22 and the data of the outputs G1 to G5 of the clock counter 23-1 so that the data of Q _m and G _m are paired (m =
1 to 5) AN which is obtained by inputting to an EX.NOR (exclusive NOR) circuit and a pulse width control clock CPG
Input to D circuit and obtain coincidence circuit output.

The output obtained by the coincidence circuit 23-2 is input to the reset R of the flip-flop 23-3, the flip-flop 23-3 is reset, and the pulse width modulation circuit output from the flip-flop 23-3. PMW is output. As described above, the pulse width (PWM) corresponding to the lower 5 bits of the gradation data is obtained.

For example, in FIG. 2, the grayscale data in the latch circuit 22 on the n-th line is 2FH in hexadecimal (0 in binary).
010111), the data input to the pulse width modulation circuit 23 is 0F (binary number 01111) in the lower 5 bits of 16H, and the data input to the decoding circuit 24 is 1H in the upper 3 bits of hexadecimal. (00 in binary
1) is input.

The pulse width control clock number CPG is determined by the number of bits (5 bits) of the gradation data input to the pulse width modulation circuit, and 32 clocks are input. The output (PWM) of the pulse width modulation circuit 23 on the n-th line rises at the LOAD signal, and gradation data (gradation data in hexadecimal notation:
00H is 1 clock, 01H is 2 clocks, 0FH is 1 clock
6 clocks, 1FH is 32 clocks), and the decoding circuit 2 is reset by a coincidence signal of the number of control clocks.
4 is input.

The decoding circuit 24 is, for example, as shown in FIG.
As shown in, the upper 3 bits (D ₅ ,
D _6, the D ₇₎ are decoded by the decoder 24-1, eight decoded signals (Q1 to Q8: signals selected to generate a set only one high level). The eight kinds of decode signals are AND signals with the pulse width modulation circuit output (PWM) to turn on / off the analog switch in the output circuit 25.
OFF control (V _ref-n selection signal) is performed.

The [0033] decode signal, the connected gray scale voltage at one end of the analog switches _{(V re f-1 ~V ref} -8) 1 one selected pulse width time (PWM) analog switch in the ON state . After turning off, it goes into a high impedance state. For example, from the relationship between the gradation data and the gradation voltage shown in FIG. 5, eight kinds of gradation voltages are selected according to the state of the upper 3 bits. For example, in case of 0H (binary number: 000), V
Select _ref-1 . In the case of 7H (binary number: 111), V _ref-8 is selected.

FIG. 6 shows the gradation voltage drive waveform, and FIG. 7 shows the liquid crystal drive voltage vs. transmittance (VT) characteristic. The gradation voltage drive waveform is composed of a ramp voltage period and a holding voltage period within one scanning period. The gradation voltage is generated by sampling the ramp voltage period for an arbitrary time. The number of samplings is determined by the number of pulse width control clocks, and is 32 pulses in this embodiment.

The driving range of the gradation voltages (V _{ref-1 to} V _ref-8 ) is, for example, V _ref-1 is V when V _ref-1 is V from the relationship of liquid crystal driving voltage vs. transmittance (VT characteristic) shown in FIG. Corresponding to the period of _{1 to} V ₂ , the voltage level of 1 to 32 gradations is generated as the number of gradations. V _ref-2 corresponds to the V _{2 to} V ₃ period, and generates a voltage level of 33 to 64 gradations. Similarly, V _ref-8 of the eighth power source corresponds to the period of V _{8 to} V ₉ , and the number of gradations is 22.
Voltage levels of 5 to 256 gradations are generated.

FIG. 8 shows a circuit configuration of an active matrix type liquid crystal display device. Reference numeral 30 is a liquid crystal display device composed of a liquid crystal panel, and 31 is a data signal circuit, which is constituted by the gradation drive circuit of the present invention. The other part is similar to the conventional circuit. That is, 32 is a scanning signal circuit, 33 is a data bus line connected to the output of the data signal circuit 31, 34 is a scanning bus line connected to the output of the scanning signal circuit 32, and 35 is a data bus line 33 and a scanning bus line. For example, an a-Si thin film transistor (hereinafter referred to as a TFT) 36 provided at an intersection with 34 is a liquid crystal cell whose one side is connected to the TFT 35.
The other is connected to the counter electrode 38 and electrically serves as a capacitor of, for example, about 0.1 pF. Reference numeral 37 denotes a storage capacitor provided in parallel with the capacitor formed of the liquid crystal cell 36, which is, for example, a 0.5 pF capacitor.

Further, the data bus line 33 is arranged so as to face the counter electrode 38 via the liquid crystal, forms a capacitor 39, and the capacitor 40 is formed by the parasitic capacitance between the data bus line 33 and the scan bus line 34. Is formed. In the case of a liquid crystal display device having a diagonal of 10 inches, the capacitor of the data bus line 33 is, for example, about 10 pF.

Next, the gradation driving operation of the liquid crystal display of the present invention will be described with reference to FIG. Here, a gradation driving method will be described based on the gradation data of the nth line. n
The grayscale data of the line is processed within the scanning time of the (n + 1) th line. First, the decoding circuit 2 of the (n + 1) th line
The gradation voltage V _ref-2 is selected based on the data 1H (hexadecimal system) in four. When the output (PWM) of the pulse width modulation circuit 23 is in the high state, the selection time (ON time) of V _ref-2 is
The analog switch is turned on, the gradation voltage of V _ref-2 starts charging the capacitors 39 and 40 of the data bus line 33 in the liquid crystal display device through the analog switch, and the output of the pulse width modulation circuit 23 ( When PWM) becomes low, the analog switch is turned off and the output V _{0 of the} analog switch becomes high impedance. When the output V ₀ is in the high impedance state, the potential V 48 is determined by the charged capacitors 39 and 40.

That is, the potential is held immediately before the high impedance state. For example, since the grayscale data of the nth line is 02H (hexadecimal number), it is held at the potential V3 during the high impedance period. Similar n
Since the grayscale data of the + 2nd line is FFH (hexadecimal number), it is held at the potential V256 during the high impedance period.

The gradation drive voltage is AC-driven (not shown) at a drive cycle (frame-by-frame, scan-by-scan) as a means for preventing deterioration of the liquid crystal cell 36. Therefore, the data bus potential V48 of the (n + 1) th line causes the scanning signal VG _{n-2 to} make the TFT 35 conductive via the scanning bus line 34, and finally the voltage V48 is applied to the liquid crystal cell 36 and the storage capacitor 37. .

Further, the data bus potential holding period THD- _n
Up to THD- _{n + 2} is determined by the ramp voltage period for generating the gradation drive voltage and the scanning time. The ramp voltage generation period is determined by the number of gradation control clocks and the time of one clock, and in this embodiment, 32 clocks × 100 ns = 3.2 μs is required. When the scanning time is set to 40 μs, the data hold period is 36.8 μs, which is a sufficient holding time.

As described above, for example, eight kinds of ramp voltages having different gradation voltage values can be input and the step time of the ramp voltage can be set to 32 steps. It can be shortened to 1/8. In addition, for the gradation level, eight kinds of lamp voltages are selected by the logical product of the decode circuit and the pulse width control circuit,
256 gray levels can be achieved.

Further, the lamp voltage generation period is set to 1
Since it can be shortened to / 8, the holding time of the data bus voltage within one scanning time can be sufficiently secured, and even in the current TFT, the potential of the data bus can be accurately written in the liquid crystal cell, The display quality can be improved. In addition, the scanning time is shortened (from 40μs to 30μ
s), a sufficient data holding time can be secured.

The present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0045]

As described in detail above, according to the present invention, the following effects can be achieved. In a gradation drive circuit of an active matrix type liquid crystal display device which performs gradation display of each display pixel at a 2 ^K level (K is an integer of 2 or more), two kinds of lamp voltages having different gradation voltage values are provided outside the driver circuit. With the above arrangement, the generation time of the lamp voltage can be shortened, a sufficient period for holding the data bus potential within the time period during which the scanning signal is in the conductive state can be secured, and the data bus potential can be accurately written to the liquid crystal cell. .

As the gradation level, for example, eight kinds of ramp voltages can be selected by the logical product of the decode circuit and the pulse width control circuit to achieve 256 gradation levels. Further, since the generation time of the ramp voltage can be shortened to 1/8 of that of the conventional one, it is possible to sufficiently secure the holding time of the data bus voltage within one scanning time, and even in the current TFT, the potential of the data bus can be reduced. The liquid crystal cell can be accurately written, and the display quality of the liquid crystal display device can be improved.

[Brief description of drawings]

FIG. 1 is a drive circuit diagram of an active matrix liquid crystal display device showing an embodiment of the present invention.

FIG. 2 is a gradation driving operation timing chart of the active matrix type liquid crystal display device showing the embodiment of the present invention.

FIG. 3 is a pulse width modulation circuit diagram in a gradation drive circuit of an active matrix liquid crystal display device showing an embodiment of the present invention.

FIG. 4 is a decoding circuit diagram in a gradation drive circuit of an active matrix type liquid crystal display device showing an embodiment of the present invention.

FIG. 5 is a diagram showing a relationship between gradation data and gradation voltage in a gradation driving circuit of an active matrix type liquid crystal display device showing an embodiment of the present invention.

FIG. 6 is a gradation voltage drive waveform chart in the gradation drive circuit of the active matrix type liquid crystal display device showing the embodiment of the present invention.

FIG. 7 is a diagram showing a relationship between liquid crystal drive voltage and transmittance of an active matrix type liquid crystal display device showing an example of the present invention.

FIG. 8 is a circuit configuration diagram of an active matrix type liquid crystal display device showing an embodiment of the present invention.

FIG. 9 is a gradation drive circuit diagram of a conventional active matrix type liquid crystal display device.

FIG. 10 is a timing chart of a grayscale driving operation of a conventional active matrix type liquid crystal display device.

FIG. 11 is a pulse width modulation circuit diagram in a grayscale drive circuit of a conventional active matrix liquid crystal display device.

FIG. 12 is a circuit configuration diagram of a conventional active matrix type liquid crystal display device.

[Explanation of symbols]

21 shift register circuit 22 latch circuit 23 pulse width modulation circuit 23-1 clock number counter 23-2 coincidence circuit 23-3 flip-flop 24 decoding circuit 25 output circuit 25-1 to 25-8 analog switch 30 liquid crystal display device 31 data Signal circuit 32 Scanning signal circuit 33 Data bus line 34 Scanning bus line 35 a-Si thin film transistor (TFT) 36 Liquid crystal cell 37 Storage capacitor 38 Counter electrode 39, 40 Capacitor D _{0 to} D ₇ Gray line data signal CP data of the nth line Shift clock ST start signal LOAD LOAD signal CPG pulse width control clock PMW pulse width modulation circuit output V _{O-1 to} V _O-192 output V _{ref-1 to} V _ref-8 gradation voltage

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Hiroshi Furuya 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (2)

[Claims] 1. A gradation drive circuit of an active matrix type liquid crystal display device for performing gradation display of each display pixel at a 2 ^K level (K is an integer of 2 or more). A shift register circuit for transferring, (b)
A latch circuit for storing the contents of the shift register circuit,
(C) A pulse width modulation circuit to which the lower n bits of the grayscale data stored in the latch circuit are input, and (d) an upper m bits of the grayscale data stored to the latch circuit are input. And a decoding circuit to which the output signal of the pulse width modulation circuit is input, and (e) 2 ^m analog switches for one output, which are connected to the decoding circuit, and have different gradation voltage values. An output circuit is provided in which a 2 ^m type power source is arranged outside, an external grayscale voltage is connected to one end of the analog switch, and the other end side of the analog switch is commonly connected. (F) The pulse width modulation circuit After being converted into a pulse having a width corresponding to gradation data (n bits), it is input to the decoding circuit, and the decoding circuit outputs gradation data (m
The external grayscale voltage input to the output circuit is selected via the analog switch according to the bit), and then the analog switch is turned on for the time of the output pulse width of the pulse width modulation circuit, and is turned off. A gradation drive circuit of an active matrix type liquid crystal display device, which is in a high impedance state, a ramp voltage is superimposed on a pulse voltage as an external gradation voltage, and the pulse voltage and the lamp voltage are set to different voltage values. 2. A liquid crystal display device comprising the grayscale drive circuit of the active matrix type liquid crystal display device according to claim 1, and a liquid crystal panel driven by the grayscale drive circuit.