JP2811015B2 - Serial / parallel AD converter - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a serial-parallel AD converter for converting an analog signal into a digital signal.

2. Prior Art FIG. 2 shows a configuration of a conventional serial-parallel AD converter. Second
In the figure, 1 is an input voltage, 2A and 2B are reference voltages, 3
Is the main reference voltage train, 4 is the main comparator train, 5 is the main logic circuit, 6
Is a sub-reference resistor row, 7 is a sub-reference voltage row, 8 is a sub-comparator row, 9 is a sub-logic circuit, and 10 is a switch row.

By connecting a plurality of sub-reference resistor strings 6 in series and dividing the two reference voltages 2A and 2B by resistance, the main reference voltage string 3
Is created. The sub-reference voltage sequence 7 is created by dividing the two adjacent main reference voltages of the main reference voltage sequence 3 by the resistors Rs constituting the sub-reference resistor sequence 6. The main comparator row 4 compares the main reference voltage row 3 with the input voltage 1, respectively. The main logic circuit 5 receives the output of the main comparator row 4 as an input, and the input voltage 1 is any of the main reference voltage rows 3. Determine if it is between the two main reference voltages. Thus, the input voltage 1 is roughly AD-converted. Subsequently, the switch array 10 selects and outputs a sub-reference voltage that divides between the two main reference voltages determined by the main logic circuit 5. The sub-comparator row 8 compares the output of the switch row 10 with the input voltage 1, and the sub-logic circuit 9 receives the output of the sub-comparator row 8 as an input, and the input voltage 1 is any one of the sub-reference voltage rows 7. Determine if it is between the two sub-reference voltages. This allows
The input voltage 1 is finely AD-converted.

In the serial-parallel AD converter shown in FIG. 2, when each switch S in the switch array 10 is turned on, a charge is injected from each switch S into the sub-reference resistor array 6 and the main reference voltage array 3 Fluctuated, and the AD conversion could not be performed correctly.

Therefore, in order to prevent this, the resistance value of each resistor Rs constituting the sub-reference resistor array 6 is reduced, and the change due to charge injection is reduced by flowing a large amount of current. In this case, Since the area of each resistor Rs constituting the sub-reference resistor array 6 increases, there is a problem that the area of the entire AD converter also increases.

FIG. 3 shows an example of another conventional serial / parallel AD converter devised to solve the above-mentioned problem. In this series-parallel AD converter, the reference voltages 2A and 2B and the main reference voltage train 3 are connected by a main reference resistor train 11. By reducing the resistance value of each resistor Rm constituting the main reference resistor array 11 and increasing the flowing current, when each switch S in the switch array 10 is turned on, the electric charge is reduced to each switch Sm.
From the main reference voltage train 3
In addition, fluctuations in the voltage of the sub-reference voltage train 7 can be reduced. Further, in this case, the resistance value of each resistor Rs constituting the sub-reference resistor row 6 does not need to be too small, and consequently the area of the entire AD converter is reduced as shown in FIG. Smaller than.

However, when the serial / parallel AD converter shown in FIG. 3 is arranged on a substrate, one sub-reference resistor row 6 is formed in a straight line, and an adjacent sub-reference resistor row is used. Although it is rational in terms of area to arrange and arrange so that 6 is folded back, in order to connect both ends of the sub-reference resistor row 6 to the main reference resistor row 11, at least two sub-reference resistors are required. For row 6,
It is necessary to arrange the wirings 12 and 13 in parallel. Therefore, the length of the wiring 14 that connects the switch row 10 and the sub-comparator row 8 and vertically intersects with the sub-comparator row 8 is increased by the thickness of the wirings 12 and 13. As the length of the wiring 14 increases, the stray capacitance associated with it increases, and the load capacitance of the switch array 10 also increases. Then, each switch S in the switch array 10 conducts between one sub-reference voltage in the sub-reference voltage array 7 and the input of one sub-comparator in the sub-comparator array 8, and then the sub-comparator. However, there is a problem that the time required for the input to become equal to the sub-reference voltage becomes longer, and as a result, the time required for AD conversion becomes longer.

An object of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a serial-parallel AD converter that operates at high speed and has a small area.

Means for Solving the Problems In order to achieve the above object, the present invention provides two main reference voltage trains each comprising a plurality of main reference voltages by dividing a resistance between two reference voltages. A main reference resistor array, a plurality of sub-reference resistor arrays each of which creates a sub-reference voltage array composed of a plurality of sub-reference voltages by dividing a resistance between two main reference voltages, and the two main reference voltages A main comparator array for comparing one of the columns with an input voltage, a main logic circuit receiving the output of the main comparator column as an input, and selecting and outputting one of the plurality of sub-reference voltage columns A row of switches, a sub-comparator row for comparing the output of the switch row with the input voltage, and a sub-logic circuit having an input of the output of the sub-comparator row, the plurality of sub-reference resistor rows Are connected in series. Are connected alternately to the two main reference voltage trains.

According to the present invention, therefore, according to the present invention, the sub-reference resistor rows are linearly arranged and arranged so that adjacent sub-reference resistor rows are folded back, and the odd-numbered connection points of these sub-reference resistor rows are connected. Connected to one main reference resistor row and the even number to the other main reference resistor row, it is possible to reduce the number of wirings running in parallel with the sub-comparator row, Can be shortened. This reduces the stray capacitance and increases the operation speed, so that the A / D conversion can be performed at high speed.

Embodiment FIG. 1 shows an embodiment of the present invention, which has the same configuration as the conventional example shown in FIG. 2 and FIG. 3, so that the same elements are denoted by the same reference numerals. is there. In FIG. 1, 1 is an input voltage, 2A and 2B are reference voltages, 3A and 3B are main reference voltage strings, 4 is a main comparator row, 5 is a main logic circuit, 6 is a sub-reference resistor row, and 7 is a sub-reference resistor row. Reference voltage train, 8 is sub comparator train, 9
Is a sub logic circuit, 10 is a switch row, and 11A and 11B are main reference resistor rows.

In the serial / parallel AD converter shown in FIG. 1, the reference voltages 2A and 2B
Is divided by two main reference resistor strings 11A and 11B, and two main reference voltage strings 3 each including three main reference voltages are provided.
A and 3B are created. The sub-reference resistor row 6 includes a main reference voltage row 3A created by the main reference resistor row 11A and a main reference resistor row 1
The main reference voltages adjacent to the main reference voltage sequence 3B created in 1B are connected alternately, and the sub-reference voltage 7
Create

The main reference voltage and the input voltage 1 on the main reference voltage train 3B side obtained by dividing the reference voltages 2A and 2B by the main reference resistor trains 11A and 11B.
Are compared in the main comparator train 4, and the main logic circuit 5 receives the output of the main comparator train 4 as an input and changes the input voltage 1 to the main reference voltage train 3B.
To determine which of the two main reference voltages are within. Thus, the input voltage 1 is roughly AD-converted. Subsequently, the switch array 10 selects and outputs a sub-reference voltage that divides between the two main reference voltages determined by the main logic circuit 5.
The sub-comparator row 8 compares the output of the switch row 10 with the input voltage 1, respectively, and the sub-logic circuit 9 receives the output of the sub-comparator row 8 as an input and changes the input voltage 1 to any of the sub-reference voltage rows 7. Determine if it is between two sub-reference voltages. As a result, the input voltage 1 is finely AD-converted.

Thus, according to the above embodiment, the main reference resistor row 11A,
By reducing the resistance value of each resistor Rm constituting 11B and increasing the flowing current, when each switch S in the switch array 10 is turned on, the electric charge is reduced to each switch Sm.
From the main reference voltage train 3
Variations in the voltages of A, 3B and the sub-reference voltage train 7 can be reduced. In this case, in order to make the variation of the reference voltage 1 the same as that of the AD converter shown in FIG. 2, assuming that the resistance values of the resistors Rs constituting the sub-reference resistor array 6 are the same, Since the resistance value of each resistor Rm constituting the main reference resistor rows 11A and 11B may be twice as large as that of the main reference resistor row 11 in FIG. 3, the area of the resistors and the power consumption of the entire AD converter are obtained. Is equivalent to the AD converter in FIG. In addition, since the wiring 13 can be omitted among the wirings 12 and 13 parallel to the sub-reference resistor row 6, the area of the entire AD converter is reduced by the area of the wiring 13, and the wiring is reduced by the thickness of the wiring 13. The length of 14 becomes shorter.
For this reason, the stray capacitance accompanying it also decreases, and the load capacitance of the switch array 10 also decreases. As a result, each switch S in the switch array 10 is turned on until one of the sub-reference voltages in the sub-reference voltage array 7 and the input of one of the sub-comparators in the sub-comparator array 8 become equal to the sub-reference voltage. The time is shortened, and as a result, the time required for AD conversion is shortened.

Effects of the Invention As is clear from the above description, according to the present invention, a useful series-parallel AD converter with a high conversion speed and a small area can be realized by adding a few circuits.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a serial-parallel AD converter showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a conventional serial-parallel AD converter, and FIG. FIG. 9 is a circuit diagram illustrating another example of the AD converter. 1 ... input voltage, 2A, 2B ... reference voltage, 3A, 3B ... main reference voltage row, 4 ... main comparator row, 5 ... main logic circuit, 6 ...
Sub-reference resistor row, 7 ... Sub-reference voltage row, 8 ... Sub-comparator row, 9 ... Sub-logic circuit, 10 ... Switch row, 11A, 11B ...
… Main reference resistor row, 12,13,14 …… Wiring, Rs, Rm …… Resistor, S …… Switch.

Claims (1)

(57) [Claims] 1. Two main reference resistor rows each of which is divided by two resistors to generate two main reference voltage rows each comprising a plurality of main reference voltages; A plurality of sub-reference resistor columns that create a sub-reference voltage sequence composed of a plurality of sub-reference voltages by dividing a resistor between the two, and a main comparison that compares one of the two main reference voltage sequences with an input voltage, respectively. A main logic circuit that receives an output of the main comparator row as an input; a switch row that selects and outputs one of the plurality of sub-reference voltage rows; an output of the switch row and the input voltage And a sub-logic circuit that receives an output of the sub-comparator row as an input, wherein the plurality of sub-reference resistor rows are connected in series, respectively. The connection point of the device row alternates between the two main reference voltage rows. Serial-parallel type AD converter characterized in that it is continued.