JPS6131904B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interrupt distributed processing method in a load distributed multiprocessor system.

Traditionally, interrupt processing in multiprocessor systems is
In function distributed systems, interrupt sources and processing units (hereinafter referred to as CPUs) have a one-to-one correspondence, and in load distributed systems, the management CPU
It was common for the CPU to accept interrupt requests all at once and distribute them to other CPUs.

In the former case, the system lacks flexibility, and the processing capacity of the CPU that accepts frequent interrupt requests limits the system's processing capacity.

Although the latter has a degree of freedom, only the management CPU handles interrupt reception and distribution, which reduces the efficiency of simultaneous parallel processing of interrupts and limits the processing capacity of the system.

LSI micro with large interrupt processing overhead
This drawback has been a huge problem in multiprocessor systems that use the CPU to process frequently occurring interrupt requests.

An object of the present invention is to provide a method for distributing interrupts to multiple processors that can easily execute simultaneous and parallel processing of interrupts in order to improve interrupt processing efficiency by removing the management CPU in a load distributed multi-process system. Our goal is to provide the following.

According to the present invention, there is a circuit that accepts a plurality of randomly generated interrupt requests one by one in priority order, a circuit that detects and distributes the accepted interrupt requests to CPUs that can process them, and a circuit that specifies the interrupt destination. interrupt, e.g. 1
It consists of a circuit that distributes interrupts from one CPU to other CPUs to designated CPUs, and generated interrupts are automatically cleared by hardware.
A method for distributing interrupts to a multiprocessor in which the interrupts are distributed to the CPU can be obtained.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. A timer interrupt, an inter-CPU interrupt, a console interrupt, and an input/output interrupt are input to the interrupt request receiving circuit 100 in descending order of priority. An input/output interrupt is a single interrupt line whose priority order is determined by interconnection of input/output devices. The interrupt request accepting circuit 100 accepts the interrupt request, and only one interrupt request is input to the distribution circuit 150. If this interrupt request is other than an input/output interrupt request, the interrupt destination instruction circuit 14
The distribution circuit 150 operates according to the instruction of 0 and interrupts the designated CPU. On the other hand, in the case of an input/output system interrupt request, the distribution circuit 150 operates according to instructions from the circulation instruction circuit 110 and interrupts the instructed CPU. When the circulation instruction circuit 110 detects that the CPU has accepted an interrupt, it updates an internal counter so that the cycle will be made to the next CPU at the next interrupt. If the interrupted CPU cannot accept the interrupt,
The CPU interrupt disable condition detection circuit 130 activates the circulation skip control circuit 120, updates the internal counter of the circulation instruction circuit, and circulates the interrupt to the next CPU.

Next, details of the circulation instruction circuit 110, the circulation skip control circuit 120, and the CPU interrupt disable condition detection circuit will be explained with reference to FIGS. 2 to 4.

FIG. 2 is a block diagram showing the circulation instruction circuit. The output of the counter 111 is an output signal 200 to the distribution circuit. The counter 111 is
The output 205 of the register 112 and the output 200 of the counter, which specify the maximum number of system implementations, are updated by a pulse obtained by differentiating the leading edge of the logical sum of the CPU interrupt acceptance signal and the output signal 201 of the cyclic skip circuit, and are output by the matcher 113. They are compared, and if they match, the matching signal 206 is reset by a pulse obtained by differentiating the leading edge.

FIG. 3 is a block diagram showing the circulation skip control circuit. The circulation control signal 201 to the circulation instruction circuit 110 is the output 200 of the counter 111,
Output 202, 20 of CPU interrupt disable condition detection circuit
3,204 and Matsushiya 121, 122,
123, and the logical sum of each matching signal is calculated.

FIG. 4 is a block diagram showing a CPU interrupt disable condition detection circuit. A signal 202 indicates an overflow of a failure detection timer provided for each CPU. This timer detects a failure by stopping periodic reset by the program and overflowing when each CPU experiences a failure. Signal 203 indicates that no CPU is installed. This signal is one for each CPU.
Indicated by book signal line. Signal 204 is the output of a busy indicating flip-flop provided for each CPU. This flip-flop sets the flip-flop corresponding to each CPU when it does not accept an interrupt, and resets the flip-flop corresponding to its own CPU when it accepts an interrupt.

By using the interrupt distribution circuit as described above, the present invention has the advantage that the time required for interrupt distribution is shortened and frequently occurring interrupt requests can be efficiently distributed and processed. . This is particularly effective for LSI CPUs with large interrupt processing overhead.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing details of the circulation instruction circuit shown in FIG. 1, and FIG. 3 is a circulation skip control shown in FIG. 1. Block showing details of the circuit, 4th
FIG. 1 is a block diagram showing details of the CPU interrupt disable condition detection circuit shown in FIG. 100: Interrupt request acceptance circuit, 110: Circulation instruction circuit, 120: Circulation skip control circuit, 13
0: CPU interrupt disable condition detection circuit, 140: Circulation destination instruction circuit, 150: Distribution circuit.

Claims (1)

[Claims] 1. In a load-balanced multiprocessor system consisting of multiple processing units, there is a circuit that accepts random interrupt requests generated from multiple interrupt sources one by one in priority order, and a circuit that sequentially sends the accepted interrupt requests to each processing unit. A circuit that instructs the interrupt to be circulated, a circuit that detects a condition in which the processing device that is attempting to cause an interrupt cannot execute the interrupt processing, and controls the interrupt destination to be circulated to other processing devices; a circuit that instructs the previous processing device to interrupt the specified interrupt request to the specified processing device; and a circuit that distributes the interrupt request to each processing device according to the output signal of each of the instruction circuits. An interrupt distribution method comprising: