JPS631633B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a data transfer device which includes a large number of switch modules and which transfers data from any processor connected via the switch modules to any other processor. The present invention relates to a data transfer method that enables a transfer device to dynamically equalize processor loads.

In a parallel processing computer in which a large number of processors are connected via a transfer system, it is important to equalize the load among the processors from the viewpoint of improving processing efficiency.
Equalization of the load can be easily achieved by dynamically distributing the load on the transfer system. However, the operation of conventional transfer systems has been passive. That is, the processor issues a transfer request specifying the transfer destination processor to the transfer system, and the transfer system receives the request and transfers the data to the designated processor. Therefore, load distribution was left to the software side. In other words, the programmer had to program so that the processor loads were balanced. This is the biggest factor causing load imbalance.

FIG. 1 is a schematic diagram of a conventional parallel processing computer. Now, let us consider the parallel execution of an algorithm whose processing form has a tree structure, typified by the divide-and-conquer method as shown in FIG. 2a, on such a parallel processing computer. Assign processing of one node of the tree to one processor. In this case, the name node of the tree is allocated to each processor as shown in FIG. 2b, which obviously causes load imbalance among the processors.

By the way, the problem of load distribution causes problems such as increased software burden, increased processing overhead, and load imbalance due to allocation errors.
This results in a decrease in processor utilization and system throughput.

An object of the present invention is to provide a data transfer method that enables dynamic load distribution.

Therefore, the present invention simplifies the means for dynamically determining the transfer destination processor by using the packet transfer method as the data transfer method. Further, the present invention is characterized by having a plurality of transfer modes in order to provide processor load information to the transfer system,
Furthermore, in order to grasp processor load information, it is characterized by having a counter that counts the number of packets passing through the switch module.

The data transfer method of the present invention will be described in detail below based on an illustrated embodiment.

FIG. 3 shows an embodiment of the present invention, and FIG. 3a shows a data transfer device in which a large number of switch modules 1 are connected in a two-dimensional array. A processor 2 is connected to each switch module 1. On the other hand, the third
FIG. b shows a data transfer device 4 having a multistage configuration of a large number of switch modules 3, and processors 5 and 5' are connected to input and output terminals of the data transfer device 4.

The configuration diagram of the switch module 1 in FIG. 3a is shown in FIG. 4a, and the switch module 3 in FIG. 3b is shown in FIG.
The configuration diagram is shown in Fig. 4b. In Fig. 4 a and b, 6 and 10 are input circuits, 7 and 11 are switches,
8 and 12 are output circuits, and 9 and 13 are counters.

Since the basic operations of both the data transfer devices shown in FIGS. 3a and 3b are the same, the data transfer device 4 shown in FIG. 3b will be explained below.

FIG. 5 shows the input circuit 1 of the switch module 3, which is a component of the data transfer device 4 shown in FIG. 3b.
0, a detailed diagram of the switch 11, and the output circuit 12. 13 is a counter, 14 is an input queue, 15 is an input control circuit, 16 is a mode queue, 17 is an output selection information queue, 18 is a selector, 19 is a selector control circuit, 20 is an arbiter, 21 is a selector,
22 is an OR gate, 23 is a counter control circuit, 2
4 is a comparison circuit.

FIG. 6 is a diagram showing the configuration of a transfer packet. Packets are transferred serially in data bus width units. In FIG. 6, 25 is a packet head, 26 is a packet body, and the leading portion of the packet head 25 is used for output selection information.

Now, in the data transfer device 4 shown in FIG. 3B, a task is used as a unit of assignment to the processors 5 and 5'.
Here, a task is a single unit of processing, like a tree node in FIG. It is assumed that each processor is capable of processing all tasks, and a task is activated when the parameters necessary for the processing are complete. When a task generates a child task (in the example in Figure 2, one node in the tree issues a processing request to a child node), the child task is processed by a light-load processor in order to distribute the processor load. . For this purpose, the processor issues a processing request to the data transfer device. The data transfer device dynamically searches for light-load processors and assigns tasks to them. The processor to which the task has been assigned performs the processing and returns the result to the requesting processor. In this system, task processing proceeds in this manner.

In order to realize the dynamic distribution of the processor load, this data transfer device has three transfer modes, and packets are transferred in one of the transfer modes. The three transfer modes are:

(a) Search mode (S mode): This is a transfer mode for dynamically searching for a load processor. Packets in this mode are
In the switch module 3, the values of the counters 13 associated with the respective output circuits 12 are compared, and the smaller output circuit is selected. Then, the value of the counter on the selected side is counted up. If the values of both counters are the same, select one of the output circuits.

(b) Transfer mode (T mode): This is a transfer mode when the transfer destination processor is always fixed. A packet in this mode has output selection information at the beginning of the packet head. In the switch module 3, the output circuit 12 is selected according to this value.

(c) Finishing mode (F mode): This is a transfer mode for notifying the data transfer device of the end of a task. A packet in this mode has output selection information at the beginning of the packet head. In the switch module 3, the output circuit 12 is selected according to this value. Further, the value of the counter 13 associated with the selected output circuit 12 is counted down.

Using these transfer modes, processor load distribution can be achieved by the following method.

When a task generates a child task, the data necessary for processing the child task is made into a packet and a processing request is issued to the data transfer device. The transfer mode of this packet is S mode. If the data consists of multiple packets, any one of them is transferred in S mode. When the data transfer device dynamically determines the processing processor for the child task, it sends a packet to inform the requesting processor that the processing destination has been determined. This transfer mode is T mode. When the requesting processor receives this packet, if the processing request consists of a plurality of packets, it transfers the remaining packets in T mode. The destination processor processes the child task using the transferred data, obtains the results, and returns the results to the requesting processor in T mode in one or more packets. When the requesting processor receives the result, it converts the result into a packet and transfers it in F mode. Such packet transfer is performed during the process from the creation of a child task to its destruction.

The transfer sequence of the switch module 3 for packets in each mode is as follows.

In FIG. 5, the input queue 14 contains a packet, the mode queue 16 contains the transfer mode of the packet corresponding to the packet in the input queue 14, and the output selection information queue 17 also contains output selection information. It is assumed that it is included. However, although the output selection information for S mode packets is not defined, dummy data is entered in the output selection information queue 17 as the corresponding output selection information,
It is assumed that the order relationship of packets in each queue 14, 16, and 17 is maintained. The counter 13 holds the difference between the number of S mode packets and the number of F mode packets among the packets that have passed through the output circuit 12. The comparison circuit 24 compares the values of the counters of the two output circuits and outputs a magnitude relationship. It becomes an input to the selector control circuit 19. below,
Explain the transfer sequence.

(i) The input control circuit 15 outputs a transfer mode (mode) from the mode queue 16, and outputs a processing request signal (reg). The transfer mode becomes a control signal for the selector control circuit 19 and is simultaneously sent to the next stage switch module via the selector 18.

(ii) The selector control circuit 19 determines the output of the selector 18 from the output value of the comparison circuit 24 (in S mode) or the output selection information queue 17 (in T, F mode) according to the transfer mode.

(iii) The reg signal and transfer mode are set by the selector 18,
The signal passes through the arbiter 20 and reaches the input control circuit 15 and mode queue 16 of the next-stage switch module.

(iv) The input control circuit 15 (of the next stage switch module)
return signal. At the same time, the transfer mode is loaded into the mode queue 16. When the input queue 14 is full, no ack signal is returned until there is space in the queue. Also, the transfer mode is not included.

(v) The ack signal becomes an input to the counter control circuit 23, which performs a predetermined operation depending on the transfer mode (count up in S mode, count down in F mode, do nothing in T mode). It also goes to the input control circuit 15 via the selector 21 and OR gate 22. As the output of the selector 12, the output corresponding to the input circuit 10 selected by the arbiter 20 is selected.

(vi) The input control circuit 15 sends the packet at the head of the input queue 14 to the selector 18 and the arbiter 20.
is transferred to the input queue 14 of the next stage switch module. At this time, the output selection information is also entered into the output selection information queue 17 under the control of the input control circuit 15.

(vii) After the packet transfer is completed, the input control circuit 15
Turn off the reg signal and end the transfer sequence.

As explained above, according to the present invention, the data transfer device can dynamically perform task distribution control using the counter provided in the switch module and equalize the processor load, so that the program processing can be The throughput and processor operating rate increase, and there is no need for software to be conscious of load distribution. Furthermore, since many switch modules with simple circuit configurations are used,
Suitable for LSI.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional parallel processing computer, Figure 2
The figure shows a schematic diagram of a tree-structured program, a diagram showing how the nodes of the tree are assigned to the parallel processing computer in Figure 1, and Figure 3.
Figures a and b are block diagrams of an embodiment of the data transfer system of the present invention, Figures 4a and b are block diagrams of the switch modules in Figures 3a and b, and Figure 5 is the switch module in Figure 4b. FIG. 6 is a detailed block diagram of the module, and FIG. 6 is a block diagram of the packet. 1, 3... switch module, 2, 5, 5'...
Processor, 4...Data transfer device, 6, 10...Input circuit, 7, 11...Switch, 8, 12...Output circuit, 9, 13...Counter, 14...Input queue, 1
5...Input control circuit, 16...Mode cue, 17...
Output selection information queue, 18, 21...Selector, 1
9... Selector control circuit, 20... Arbiter, 22...
OR gate, 23...Counter control circuit, 24...Comparison circuit, 25...Packet head, 26...Packet body.

Claims (1)

[Claims] 1. It is constructed by combining multiple switch modules that have multiple inputs and multiple outputs and can switch from any input to any output, and can be connected to any processor connected via the switch module. In a data transfer device capable of transferring data to a processor, the switch module has a counter for displaying the load of the subordinate processor corresponding to the output, and the data transfer device performs data transfer by packets, and the transfer mode is , a mode for dynamically searching for a light-load processor, a mode for notifying that the processor load has been reduced, and a mode for transferring data to a specified processor. The transfer mode packet to search for is
The switch module selects the output with the smallest counter value and counts up the corresponding counter, and also counts down the counter for transfer mode packets to notify that the load on the processor has been reduced, and these counter operations 1. A data transfer method characterized in that processor load information is provided to a data transfer device by means of a data transfer device, and the data transfer device dynamically distributes the processor load.