JPS58200366A - Data transfer system - Google Patents

Abstract

PURPOSE:To improve a throughput and an operating rate by processing a data transfer device under the dynamic decentralized control of a counter provided to a switch module, and making uniform a load on a processor. CONSTITUTION:When a task generates a subtask, a processor 5 buckets data necessary for subtask processing and sends a request for processing to the data transfer device 4. In the switch module 3 of the data transfer device 4, the values of counters 13 attached to respective output circuits 12 are compared for finding a light-load processor dynamically to select one output circuit 12, to which the task is alloted. The processor 5' allotted for the task performs the processing and returns the result to the requesting processor 5.

Description

DETAILED DESCRIPTION OF THE INVENTION In a data transfer device that transfers data from any processor connected via the switch module to any other processor, the data transfer device dynamically equalizes processor loads. This relates to a data transfer method that makes it possible to do this.

In a parallel processing computer in which a large number of processors are connected via a transfer system, it is important to equalize the load among the processors from the viewpoint of improving processing efficiency.

Equalization of the load can be easily achieved by dynamically distributing the load on the transfer system. However: The operation of conventional transfer systems has been passive. That is, the processor issues a transfer request specifying the transfer destination processor to the transfer system, and the transfer system receives the request and transfers the data to the specified processor. Therefore, load distribution was left to the software side. In other words, the programmer had to program so that the processor loads were balanced.

This is the biggest factor causing load imbalance.

FIG. 1 is a schematic diagram of a conventional parallel processing computer. Now, let us consider parallel execution of an algorithm whose processing form has a tree structure, as represented by the divide-and-conquer method, as shown in FIG. 2 (α), on such a parallel processing computer. Assign processing of one node of the tree to one processor. Then, each node of the tree is assigned to each processor as shown in FIG. 2(h), which clearly causes load imbalance among the processors.

By the way, the problem of load distribution causes problems such as an increase in the burden on software, an increase in processing overhead, and load imbalance due to incorrect allocation, which leads to a decrease in processor utilization rate and a decrease in system throughput. It turns out.

An object of the present invention is to provide a data transfer device that enables dynamic load distribution.

Therefore, the present invention simplifies the means for dynamically determining the transfer destination processor by using the packet transfer method as the data transfer method. Further, the present invention is characterized by having a plurality of transfer modes in order to provide processor load information to the transfer system, and furthermore, in order to control the processor load information, the number of packets passing through the switch module is counted. It is characterized by having a counter.

The data transfer method of the present invention will be described in detail below based on an illustrated embodiment.

FIG. 3 shows an embodiment of the present invention, and FIG. 8 (α) shows a data transfer device in which a large number of switch modules 1 are combined into a 21-dimensional array P. A processor 2 is connected to each switch module l. On the other hand, FIG. 8(h) shows a data transfer device 4 in which a large number of switch modules 8 are configured in multiple stages, and the input/output of the data transfer device 4 includes a processor 5.5.
′ is connected.

FIG. 4(a) shows a block diagram of the switch module l of FIG. 8(α), and FIG. 4(h) shows a block diagram of the switch module 8 of FIG. 3<b>. In FIGS. 4(a) and (h), 6 and 10 are input circuits, 7 and 11 are switches, and 8
．． 12 is an output circuit, and 9.18 is a counter.

Since the basic operation of both data transfer devices in FIG. 3(α) and FIG. 3(h) is the same, the data transfer device 4 in FIG. 3(Ch) will be explained below.

FIG. 5 shows an input circuit 10, a switch 11 . 3 is a detailed diagram of the output circuit 12. FIG. 18 is a counter, 14 is an input queue, 15 is an input control circuit, 16 is a mode queue, 17 is an output selection information queue, 18 is a selector, 19 is a selector control circuit, 20 is an arbiter, 21 is a selector, 22 is an OR gate, 23 is the counter control circuit,
24 is a comparison circuit.

FIG. 6 is a configuration diagram of a transfer packet. Packets are transferred serially in data bus width units. In Figure 6, 25
is the packet head, 26 is the packet body, and the leading part of the packet head 25 is used for output selection information.

Now, in the data transfer device 4 of FIG. 8<h), a task is the unit of assignment to the processor 5.5'. Here, a task is a single unit of processing, like a tree node in Figure 2. It is assumed that each processor is capable of processing all tasks, and a task is activated when the parameters necessary for the processing are complete. When a task generates a child task (in the example in Figure 2, one node in the tree issues a processing request to a child node), the child task is processed by a light-load processor in order to distribute the processor load. Ru. For this purpose, the processor issues a processing request to the data transfer device. The data transfer device dynamically searches for lightly loaded processors and assigns tasks to them.

The processor to which the task has been assigned performs the processing and returns the result to the requesting processor. In this system, task processing proceeds in this manner.

In order to realize the dynamic distribution of the processor load mentioned above,
This data transfer device has three transfer modes, and packets are transferred in one of the transfer modes. The three transfer modes are:

(a) Search mode (S mode): This is a transfer mode for dynamically searching for a reload processor. For packets in this mode, the switch module 8 compares the values of the counters 13 associated with the respective output circuits 12 and selects the smaller output circuit. Then, the value of the counter on the selected side is counted up. If the values of both counters are the same, select one of the output circuits.

(h) Transfer mode (T mode): This is a transfer mode when the transfer destination processor is always fixed. A packet in this mode has output selection information at the beginning of the packet head. In the switch module 3, the output circuit 12 is selected according to this value.

(C) File transfer mode (F single mode): This is a transfer mode for notifying the data transfer device of the end of a task. Nonoket in this mode has output selection information at the beginning of the packet head. In switch module 8,
Output circuit 12 is selected according to this value. Furthermore, the value of the counter 18 associated with the selected output circuit 12 is counted down.

Using these transfer modes, the processor load can be distributed by the following method.

When a task generates a child task, the data necessary for processing the child task is made into a packet and a processing request is issued to the data transfer device. The transfer mode of this packet is S mode. If the data consists of multiple packets, any one of them is transferred in S mode. When the processing processor for the child task is dynamically determined, the data transfer device notifies the requesting processor in the form of a packet that the processing destination has been determined. This transfer mode is T mode. When the requesting processor receives this packet, if the processing request consists of a plurality of packets, it transfers the remaining packets in T mode. The processing destination processor processes the child task based on the transferred data, obtains the result, converts it into one or more packets, and returns it to the requesting processor in T mode.

When the requesting processor receives the result, it converts the result into a packet and transfers it in F mode. Such packet transfer is performed during the process from creation to destruction of a child task.

The transfer sequence of the switch module 8 for packets in each mode is as follows.

In FIG. 5, the input queue 14 contains a packet, the mode queue 16 contains the transfer mode of the packet corresponding to the packet in the input queue 14, and the output selection information queue 17 also contains output selection information. It is assumed that . However, output selection information for S mode packets is not defined, but output selection information queue 17
Input dummy data as the corresponding output selection information,
It is assumed that the order relationship of packets in each queue 14, 16, and 17 is maintained. The counter 13 holds the difference between the number of S mode packets and the number of F mode packets among the packets that have passed through the output circuit 12. Comparison circuit 2
4 compares the values of the counters of the two output circuits and outputs the magnitude relationship. It becomes an input to the selector control circuit 19. The transfer sequence will be explained below.

(1) The input control circuit 15 outputs the transfer mode (mode) from the mode queue 16, and itself receives the processing request signal (r
eq). The transfer mode becomes a control signal for the selector control circuit 19 and is simultaneously sent to the next stage switch module via the selector 18.

(11) The selector control circuit 19 determines the output of the selector 18 based on the output value of the comparison circuit 24 (in S mode) or the output selection information queue 17 (in T or F mode) according to the transfer mode.

1i) The req signal and transfer mode are set by selector 1.
8. The signal reaches the input control circuit 15 and mode queue 16 of the next stage switch module via the arbiter 20.

(iV) The input control circuit 15 (of the next-stage switch module) returns the αck signal unless the input queue 14 is full. At the same time, the transfer mode is loaded into the mode queue 16. When the input queue 14 is full, the ack signal is not returned until there is space in the queue. It also does not import the transfer mode.

The αck signal becomes an input to the counter control circuit 23, and performs a predetermined operation depending on the transfer mode (count up in S mode, count down in F mode, do nothing in T mode). It also goes to the input control circuit 15 via the selector 21 and OR gate 22. Selector 2
1, the output corresponding to the input circuit 10 selected by the arbiter 20 is selected.

(vl) The input control circuit 15 transfers the packet at the head of the input queue 14 to the input queue 14 of the next stage switch module via the selector 18 and arbiter 20.

At this time, the output selection information is also put into the output selection information queue 17 under the control of the input control circuit 15: .

(vll) After the packet transfer is completed, the input control circuit 15
The eq signal is turned off and the transfer sequence ends.

As explained above, according to the present invention, the data transfer device can dynamically perform task distribution control using the counter provided in the switch module and equalize the processor load, thereby increasing the throughput of program processing. , the utilization rate of the processor increases, and there is no need to be aware of load distribution on the software side. Furthermore, since many switch modules with simple circuit configurations are used, the LS
Suitable for I.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional parallel processing computer, Figure 2 is a schematic diagram of a tree-structured program and a diagram showing how the nodes of the tree are assigned to the parallel processing computer in Figure 1, and Figures 8 (α) and (b). ) is a configuration diagram of an embodiment of the data transfer method of the present invention, and FIG.
), (b) are configuration diagrams of the switch modules in Figures 3(a) and (h), Figure 5 is a detailed configuration diagram of the switch module in Figure 4 <b>, and Figure 6 is a diagram of the packet configuration. be.
. 1.3...Switch module, 2,5.5'...
Processor, 4... Data transfer device, 6, 10...
Input circuit, 7.11...Switch, 8.12...Output circuit, 9.13...Counter, ■4...Input queue, 15...Input control circuit, 16...Mode queue , 17... Output selection information queue, :ts, 21...
Selector, 19... Selector control circuit, zO... Arbiter, 2z... OR gate, 23... Counter control circuit, 24... Comparison circuit, 25... Packet head, 26... Packet Body. Agent Patent Attorney Makoto Suzuki (':(B)
1 Figure 3 (α) Figure 4 C (1) (b)

Claims (1)

[Claims] (1) Constructed by combining multiple switch modules that have multiple inputs and multiple outputs and can switch from any input to any output, and from any processor connected via the switch module to any processor In the data transfer device capable of transferring data to, the switch module has a counter for displaying the load of the subordinate processor corresponding to the output, and the data transfer device performs data transfer by packets, and the transfer mode is: It has a mode for dynamically searching for a light load processor, a mode for notifying that the processor load has been reduced, and a mode for transferring data to a specified processor. For transfer mode packets to be searched, the switch module selects the output with the smallest counter value and counts up the corresponding counter, and for transfer mode packets to notify that the load on the processor has been reduced, the counter is counted up. A data transfer method characterized by counting down the counters, providing processor load information to a data transfer device by operating these counters, and causing the data transfer device to dynamically distribute the processor load.