JPS61296717A - Formation of fine pattern - Google Patents

Abstract

PURPOSE:To avoid crackings created in spin-on glass material of a silica intermediate layer when the silica intermediate layer is baked by a method wherein a lower photoresist layer is exposed to ultraviolet rays and is at the same time subjected to a heat treatment. CONSTITUTION:On the assumption that there are surface steps 2 on a semiconductor substrate 1, after a positive type photoresist of phenolic-novolak-based material is applied to the surface, far ultraviolet rays are applied and, at the same time, a heat treatment is performed by a hot-plate to form a lower photoresist layer 21 which has a flat surface without steps. Then spin-on glass material is applied to the lower photoresist layer 21 and subjected to a heat treatment to form an intermediate layer 12 of silica material. After that, an upper photoresit layer 13 is formed and predetermined exposed parts 3 are removed by a developer to form an upper layer photoresist pattern 13A. The predetermined parts of the silica intermediate layer 12 are removed by using the upper layer photoresist pattern 13A as a mask to form a silica intermediate layer pattern 12A and a lower layer photoresist pattern 21A is formed by etching for a predetermined period by using the intermediate layer pattern 12A as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming fine patterns, and particularly to a method for forming fine patterns suitable for large-scale integrated circuits.

[Conventional technology]

In recent years, in semiconductor devices such as LSI and VLSI,
Chips containing several dozen to millions of semiconductor elements have appeared, and as a result, the packaging density of elements in semiconductor devices has become extremely high, requiring miniaturization of element patterns formed on semiconductor substrates. has been done.

Therefore, it is difficult to decide whether to use a multilayer resist method to form the fine patterns required for these large-scale integrated circuits.
The process is performed as shown in Figures (a) to (f).

First, a surface step 2 of approximately 0.5 μm is formed on the surface of the semiconductor substrate l.
Suppose there is. On top of that, apply a positive photoresist made of phenol/novolak material (for example, Silapray (5hip)
Microposit manufactured by Ray)
t) 1300-38) to about 1 by the spin code method.
．． After coating to a thickness of 8 μm, the lower photoresist layer 11 is heated on a hot plate at 200 C for 90 seconds to form a lower photoresist layer 11 having a flat surface with no steps (see FIG. 2).
a)).

Next, on the lower photoresist layer 11, a spin-on photoresist layer is formed.
x, (5pin Qn Qlass) material (for example, 0CD manufactured by Tokyo Ohka Kogyo Co., Ltd.) was coated by the same spin code method and heated on a hot plate at 190C for 60 seconds to form an intermediate layer of silica material H2 with a thickness of 0.12 μm. (Fig. 2(b)).

In step-11, a positive photoresist (for example, Microbodi manufactured by Silapray) 1400 is applied on the silica intermediate layer 12.
-10) is applied to a thickness of 0.6 .mu.m by a spin code method and subjected to hot plate heat treatment at 100 C for 45 seconds to form the upper photoresist layer 13 (FIG. 2(C)).

Next, a reduction projection type exposure device (for example, DSW manufactured by GCA)
4800) and a developer containing tetramethylammonium hydroxide (CHI)4N.OH as a main component, a predetermined exposed portion 3 of the upper photoresist layer 130 is removed to form the upper photoresist pattern 13A.
(Fig. 2(d)).

Next, using a parallel plate reactive ion etching device,
The upper photoresist pattern 13A is masked in plasma of a mixed gas of CFa and H8, and a predetermined portion of the silica intermediate layer 120 is removed by etching.
A is formed (Fig. 2(e)).

Next, the etching gas of the reactive etching device was
When etching is further performed for a predetermined period of time using the silica intermediate layer pattern 12A as a mask, a predetermined portion of the lower photoresist layer 11 and the upper photoresist pattern 13A are removed, and a lower photoresist pattern IIA is formed. Two-layer resist pattern formation is completed. (Figure 2(f)).

In the multilayer resist method according to the above method, the steps on the surface of the semiconductor substrate are flattened by the lower photoresist layer 11,
Since the thickness of the upper photoresist layer 13 can be made thinner than in the case of a single-layer photoresist method, pattern resolution and dimensional controllability are significantly improved.

[Problem that the invention seeks to solve]

In the conventional multilayer resist method described above, when a spin-on glass material with a silica intermediate layer is applied and then heat-treated,
Cracks are particularly likely to occur on the stepped portion 2 of the half-quad board.
As a result, pattern defects are increased compared to the conventional single-layer "sist" method, which adversely affects the cost and performance of the product.

The cause of this problem is that the lower photoresist film shrinks in volume when baking the silica intermediate layer.The possible solution is to increase the baking temperature of the lower photoresist layer or lower the baking temperature of the silica intermediate layer. It will be done. However, if the baking temperature of the lower photoresist layer is raised significantly higher than before, the novolac resin will deteriorate and become unusable as a mask when etching the semiconductor substrate surface in the later process. If the temperature is lower than the conventional temperature, the solvent component in the material cannot be removed sufficiently, which will have an adverse effect on the subsequent formation of the upper layer photoresist pattern.

[Means for solving problems]

The fine pattern forming method of the present invention is applied to the surface of a semiconductor substrate (including cases where an insulating layer, a semiconductor layer, or a metal layer is laminated on the surface of a semiconductor substrate, singly or in combination).
a step of forming a resin layer on the resin layer, a step of heating the resin layer while irradiating it with ultraviolet light, a step of laminating an inorganic layer on the resin layer, and a step of laminating a photoresist layer on the inorganic layer. a step of selectively removing the photoresist layer to form an upper resist pattern; a step of removing a predetermined portion of the inorganic layer by masking the upper resist pattern; and a step of removing the resin using the inorganic layer as a mask. and removing a predetermined portion of the layer.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(f) are longitudinal cross-sectional views showing the steps of an embodiment of the fine pattern forming method of the present invention.

First, it is assumed that there is a surface step 2 of about 0.5 μm on the semiconductor substrate 1. On top of that, a positive photoresist made of phenol-e-novolatile material (for example, Silaplay (5hiple)) is applied.
y) Micro-posit manufactured by
) 1300-38) to about 1 by the spin code method.
．． After coating to a thickness of 8 μm, a deep ultraviolet light irradiation device (for example, Microl manufactured by Fusion) was applied.
ite Photostabilizer 126PA
) is used to irradiate deep ultraviolet light 4 and at the same time perform heat treatment using a hot plate to form a lower photoresist layer 21 having a flat surface with no steps (see FIG.
a)). Here, the irradiation conditions are in the wavelength range 200 to 300.
Rlm deep ultraviolet light is irradiated for 60 seconds at an illuminance of 0.75 W/m. As heating conditions, the hot plate temperature was set at 100C at the start of irradiation, and then 2. The hot plate temperature is increased at a rate of OC/sec, and irradiation is completed when the hot plate temperature reaches 220C after 60 seconds.From the time the irradiation is completed, the hot plate temperature is lowered to room temperature (22~22C) within 60 seconds by water cooling method. 230].

Next, a spin-on glass material (for example, 0CD manufactured by Tokyo Ohka Kogyo Co., Ltd.) is coated on the lower photoresist layer 21 by a spin code method, and heated on a hot plate at 2201:1' for 60 seconds to form a film with a thickness of 0.12 μm. An intermediate layer 12 made of silica material is formed (FIG. 1(b)).

Next, a positive photoresist (
For example, Microposit 1400-10 manufactured by 8hipley
) is coated by a spin code method and subjected to hot plate heating treatment for 1.45 seconds to form an upper photoresist layer 13 (FIG. 1(C)).

Next, a reduction projection exposure system! (For example, GCA's DSW4
800) and a developer containing tetramethylammonium hydroxide (CHs)4N110H as a main component, a predetermined exposed portion 3 of the upper photoresist layer 13 is removed, and the upper photoresist pattern 13 is removed.
A is formed (Fig. 1(d)).

Next, using a parallel plate type reactive ion etching device, processing was performed with a plasma of a mixed gas of CF4 and H2.
Using the upper photoresist pattern 13A as a mask, a predetermined portion of the silica intermediate layer 120 is removed to form a silica intermediate layer pattern 12A (FIG. 1(e)).

Further, the etching gas of the reactive ion etching apparatus is changed to 02, and etching is performed for a predetermined time using the silica intermediate layer pattern 12A as a mask. As a result, a predetermined portion of the lower resist layer 21 and the upper layer photoresist pattern 13A are etched away to form a lower layer photoresist pattern 21A, completing the formation of a fine resist pattern according to the present invention (Figure 1 (f)). Effects of the Invention As explained above, in the present invention, by irradiating the lower photoresist layer with ultraviolet light and heat-treating it, the polymerization of the phenol-novolac resin, which is the main component of the photoresist material, is significantly promoted.

Therefore, the heat resistance of the lower photoresist layer is improved, and the volumetric shrinkage during baking of the next silica intermediate layer can be reduced to i/10 or less compared to the conventional method.

For this reason, cracks that occur in the spin-on glass material of the silica intermediate layer during baking of the silica intermediate layer are smaller than in the past.
It has become possible to reduce this to a negligible level of /100 or less. Therefore, it is extremely preferable for improving product yield and lowering prices in mass production processes.

[Brief explanation of drawings]

FIGS. 1(a) to (f) are vertical cross-sectional views showing an example of the fine pattern forming method of the present invention in the order of steps, and FIGS. 2(a) to (f) are steps of the conventional fine pattern forming method. FIG. 1...Semiconductor substrate, 2...Surface step,
3. River: predetermined exposure area, 4. River: far ultraviolet light, 11.
21 ... lower photoresist layer, IIA,
21A... River/lower photoresist pattern, 12...
... Silica intermediate layer, 12A... Silica intermediate layer pattern, 13... Upper photoresist layer,
13A... Upper layer photoresist pattern. Gu・shi / $ l Figure 1 $ 2 Figure

Claims (1)

[Claims] A step of forming a resin layer on the surface of a semiconductor substrate, a step of heat-treating the resin layer while irradiating it with ultraviolet light, a step of laminating an inorganic layer on the resin layer, and a step of depositing a photoresist layer on the inorganic layer. a step of laminating the photoresist layer; a step of selectively removing the photoresist layer to form an upper resist pattern; a step of removing a predetermined portion of the inorganic layer using the upper resist pattern as a mask; and a step of removing the inorganic layer as a mask. and removing a predetermined portion of the resin layer.