KR20030092865A - Forming method for fine patterns of semiconductor device - Google Patents
Forming method for fine patterns of semiconductor device Download PDFInfo
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- KR20030092865A KR20030092865A KR1020020030703A KR20020030703A KR20030092865A KR 20030092865 A KR20030092865 A KR 20030092865A KR 1020020030703 A KR1020020030703 A KR 1020020030703A KR 20020030703 A KR20020030703 A KR 20020030703A KR 20030092865 A KR20030092865 A KR 20030092865A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/039—Macromolecular compounds which are photodegradable, e.g. positive electron resists
- G03F7/0392—Macromolecular compounds which are photodegradable, e.g. positive electron resists the macromolecular compound being present in a chemically amplified positive photoresist composition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
Description
본 발명은 반도체소자의 미세패턴 형성방법에 관한 것으로, 보다 상세하게 감광막패턴의 표면을 경화시킨 후 플로우(flow) 공정을 실시하여 패턴 프로파일의 변형을 방지하는 반도체소자의 미세패턴 형성방법에 관한 것이다.The present invention relates to a method of forming a fine pattern of a semiconductor device, and more particularly, to a method of forming a fine pattern of a semiconductor device which prevents deformation of a pattern profile by performing a flow process after curing the surface of the photoresist pattern. .
최근에 반도체의 집적도가 비약적으로 증가함에 따라 리소그래피(lithography) 분야에서 가장 큰 문제점으로 대두되는 것 중의 하나가 장비 및 감광막의 한계 해상력을 넘어선 콘택홀 패턴의 형성이다. 현재 KrF 리소그래피에 있어 콘택홀 패터닝의 한계는 약 0.18㎛ 정도이고, 그 이하의 작은 콘택홀을 형성하기 위하여 현재로서는 감광막 플로우를 이용하는 방법이 가장 각광받고 있는 실정이다.Recently, as the integration of semiconductors has increased dramatically, one of the biggest problems in the lithography field is the formation of contact hole patterns beyond the limit resolution of equipment and photoresist. Currently, the limit of contact hole patterning in KrF lithography is about 0.18 μm, and a method of using a photoresist film flow is currently in the spotlight to form a small contact hole of less than that.
감광막의 플로우는 노광 장비의 분해능 이상의 미세 콘택홀을 형성하기 위한 공정 기술로서, 일단 감광막을 패터닝한 후에 감광막 내의 중합체가 갖는 유리전이 온도 (Glass Transition Temperature ; Tg) 이상으로 다시 가열하여 감광막을 플로우 시킴으로써 콘택홀 크기를 줄일 수 있는 방법이다.The flow of the photoresist film is a process technology for forming a fine contact hole having a resolution higher than that of an exposure apparatus.The patterning film is once patterned and then heated again above the glass transition temperature (Tg) of the polymer in the photoresist film to flow the photoresist film. This can reduce the contact hole size.
이하, 첨부된 도면을 참고로 하여 종래기술에 따른 반도체소자의 미세패턴 형성방법에 대하여 설명한다.Hereinafter, a method for forming a fine pattern of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.
도 1a 내지 도 1c 는 종래기술에 따른 반도체소자의 미세패턴 형성방법을 도시한 공정 단면도이고, 도 1d 는 도 1c 의 ⓐ부분을 상세하게 도시한 도면이고, 2a 내지 도 2c 는 종래기술에 따른 반도체소자의 미세패턴 형성방법에 의해 형성된 감광막패턴의 프로파일을 나타낸 사진으로서 서로 연관지어 설명한다.1A to 1C are cross-sectional views illustrating a method of forming a micropattern of a semiconductor device according to the prior art, FIG. 1D is a detailed view of part ⓐ of FIG. 1C, and FIGS. 2A to 2C are conventional semiconductors. A photograph showing the profile of the photosensitive film pattern formed by the method for forming a micropattern of the device will be described in association with each other.
먼저, 웨이퍼(11) 상부에 피식각층(13)을 형성한다. 이때, 상기 피식각층(13)은 산화막 및 질화막 등의 절연층이 사용될 수 있다.First, an etching target layer 13 is formed on the wafer 11. In this case, an insulating layer such as an oxide film and a nitride film may be used as the etched layer 13.
다음, 상기 피식각층(13) 상부에 감광막(15)을 도포한다. 이때, 상기 감광막(15)은 용해억제형 또는 화학증폭형 감광막으로서, 포지티브형 감광막이 사용된다.Next, a photosensitive film 15 is coated on the etched layer 13. At this time, the photosensitive film 15 is a dissolution inhibiting or chemically amplified photosensitive film, a positive photosensitive film is used.
그 다음, 패턴으로 예정되는 부분을 보호하는 노광마스크(17)를 이용하여 노광공정을 실시한다. 이때, 상기 노광마스크(17)에 노출되는 부분의 선폭은 'x'로 가정한다. (도 1a 참조)Next, the exposure process is performed using the exposure mask 17 which protects the part scheduled by a pattern. In this case, it is assumed that the line width of the portion exposed to the exposure mask 17 is 'x'. (See Figure 1A)
다음, 상기 감광막(15)의 노광된 부분을 현상공정으로 제거하여 감광막패턴(19)을 형성한다. 이때, 상기 현상공정으로 제거된 부분의 선폭은 'x'로 형성된다. (도 1b 및 도 2a 참조)Next, the exposed portion of the photosensitive film 15 is removed by a developing process to form the photosensitive film pattern 19. At this time, the line width of the portion removed by the developing step is formed as 'x'. (See FIGS. 1B and 2A)
그 다음, 상기 웨이퍼(11)를 오븐에 장착하고 베이크 공정을 실시하여 상기 웨이퍼(11) 상에 형성된 감광막패턴(19)을 플로우시킨다. 이때, 상기 베이크 공정은 120 ∼ 200℃의 온도범위에서 20 ∼ 150 초간 실시되고, 상기 플로우된 감광막패턴(21)이 노출시키는 콘택 영역의 선폭은 'y'로 플루우 전의 선폭보다 좁아진다(x>y).Next, the wafer 11 is mounted in an oven and a baking process is performed to flow the photoresist pattern 19 formed on the wafer 11. At this time, the baking process is performed for 20 to 150 seconds in the temperature range of 120 to 200 ℃, the line width of the contact region exposed by the flow photosensitive film pattern 21 is 'y' narrower than the line width before the flow (x > y).
여기서, 상기 플로우된 감광막패턴(21)이 노출시키는 콘택 영역의 선폭은 상측(y) 및 하측(z)의 크기가 같게 형성되어야 이상적이다. (도 1c 참조)Here, the line width of the contact region exposed by the flow photosensitive film pattern 21 is ideal when the upper (y) and the lower (z) have the same size. (See Figure 1C)
그러나, 상기 플로우된 감광막패턴(21)의 ⓐ부분을 상세하게 도시한 도면으로서, 플로우공정 시 감광막패턴(21)의 상측에서 흘러내리려는 힘과 확장하려는 힘인 추력(F)이 크게 작용하여 오버행(overhang)이 발생하고, 그로 인하여 플로우된 감광막패턴(21) 콘택 영역의 상측(y) 선폭이 하측(z) 선폭보다 작게 형성된다(y<z).However, as shown in detail ⓐ portion of the flow of the photosensitive film pattern 21, the thrust (F), which is a force to extend from the upper side of the photosensitive film pattern 21 and the force to expand during the flow process acts largely overhang ( overhang occurs, whereby the upper (y) line width of the flow-sensitive photoresist pattern 21 contact region is formed smaller than the lower (z) line width (y <z).
도 2b 는 감광막패턴을 플로우시켜 오픈영역을 50㎚ 축소시킨 경우이고, 도 2c 는 70㎚ 축소시킨 경우를 나타내며, 축소 정도가 클수록 감광막패턴의 프로파일이 변형이 심해진다.FIG. 2B shows a case where the open region is reduced by 50 nm by flowing the photoresist pattern, and FIG. 2C shows a case where the open region is reduced by 70 nm.
상기한 바와 같이 종래기술에 따른 반도체소자의 미세패턴 형성방법은, 미세패턴을 형성하기 위하여 노광 및 현상공정으로 감광막패턴을 형성한 다음, 고온의 오븐에서 베이크공정을 실시하여 감광막패턴의 콘택 영역을 축소시켰으나, 축소 정도가 50㎚ 이상인 경우 감광막패턴의 프로파일이 심하게 변형되고, 그로 인하여 원하는 패턴을 형성할 수 없으며 측정 상의 문제를 일으켜 공정의 재현성을 저하시키는 동시에 반도체소자의 고집적화를 저해하는 문제점이 있다.As described above, in the method of forming a micropattern of a semiconductor device according to the related art, a photoresist pattern is formed by an exposure and development process to form a micropattern, and then a baking process is performed in a high temperature oven to form a contact region of the photoresist pattern. However, when the degree of reduction is 50 nm or more, the profile of the photoresist pattern is severely deformed, and thus, a desired pattern cannot be formed, which causes a problem in measurement, thereby reducing the reproducibility of the process and at the same time inhibiting the high integration of semiconductor devices. .
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 감광막패턴의 표면에 자외선 또는 전자빔을 조사하여 경화시킨 후 열처리를 실시하여 플로우시킴으로써 상기 감광막패턴의 플로우 시 추력을 분산시켜 감광막패턴의 프로파일이 변형되는 것을 방지하는 반도체소자의 미세패턴 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the surface of the photoresist pattern is irradiated with ultraviolet rays or electron beams and cured, followed by heat treatment to flow the photoresist pattern so that the thrust is dispersed during the flow of the photoresist pattern. It is an object of the present invention to provide a method for forming a micropattern of a semiconductor device which is prevented from being made.
도 1a 내지 도 1c 는 종래기술에 따른 반도체소자의 미세패턴 형성방법을 도시한 공정 단면도.1A to 1C are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device according to the prior art.
도 1d 는 도 1c 의 ⓐ부분을 상세하게 도시한 도면.FIG. 1D illustrates a detail ⓐ portion of FIG. 1C; FIG.
도 2a 내지 도 2c 는 종래기술에 따른 반도체소자의 미세패턴 형성방법에 의해 형성된 감광막패턴의 프로파일을 나타낸 사진.2A to 2C are photographs showing a profile of a photoresist pattern formed by a method for forming a micropattern of a semiconductor device according to the prior art.
도 3a 내지 도 3c 는 본 발명에 따른 반도체소자의 미세패턴 형성방법을 도시한 공정 단면도.3A to 3C are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device according to the present invention.
도 3d 는 도 3c 의 ⓑ부분을 상세하게 도시한 도면.FIG. 3D is a detailed view of ⓑ of FIG. 3C.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11, 31 : 웨이퍼 13, 33 : 피식각층11, 31: wafer 13, 33: etching layer
15 : 감광막 17 : 노광마스크15 photosensitive film 17 exposure mask
19, 35 : 감광막패턴 21, 39 : 플로우된 감광막패턴19, 35: photoresist pattern 21, 39: flow photoresist pattern
37 : 감광막패턴의 경화된 부분37: hardened portion of the photosensitive film pattern
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 미세패턴 형성방법은,In order to achieve the above object, the method of forming a fine pattern of a semiconductor device according to the present invention,
웨이퍼 상부에 피식각층을 형성하는 공정과,Forming an etching target layer on the wafer;
상기 피식각층 상부에 감광막을 도포하는 공정과,Coating a photoresist film on the etched layer;
콘택영역을 노출시키는 콘택마스크를 이용한 사진공정으로 상기 감광막을 노광 및 현상하여 감광막패턴을 형성하는 공정과,Forming a photoresist pattern by exposing and developing the photoresist by a photolithography process using a contact mask exposing a contact region;
상기 감광막패턴의 표면을 경화시키는 공정과,Curing the surface of the photosensitive film pattern;
상기 감광막패턴을 베이크하여 플로우시킴으로써 상기 감광막패턴 간의 간격을 축소시키는 공정과,Reducing the gap between the photoresist pattern by baking and flowing the photoresist pattern;
상기 감광막은 용해억제형 또는 화학증폭형 감광막인 것과,Wherein the photosensitive film is a dissolution inhibiting or chemically amplified photosensitive film,
상기 감광막은 포지티브형 감광막인 것과,The photosensitive film is a positive photosensitive film,
상기 감광막패턴의 표면을 경화시키는 공정은 상기 감광막패턴의 표면에 자외선 또는 전자빔을 조사하여 실시되는 것과,The step of curing the surface of the photosensitive film pattern is carried out by irradiating the surface of the photosensitive film pattern with ultraviolet or electron beam,
상기 자외선 또는 전자빔은 15 ∼ 150℃의 온도 및 0.5 ∼ 20mTorr의 진공챔버 내에서 조사되는 것과,The ultraviolet or electron beam is irradiated in a vacuum chamber at a temperature of 15 to 150 ℃ and 0.5 to 20mTorr,
상기 자외선 또는 전자빔은 0 ∼ 45。의 각도 및 0.05 ∼ 20uC의 에너지를 사용하여 조사되는 것과,The ultraviolet or electron beam is irradiated using an angle of 0 to 45 ° and energy of 0.05 to 20uC,
상기 감광막패턴 간의 간격은 50 ∼ 100㎚ 만큼 축소되는 것과,The interval between the photosensitive film pattern is reduced by 50 to 100nm,
상기 베이크공정은 120 ∼ 200℃의 온도에서 20 ∼ 150초간 실시되는 것과,The baking step is carried out for 20 to 150 seconds at a temperature of 120 to 200 ℃,
상기 패턴은 콘택홀 또는 금속배선인 것을 특징으로 한다.The pattern may be a contact hole or a metal wiring.
본 발명의 원리는 감광막패턴의 표면에 자외선 또는 전자빔을 조사하여 경화시킨 후 플로우 공정을 실시함으로써 감광막패턴의 흘러내리려는 힘과 확장하려는힘인 추력(F)이 감광막패턴의 상측 및 하측에서 균일하게 작용하도록 하여 감광막패턴의 프로파일 변형을 방지하는 것이다.The principle of the present invention is to irradiate and harden the surface of the photoresist pattern by irradiating ultraviolet rays or electron beams and then perform a flow process so that the thrust force F, which is the force to flow down and the force to expand, is uniformly applied to the upper and lower sides of the photoresist pattern. This is to prevent the deformation of the profile of the photoresist pattern.
이하, 첨부된 도면을 참고로 하여 본 발명에 따른 반도체소자의 미세패턴 형성방법에 대하여 상세히 설명한다.Hereinafter, a method of forming a fine pattern of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3c 는 본 발명에 따른 반도체소자의 미세패턴 형성방법을 도시한 공정 단면도이고, 도 3d 는 도 3c 의 ⓑ부분을 상세하게 도시한 도면이다.3A to 3C are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device in accordance with the present invention, and FIG. 3D is a detailed view illustrating ⓑ of FIG. 3C.
먼저, 웨이퍼(31) 상부에 피식각층(33)을 형성한다. 이때, 상기 피식각층(33)은 산화막 및 질화막 등의 절연층이 사용될 수 있다.First, an etching target layer 33 is formed on the wafer 31. In this case, an insulating layer such as an oxide film and a nitride film may be used as the etching target layer 33.
다음, 상기 피식각층(33) 상부에 감광막(도시안됨)을 도포한다. 이때, 상기 감광막은 용해억제형 또는 화학증폭형 감광막으로서, 포지티브형 감광막이 사용된다.Next, a photosensitive film (not shown) is applied on the etched layer 33. At this time, the photosensitive film is a positive type photosensitive film as a dissolution inhibiting or chemically amplified photosensitive film.
그 다음, 패턴으로 예정되는 부분을 보호하는 노광마스크(도시안됨)를 이용하여 노광공정을 실시한다. 이때, 상기 노광마스크에 노출되는 부분의 선폭은 'x'로 가정한다.Next, an exposure process is performed using an exposure mask (not shown) that protects a portion intended as a pattern. In this case, the line width of the portion exposed to the exposure mask is assumed to be 'x'.
다음, 상기 감광막의 노광된 부분을 현상공정으로 제거하여 콘택 영역을 노출시키는 감광막패턴(35)을 형성한다. 이때, 상기 현상공정으로 제거된 콘택 영역의 선폭은 'x'로 형성된다. (도 3a 참조)Next, the exposed portion of the photoresist film is removed by a developing process to form a photoresist pattern 35 exposing the contact region. In this case, the line width of the contact region removed by the developing process is formed as 'x'. (See Figure 3A)
그 다음, 상기 감광막패턴(35)이 형성되어 있는 웨이퍼(31)를 진공 챔버 내에 장착시킨 후 자외선 또는 전자빔을 전면적으로 조사하여 상기 감광막패턴(35)의 표면을 경화시킨다. 일반적으로 감광막이 자외선 또는 전자빔에 노출되면 경화되는특성을 갖고 있다.Next, the wafer 31 on which the photoresist pattern 35 is formed is mounted in a vacuum chamber, and then irradiated with ultraviolet rays or electron beams on the entire surface to harden the surface of the photoresist pattern 35. In general, the photosensitive film has a property of curing when exposed to ultraviolet rays or electron beams.
이때, 상기 진공 챔버는 0.5 ∼ 10mTorr의 압력과 15 ∼ 150℃의 온도를 유지시키고, 상기 자외선 또는 전자빔은 0 ∼ 45。의 각도 및 0.05 ∼ 20uC의 에너지를 사용하여 조사된다.At this time, the vacuum chamber is maintained at a pressure of 0.5 ~ 10mTorr and a temperature of 15 ~ 150 ℃, the ultraviolet or electron beam is irradiated using an angle of 0 ~ 45 ° and energy of 0.05 ~ 20uC.
다음, 상기 웨이퍼(31)를 오븐에 장착하고 베이크공정을 실시하여 상기 감광막패턴(35)을 플로우시킨다. 이때, 상기 베이크 공정은 120 ∼ 200℃의 온도범위에서 20 ∼ 150 초간 실시되고, 상기 플로우된 감광막패턴(39)이 노출시키는 콘택 영역의 선폭은 'y'로 플로우 전의 선폭보다 좁게 형성된다(x>y).Next, the wafer 31 is mounted in an oven, and a baking process is performed to flow the photoresist pattern 35. At this time, the baking process is performed for 20 to 150 seconds in the temperature range of 120 to 200 ℃, the line width of the contact region exposed by the flow photosensitive film pattern 39 is formed to be 'y' narrower than the line width before the flow (x > y).
상기 베이크공정 시 상기 감광막패턴의 경화된 부분(37)에 의해 감광막패턴(35)의 추력(F)이 감광막패턴(35)의 상측 및 하측으로 분산되어(G) 플로우된 감광막패턴(39)의 프로파일이 변형되는 것을 억제한다.The thrust F of the photoresist pattern 35 is dispersed to the upper and lower sides of the photoresist pattern 35 by the hardened portion 37 of the photoresist pattern during the baking process (G). Suppress the deformation of the profile.
상기 베이크공정으로 상기 감광막패턴(35)의 콘택 영역을 50 ∼ 100㎚ 축소시킬 수 있다. (도 3c 및 도 3d 참조)The baking process may reduce the contact area of the photoresist pattern 35 by 50 to 100 nm. (See Figures 3C and 3D)
한편, 도시되어 있지는 않지만 다른 실시예로서 다마신 방법을 이용한 금속배선 형성방법에 감광막패턴 간의 간격을 축소시키는 방법이 사용될 수도 있다.On the other hand, although not shown, a method of reducing the gap between the photoresist pattern may be used in the metal wiring forming method using the damascene method as another embodiment.
이상에서 살펴본 바와 같이, 본 발명에 따른 반도체소자의 미세패턴 형성방법은 콘택홀 형성공정 시 콘택영역을 노출시키는 감광막패턴을 형성하고, 상기 감광막패턴의 표면에 자외선 또는 전자빔을 조사하여 경화시킨 후 플로우공정을 실시하여 감광막패턴의 추력을 상측 및 하측으로 분산시켜 감광막패턴의 프로파일이 변형되는 것을 방지함으로써 소자의 재현성을 향상시키고 그에 따른 반도체소자의 고집적화를 유리하게 하는 이점이 있다.As described above, in the method of forming a micropattern of a semiconductor device according to the present invention, a photoresist pattern is formed to expose a contact region during a contact hole forming process, and the surface of the photoresist pattern is irradiated with ultraviolet rays or an electron beam to cure and then flowed. By performing the process, the thrust of the photoresist pattern is dispersed to the upper side and the lower side, thereby preventing the profile of the photoresist pattern from being deformed, thereby improving the reproducibility of the device and consequently increasing the integration of the semiconductor device.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009114244A2 (en) * | 2008-03-11 | 2009-09-17 | Lam Research Corporation | Line width roughness improvement with noble gas plasma |
| CN109285763A (en) * | 2017-07-19 | 2019-01-29 | 东京毅力科创株式会社 | Substrate board treatment, substrate processing method using same and storage medium |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009114244A2 (en) * | 2008-03-11 | 2009-09-17 | Lam Research Corporation | Line width roughness improvement with noble gas plasma |
| WO2009114244A3 (en) * | 2008-03-11 | 2009-11-05 | Lam Research Corporation | Line width roughness improvement with noble gas plasma |
| US8753804B2 (en) | 2008-03-11 | 2014-06-17 | Lam Research Corporation | Line width roughness improvement with noble gas plasma |
| US9263284B2 (en) | 2008-03-11 | 2016-02-16 | Lam Research Corporation | Line width roughness improvement with noble gas plasma |
| US9466502B2 (en) | 2008-03-11 | 2016-10-11 | Lam Research Corporation | Line width roughness improvement with noble gas plasma |
| CN109285763A (en) * | 2017-07-19 | 2019-01-29 | 东京毅力科创株式会社 | Substrate board treatment, substrate processing method using same and storage medium |
| KR20190009703A (en) * | 2017-07-19 | 2019-01-29 | 도쿄엘렉트론가부시키가이샤 | Substrate processing apparatus, substrate processing method, and storage medium |
| CN109285763B (en) * | 2017-07-19 | 2023-10-20 | 东京毅力科创株式会社 | Substrate processing apparatus, substrate processing method, and storage medium |
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