JPS61292375A - Thin film transistor - Google Patents

Abstract

PURPOSE:To obtain a chemically stable electrode by providing an inert metal on the uppest layer of the drain or source electrode. CONSTITUTION:An insulation film 12, an amorphous silicon film 13 layer are formed on the gate electrode 17 evaporated on a glass substrate 10. Then, an Al layer S1, a Ti layer S2, and an Au layer S3 are evaporated respectively. The Au layer S3 has a patterned resist as a mask and etched with an etchant consisting of iodine, ammonium iodide, ethanol, and water. The Ti layer S2 and the Al layer S1 are etched with the Au layer S3 as a mask so as to form a source electrode 15' and a drain electrode 14'. When those electrodes was kept in the atmosphere with moisture of 90% at a temperature of 60 deg.C, the resistance of the electrodes was scarcely changed and stable.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a thin film transistor (hereinafter referred to as TPT).

(#Conventional technology In recent years, liquid crystal display panels for displaying TV images have appeared in which thin film transistors are arranged in a matrix in a panel circle.For example, Nikkei Electronics #1982 12
For details, see the article in the May 7th issue, ``Research on 81 thin film transistors for liquid crystal displays is gaining momentum.''

The flat surface of the main part of such a liquid crystal display panel is caused by the third factor (a) t.
= shown, same figure φ]≦: shows its XX/ line cross-sectional view.

In these figures (2), mouse is on the first glass substrate, and ■ is on the first glass substrate CII. Transparent electrode, (13-... is the transparent electrode <Ll) (Lll... gap is 1 in the vertical direction; a plurality of amorphous silicon films arranged in parallel, and provided on insulation Mα4.I . . . are drain lines made of aluminum films arranged vertically (two or more in parallel) in a state that they are partially overlapped on the left side of each amorphous silicon ff1 (13-) via the C2 insulating film α2.

(L51aω... is each amorphous silicon film α3)
-... on the right side C: Insulating film (partially overlapped through 1z, and in the next state each transparent electrode αDαυ...C: Source electrode film consisting of a correspondingly arranged aluminum film; its right side is It is connected to the lower left end of each transparent electrode (11) (lυ). A gate line consisting of a two-layer film of gold and chromium formed between the glass substrate (1 (1) and the insulating film U, and the line U
bJ...C2 is an amorphous silicon film located in the gap between each of the source electrodes α4... and the drain line α4... and the lower gate is integrally formed with the polar film ση...C;
It is formed. That is, the train line a shown in the figure
4... The drain electrode film at locations, the source electrode film α shown by S, and the gate electrode film η shown by G,
These electrode films, 51Gc bonded amorphous silicon film (L3... location and C binary value) constitute a switching transistor consisting of TFT, and each transparent electrode αυ (11J... !1) is connected to the drain line I・− through the corresponding switching transistor.
. . . and the drain line (14) .

On the other hand, (to) is the second glass substrate, and its lower surface, that is, the surface C2 facing the glass substrate μ of fJl is one surface C:
A common electrode 21J and an alignment film are sequentially formed.

(3) is a liquid crystal substance sealed in both substrates, and for each matrix segment ≦: the TPT is turned on @C; therefore, the transparent electrode α point of the first glass substrate 4 to which a voltage is applied The liquid crystal material (5) causes an electro-optical effect, and 11 images can be displayed on the entire panel.

eC Problems to be Solved by the Invention In general, aluminum A, or a small amount of silicon St, titanium T, is used as an ohmic electrode for a semiconductor C whose main material is silicon.
11 AI added with copper Cu, etc.! Since an alloy is used, even in TPT+2 as mentioned above, both electrodes (13 (141 is an AI! layer) are formed with respect to the amorphous silicon film aJ.However, AI! or AI! alloy is chemically (TFT) is active and reacts with water, oxygen, organic solvents, etc., corrodes or becomes an insulating compound (e.g. alumina), and has a chemically dianxious element.
t-Liquid crystal display panel (: TFT top layer if used)
AI of two source electrodes α fathom and drain electrode α$!
reacts with the liquid crystal or impurities in the liquid crystal (H20%02, etc.) and deteriorates over time, resulting in both electrodes made of AI! (there is a problem that the ohmic resistance of the 14α increases).As a solution to this, AI! It is conceivable to use an inert metal layer such as gold Au as both electrodes α4α9.

However, both electrodes α4αS are placed on the A7 layer (-single (:Au
In the case of a two-layer structure with layers, the Au layer has a predetermined shape C
; When etching C; Underlayer AI! A phenomenon in which the layer is significantly side-etched occurs, resulting in a disadvantage that the patterning accuracy of the c-source electrode I and the drain electrode film is reduced. That is, aqua regia as an etchant for the AU layer,
Although hydrogen etchants are available, they all side-etch the AJ layer, resulting in partial peeling of the Au layer.

B) Means for Solving the Problems The TPT of the present invention has at least one of the drain electrode array C and the source electrode made of Al or AI! It has a three-layer structure of alloy, titanium, and inert metal.

(e) Effect ffj4 T F T c X Shiba, AI! -T
Since an electrode with an i-Au(7) three-layer structure is used, when aqua regia is used as an etchant, the underlying metal as well as the Au are attacked, making microfabrication difficult. At the time, the base metal Al-Ti1 did not attack.
: Only Au was selectively etched. The details of this reason are unknown, but in general, iodine etchants are
I! AJt in contact with Au hardly etches alone, and when it is significantly etched or buttered, the Ti, A,/layer is etched by A with an acid-based etchant such as phosphoric acid.
It can be easily processed as a ut-mask. That is, l
By introducing a cTi layer between / and Au and using an iodine etchant, it is possible to process with high precision.

(to) 5! Embodiment FIG. 1C shows a sectional view of the TPT of the present invention, and the TFT+ of the present invention will be described in detail below based on section 2 of the figure.

5iOzt-μ on coated glass substrate C1O
Cr2 was vaporized and etched into a predetermined shape with a mixed solution of ceric ammonium nitrate and perchloric acid to form a gate electrode ση. On top of this, a silicon nitride insulating film layer, an amorphous silicon film t13 layer is provided, and a silicon nitride insulating film U is an elastomer) HF
-NH4F (double etching molding, amorphous silicon III (13 is etchant HF-HNO3-
CH5COOH (double etching molding. Then,
The A/layer (81), the T1 layer (S2), and the Au layer (S3) are sequentially deposited.

The third Au layer (Sg) is patterned by photolithography and then coated with a resist (e.g. AZ-1350Ji).
Use it as a mask and etch it with an iodine etchant consisting of iodine, ammonium iodide, ethanol, and water.
(-This top layer of Au layer (f3s) @80 as a mask
The Ti layer (-8s) and the A47 layer (S1) were etched in phosphoric acid at °C to form source electrode 0 and drain electrode aet-
It forms.

Next cAI! -Ti-Au1! To see the pole [14) αsco stability 'r ≦;, on the glass substrate 6; conventional AJ1
! Polar and present invention 03kI! -Ti-Au electrode '2i 5μ
Create a marking surface model formed by the line width and set it at a temperature of 6O.
When stored in a humid environment of 90 degrees centigrade, Figure 2 (as shown in Figure 2)
l! Although the resistance of the electrode increased, AI! -Ti-Au electrode has very little change in resistance and is very stable.

(G) Effect Since the TPT of the present invention has a three-layer structure of the drain electrode and at least one of the two source electrodes, t-1hli or A/gold alloy titanium, and an inert metal, for example, an iodine-based etchant can be used. When etching an inert metal, there is no t-id etching of the lower metal, and as a result, the processing accuracy of the electrode is improved by two times. Furthermore, due to the presence of the inert metal in the top layer, a chemically stable electrode can be obtained, and therefore, when used in, for example, a liquid crystal display panel C, there is no adverse effect on the liquid crystal material.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of the TPT of the present invention, and the second cause is the JTF of the present invention.
T's AI! -'ri -Au electrode and conventional) AI! Time-dependent characteristic diagram with ta, @51W (aJ(b) is TPT=
FIG. 2 is a plan view and a cross-sectional view of a secondary liquid crystal display panel.

Claims (1)

[Claims] 1) A thin film transistor in which a gate electrode, an insulating film, a semiconductor film, a drain electrode, and a source electrode are sequentially laminated on an insulating substrate, in which at least one of the drain electrode and the source electrode is made of aluminum or an aluminum alloy. A thin film transistor characterized by having a three-layer structure in which a first metal layer is titanium as a second metal layer, and an inert metal such as gold, platinum, palladium or the like as a third metal layer. 2) Claim 1, characterized in that the third metal layer, which is an inert metal, is etched into a predetermined shape with a mixed solution of iodine and ammonium iodide, or a mixed solution of iodine, ammonium iodide, and ammonia. The thin film transistor described.