JPS61292297A - Ic inspecting device - Google Patents

Abstract

PURPOSE:To perform the inspection of an IC memory at high speed by impress ing data share of two cycles on the IC memory in one cycle of an inspecting device main body and performing two times of decision in one cycle. CONSTITUTION:A function test controller 3 outputs a timing signal TMG having a doubled frequency and a decision strobe signal DS and operates an impressing part 4 and a deciding part 5 with the frequency doubled as much as an existing one. Multiplexers 7a and 7b separate a test data DATA of 16 bits and an expected value E supplied from the controller 3 to high-order eight bits and low-order eight bits and supplies them to the impressing part 4 and the detecting part 5. The low-order eight bits D0-D7 and the high-order bits D8-D15 of the test data DATA are impressed on IC memories 10a and 10b respectively as the first half data and the last half data and the test data share of two cycles are impressed on a device to be measured during one cycle of the control ler 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technology for testing semiconductor integrated circuits, and relates to a technology that is effective for use in, for example, testing equipment for semiconductor storage devices (hereinafter referred to as IC memories).

[Background Art] Conventionally, an apparatus as shown in FIG. 3 has been provided as an IC memory inspection apparatus.

That is, in this testing device, the function test controller 3 performs tests necessary for testing the IC memory based on the test pattern TP supplied from the pattern generator 1 and the timing clock CK supplied from the timing generator 2. Test data DAT such as write data
A and a timing signal TMG such as an address signal, a chip select signal, and a write enable signal.

Then, these data DATA and timing signal TM
G is applied to the IC memory 10 by the application unit 4, and the data read out from the IC memory IO by this is applied to the determination unit 5 in synchronization with the determination strobe signal DS supplied from the controller 3. By comparing with the expected value E also supplied from the controller 3, it is checked whether the IC memory operates normally.

The above-mentioned testing device is described in the rT3332 Memory Test System General Specifications published by Takeda Riken Kogyo Co., Ltd. in March 1984.

In addition, in the above inspection device, the pattern generator l operates one at a time.
It is possible to generate an 8-bit data pattern, and the function test controller 3 and judgment unit 5 also have 18 bits.
It is designed to handle bit data.

Therefore, when testing, for example, an 8-bit IC memory using the above testing apparatus, devices under test 10a and 10b are arranged in parallel as shown in FIG. By applying test data (upper 8 bits and lower 8 bits), two IC memories can be tested simultaneously. Therefore, this improves inspection efficiency.

However, there is a limit to the operating frequency of the above-mentioned testing equipment, and even though faster testing is required from the IC memory side, the speed of the testing equipment is limited, making it impossible to perform testing. was there.

In addition, in order to increase the inspection speed with the system configuration described above, it is necessary to increase the operating frequency of the pattern generator 1 and function test controller 3, but this would require the hardware of each device to become large-scale. Become,
There is a problem that the cost of the entire inspection device increases.

[Object of the Invention] An object of the present invention is to provide a testing technique that can test an IC memory at twice the speed of a conventional testing device without significantly changing the hardware.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

In other words, test data and expected values formed based on a test pattern are divided in a multiplexer according to the number of bits of the device under test, and the multiplexer is used in a time-division manner and at a frequency that is more than twice the operating frequency of the test equipment itself. By driving the test data and expected values to be supplied to the device under test and the determination section, data for two cycles can be applied to the IC memory during one cycle of the test equipment main body, and This method achieves the above object of making it possible to test an IC memory twice as fast as the conventional method by performing the determination twice in a cycle.

The present invention will be described in detail below along with examples.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to an IC memory testing device.

The inspection apparatus of this embodiment has a main body composed of a pattern generator 1, a timing generator 2, and a function test controller 3, similar to the conventional inspection apparatus shown in FIG. In this embodiment, multiplexers 7a, 7
b is connected, and the test data DATA and expected value E output from the function test controller 3
is supplied to the application section 4 and the determination section 5 via multiplexers 7a and 7b.

Although not particularly limited, in this embodiment, a 16-bit test pattern is generated from the pattern generator 1, which will be described below. The supplied 16-bit test data DATA and expected value E are divided into upper 8 bits and lower 8 bits, and first, the lower 8 bits that are input are output as data for the first half in the form of 16-bit data in the upper and lower parts. and supplies it to the application section 4 and determination section 5. In addition, the output of the function test controller 3 is
The upper 8 bits of the test data DATA and the expected value E are held while the multiplexers 7a and 7b output the lower 8 bits.・16 in the bottom
The data is output in the form of bit data and can be supplied to the application section 4 and the determination section 5, respectively.

The test data DATA supplied to the application section 4 is waveform-shaped in the application section and applied to the two devices under test (IC memories) 10a and 10b.

In other words, the lower 8 of the 16-bit test data DATA output from the function test controller 3
Bits DO to D7 and upper 8 bits Dθ to D16 are stored in two IC memories (10
a and 10b).

Furthermore, in this embodiment, based on the timing clock CK supplied from the timing generator 2, the function test controller 3 operates the application unit 4 and the determination unit 5 in the conventional inspection apparatus shown in FIG. The timing signal TMG and the determination strobe signal DS having twice the frequency of the various timing signals TMG and the determination strobe signal DS which are supplied to the circuit are formed and output.

Then, the multiplexer 7a and the application section 4 are driven by the timing signal TMG of twice the frequency, and the multiplexer 7b and the determination section 5 are driven by the determination strobe signal DS, and the application section 4 in the conventional inspection apparatus (FIG. 3) is driven.
It operates at twice the operating frequency of the determining section 5.

Note that the multiplexers 7a and 7b, the application section 4° and the determination section 5
etc., the pattern generator l or function
It is possible to drive at a sufficiently higher frequency than the test controller 3. Therefore, the pattern generator 1 and the functional test controller 3 can be operated at the same frequency as in the conventional inspection device, while the application section 4 and the determination section 5 can be operated at twice the frequency of the conventional inspection device.

As a result, the 16-bit test data DATA output from the function test controller 3 is divided into two parts, the first half data DO to D7 and the second half data D8 to D16, as shown in FIG. device 1
It can be applied to 0a and 10b. As a result, two cycles worth of test data are applied to the device under test during one cycle of the function test controller 3. Also, the device under test 10a.

The data outputted from 10b is compared with two expected values taken in from multiplexer 7b twice during one cycle of function test controller 3 by judgment unit 5 to make a judgment.

Therefore, according to this embodiment, multiplexers 7a and 7b
By simply adding
C memory can be checked.

In the above embodiment, a case has been described in which an 8-bit IC memory is measured in an inspection apparatus equipped with a pattern generator capable of generating a 16-bit test pattern, but an IC memory with a 4-bit configuration is also tested. In this case, the multiplexer 7a divides the test data DATA into four parts and supplies them to four IC memories in a time-sharing manner, and the multiplexer 7b divides the expected value E into four parts.
It is divided and supplied to the determination section 5. Then, the applying section 4, the determining section 5, and the multiplexers 7a and 7b.

The function test controller 3 is operated at a frequency four times higher than its operating frequency. As a result, it is possible to test IC memories four times faster than conventional testing equipment.Furthermore, in testing equipment equipped with a pattern generator that can generate 16-bit test patterns, it is possible to test IC memories with a 16-bit configuration. When measuring , it is possible to perform the inspection at twice the speed of conventional inspection equipment by doing the following.

That is, in this case, multiplexer 7a.

As a function of 7b, 16-bit test data DAT supplied from the function test controller 3
A function that sends A and the expected value E as they are to the application section 4 and the judgment section 5, and the lower 8 bits D of the test data DATA and the expected value E.
0 to D7 and the upper 8 bits Da to fa1s are exchanged and supplied to the application section 4 and the determination section 5, and the switching is performed by the timing signal TMG from the function test controller 3. The multiplexers 7a and 7b are operated at twice the operating frequency of the pattern generator 1 and the function test controller 3. The other configurations are the same as shown in FIG. However, in this case, the application section 411 constant section 5
There is only one device under test connected to.

As a result, during one cycle of the function test controller 3, two types of test data (the test data DATA itself and the one with the upper and lower bits swapped) are sent from the multiplexers 7a and 7b to the application section 4 and the judgment section 5. test data will be provided.

As a result, it is possible to test a 16-bit IC memory at twice the speed of the conventional testing device shown in FIG.

[Effect] The test data and expected values formed based on the test pattern are divided in a multiplexer according to the number of bits of the device under test, and the test data and expected values are divided in a multiplexer according to the number of bits of the device under test. Since the multiplexer is driven to supply test data and expected values to the device under test and the judgment section, two cycles worth of data is applied to the IC memory during one cycle of the test equipment main body, and one The effect of performing the determination twice per cycle has the effect that IC memory can be tested twice as fast as in the past without making any major changes to the hardware.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above example,
Although the pattern generator 1 is designed to generate a 16-bit test pattern, the test pattern is not limited to 16 bits, but may be 8 bits, 32 bits, or any other number of bits.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to the field of application for IC memory, which is the background of the invention. It can be used for other LSI inspection devices in general. INDUSTRIAL APPLICATION This invention can be utilized for the test|inspection apparatus which performs the test|inspection using a test pattern at least.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to an IC memory testing device. FIG. 2 is an explanatory diagram showing a test I-data supply method in the embodiment. FIG. 3 is a block diagram showing an example of a conventional IC memory testing device, and FIG. 4 is a block diagram showing another method of using the testing device. DESCRIPTION OF SYMBOLS 1... Pattern generator, 2... Timing generator, 3... Control section (function test controller), 4... Application section, 5... Judgment section, 7
a, 7b” multiplexer, 10.10a. 10b...Device under test (IC memory).

Claims (1)

[Claims] 1. A pattern generator that generates a test pattern, a timing generator that generates a timing clock, and test data, expected values, and control signals for the device under test based on the test pattern and timing clock. a control unit that forms and outputs the test data, an application unit that applies the test data and a predetermined control signal to the object to be measured, and a signal read from the object to be measured and an expected value supplied from the control unit. What is claimed is: 1. An IC testing device comprising: a determining section for comparing and determining; and a multiplexer is provided between the control section, the applying section, and the determining section, respectively. 2. The pattern generator is capable of generating a test pattern with a number of bits that is twice or more than the number of bits of test data required for the device under test, and the multiplexer is configured to generate test patterns each supplied from the control section. 2. The IC testing device according to claim 1, wherein data and expected values are held, divided into two or more parts, and can be sequentially supplied to an application section and a determination section.